Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Montero et al. US PG-Pub 2023/0281133 A1 (Montero) in view of McCormick, JR US PG-Pub 2014/0195772 (hereinafter McCormick).
As per claim 1, Montero teaches an apparatus, comprising:
a processor circuit configured to execute a translation barrier instruction, wherein to execute the translation barrier instruction (processors issuing and executing barrier instructions (ISB/DSB) for synchronization events — para. [0057]-[0060]), the processor circuit is configured to:
prevent, until after the translation barrier instruction completes, address translations for instructions that occur subsequent to the translation barrier instruction in program order (identifying and purging speculative memory access requests queued for instructions after the barrier; aborting table-walks and preventing filling of translation caches — para. [0060]–[0062], [0065]–[0067]); and
complete the translation barrier instruction based on finishing all address translations for instructions that occur prior to the translation barrier instruction in program order (barrier semantics require prior translations to complete / barrier completion gated on completion of older translations — para. [0058], [0062], [0067], [0075]);
Montero does not expressly disclose performing subsequent instructions that do not depend on a pending address translation while the translation barrier instruction remains pending.
However, McCormick teaches postponing a data-prefetch instruction that cannot execute because a required resource is unavailable without stalling following instructions. McCormick explains that the following instructions execute out of order with respect to the delayed data-prefetch instruction and continue executing while the delayed instruction waits for the required resource, see paragraph [0013];
McCormick further teaches a translation lookaside buffer for mapping virtual addresses to physical addresses and a hardware page walker that performs an address translation when a requested translation is not present in the TLB, see paragraph [0020]. McCormick explains that only prefetch instructions placed in the prefetch queue because of a TLB miss wait for the outstanding hardware page walks, whereas other instructions and pipelines may proceed, see paragraphs [0021]-[0022];
Thus, McCormick teaches performing following instructions – that is, instructions subsequent in program – that are not dependent on the pending address translation, while postponing the instruction that is waiting for completion of the TLB-miss address translation.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Montero’s processor according to McCormick so that, while an address translation for a younger instruction remains pending, the processor continues issuing an executing younger instructions that do not depend on that pending translation. Montero recognizes that outstanding address translations and long-latency table walks increase synchronization-event latency and therefore purges or prevents younger speculative translations to expediate completion of synchronization event. McCormick similarly recognizes that an instruction waiting for an unavailable resource, including a translation resulting from a TLB miss and hardware page walk, can unnecessarily stall following instructions. McCormick solves that problem by postponing the translation-dependent instruction while allowing following instructions and other pipelines to continue executing, see McCormick, paragraphs [0012]-[0013], [0020]-[0022].
Applying McCormick’s known nonblocking instruction-scheduling technique to Montero would have predictable reduced pipeline stalls and improved processor utilization during Montero’s translation-barrier operation. The modification would preserve Montero’s translation-ordering requirements because instructions dependent on unresolved translations would remain prevented from executing, while instructions that do not depend on those translations would be permitted to proceed.
As per claim 2, Montero further teaches the apparatus of claim 1, further comprising:
a set of system registers (translation control system registers and system register updates described — [0057], [0063]–[0064]); wherein to execute the translation barrier instruction, the processor circuit is configured to:
prevent, until after the translation barrier instruction completes, changes to a subset of the set of system registers that occur subsequent to the translation barrier instruction in program order (barrier ensures context‑changing operations and system register updates appearing after the barrier take effect only after barrier completes — [0058], [0064], [0068]–[0070]); and
complete the translation barrier instruction based on finishing all changes to the set of system registers that occur prior to the translation barrier instruction in program order (completion semantics tied to prior register changes being made visible — [0058], [0068]–[0070]).
As per claim 3, Montero further teaches the apparatus of claim 2, wherein the subset of system registers is the complete set of system registers (para. [0057] and [0063], system registers).
As per claim 4, Montero further teaches the apparatus of claim 2, wherein the subset of system registers are all registers that affect address translation (TTBR and translation regime registers; discussion of registers that affect translations — [0033]–[0036], [0051]–[0054], [0057]).
As per claim 5, Montero further teaches the apparatus of claim 2, wherein the subset of system registers are all registers that affect address permissions (registers affecting translation/permissions and barrier requirements — [0057], [0064], [0068]).
As per claim 6, Montero further teaches the apparatus of claim 2, wherein the subset of system registers are all registers that affect address translation or address permissions (combined disclosure of registers affecting translation and permissions — [0033]-[0036], [0057], [0064]).
As per claim 7, Montero further teaches the apparatus of claim 6, wherein the subset of system registers includes a base address register that stores a base address of a page table or a permission table (TTBR (translation table base register) and page table references — [0033]-[0036], [0051]–[0054]).
As per claim 8, Montero further teaches the apparatus of claim 1, further comprising:
one or more translation lookaside buffers (TLBs) configured to store virtual-to-physical address mappings (translation cache/TLB and page table cache described — [0004], [0033]-[0036], [0068]);
wherein to execute the translation barrier instruction, the processor circuit is configured to:
prevent, until after the translation barrier instruction completes, caching of address translations in the one or more TLBs for speculatively-executed instructions that occur subsequent to the translation barrier instruction in program order (aborting filling translation caches, purging speculative translations, marking “purged, with null-response” — [0004], [0060], [0065], [0068]-[0070]).
As per claim 9, Montero further teaches the apparatus of claim 1, wherein to prevent the address translations for the instructions that occur subsequent to the translation barrier instruction, the processor circuit is configured to stall issuance of one or more instructions that occur subsequent to the translation barrier instruction in program order (REU/LSU/MMU coordination to generate purge instructions, abort speculative translations, withhold units (IFU/LSU/REU/MMU/prefetch engine) from using speculative data — [0046]-[0047], [0060], [0068], [0074]-[0075])
As per claim 10, it is rejected for the same reasons set forth above in claim 1.
As per claims 11-13, they are rejected for the same reasons set forth above in claim 2-4.
As per claim 14, it is rejected for the same reasons set forth above in claim 6.
As per claim 15, it is rejected for the same reasons set forth above in claim 9.
As per claim 16, it’s rejected for the same reasons set forth above in claim 8.
As per claim 17, Montero teaches an apparatus, comprising:
a processor circuit that includes an instruction pipeline circuit that is configured to execute a translation barrier instruction (Processors executing barrier instructions (ISB/DSB) during synchronization events: [0057]–[0060]; Pipeline/queue context for in-order program semantics: request queues and processor units (IFU/REU/LSU/MMU) coordinating memory accesses and instruction [0068]–[0072]. These establish the instruction pipeline and how instructions are ordered/handled around barrier) wherein to execute the translation barrier instruction, the instruction pipeline circuit is configured to:
perform address translations for instructions in the instruction pipeline circuit that are older than the translation barrier instruction (barrier semantics ensure effects of context-changing operations before the barrier are visible to instructions fetched after completion; translations already in-flight (older) are allowed/finished: [0058] (ISB ensures prior operations’ effects), [0067], [0075] (completion tied to finishing prior translations), plus flow diagrams showing ongoing translations being completed: [0068]–[0070] (purge targets speculative/younger; implies older translations proceed);
decode and issue instructions that are younger than the translation barrier instruction (paragraph [0044] shows that IFU 212 is configured to “prefetch, decode, and/or prepare instructions in parallel with execution of current instructions.” Montero paragraph [0046] further teaches that REU 214 performs instruction dispatch);
prevent address translations for instructions in the instruction pipeline circuit that are younger than the translation barrier instruction (Identification and purging of speculative memory access requests queued for instructions received subsequent to the barrier; aborting table walks; not filling translation caches (TLBs/page table cache): [0060]–[0062], [0065]–[0067]. Marking speculative requests “purged, with null-response” and withholding processor units from using data: [0068]–[0070]); and
complete the translation barrier instruction based on finishing the address translations for all the instructions in the instruction pipeline circuit that are older than the translation barrier instruction (barrier completion gated on finishing prior (older) translations and making their effects visible; synchronization event completes only after earlier translations are completed: [0058], [0062], [0067], [0075]);
Montero did not specifically disclose execute instructions that are younger than the translation barrier instruction and that do not depend on a pending address translation.
However, McCormick teaches postponing an instruction waiting for an unavailable resource without stalling following instructions, allowing the following instructions to continue executing, see paragraph [0013]. McCormick further identifies the unavailable resource as virtual-to-physical address translation resulting from a TLB miss and outstanding hardware page walk, paragraph [0020]. Only instructions placed in the prefetch queue because of a TLB miss wait for completion of the outstanding hardware page walks, while other pipeline continue executing during the page walks, see paragraph [0021]-[0022].
Therefore, McCormick teaches executing younger or following instructions that do not depend on the pending address translation while withholding the instruction whose execution depends on that translation. The motivation is similar as in the rejection of claim 1.
As per claim 18, it’s rejected for the same reasons set forth above in claim 2. Further, see pipeline and register update sequencing during synchronization events in para. [0057]-[0060], [0063]-[0064].
As per claim 19, it is rejected for the same reasons set forth above in claim 6.
As per claim 20, it is rejected for the same reasons set forth above in claim 8.
Response to Arguments
Applicant's arguments filed 2/23/2026 have been fully considered but they are not persuasive. Applicant argues that Montero describes a traditional instruction synchronization barrier in which all instructions following the barrier are fetched only after the barrier has completed and, therefore, Montero does not teach performing subsequent instructions that do not depend on a pending address translation.
Applicant’s argument is not persuasive because the present rejection does not rely on Montero along for the newly added selective-execution limitation. Montero is relied upon for the translation barrier instruction, prevention of subsequent address translation, completion of prior address translations, system-register ordering, TLB operation, and the remaining limitations, as set forth in the preceding claim mappings. McCormick is relied upon for permitting instructions that are not dependent on a pending address translation to continue executing.
Specifically, McCormick teaches postponing an instruction that cannot execute because a required resource is unavailable without stalling following instructions. The following instructions continue executing while the postponed instruction waits for the required resource, McCormick, paragraph [0013].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Riocreux et al. US 8,463,966 teaches synchronizing activities of various components in distributed system.
Abhishek Raja US PG-Pub 2021/0294607 teaches processing of plural-register-load instruction
Wang et al. US PG-Pub 2020/0142829 teaches method for implementing lock-free data structures.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDRISS N ALROBAYE whose telephone number is (571)270-1023. The examiner can normally be reached Mon-Fri, 8am-4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached at 571-272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
Prosecution Insights