DETAILED ACTION
This action responds to Application No. 18/970654, filed 12/05/2024.
Claims 1-20 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/05/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The claims are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, as follows:
Claim 8, language “in response to transmitting a set number of the RFM commands to perform the read operation on the first register” (lines 6-7). This limitation is indefinite, for 2 reasons. First, the limitation “the RFM commands” lacks sufficient antecedent basis in the claims, as there is only support for “an RFM command” (e.g. claim 1, line 3). Second, it is unclear whether the limitation “to perform the read operation on the first register” is intended to limit “RFM commands”, or whether it describes what happens when the operation mode goes back to the first mode. Previous limitations of the claims describe RFM commands and performing the read operation on the first register separately, but not together; moreover, the read operation is performed on the first register is performed in the first mode (claim 8, line 2), when the RFM commands are not transmitted (claim 5, lines 4-5).
Claim 10, language “perform a read operation on the first register after operating in the second mode until the RFM command is transmitted no more than a predefined number of times, based on the risk signal being applied through the alert pin while the memory controller operates in the first mode” (lines 1-4). This limitation is indefinite, for 2 reasons. First, the language “perform a read operation on the first register” is a single, discrete action, not a continuous one; accordingly, it is not clear what it means to perform a read operation “until” the condition is met. Second, this claim is conditional on both the first register, as well as the alert pin; however, in parent claim 4, the first register and alert pin appear to be alternative embodiments performing equivalent functions. It is unclear how they work in conjunction.
Claim 15, language “transmit the RFM command based on the number of occurrences of bank activation reaching a third threshold in the first temperature range; and transmit the RFM command based on the number of occurrences of bank activation reaching a fourth threshold in the second temperature range, and” (lines 6-9). This limitation is indefinite, for 2 reasons. First, it is unclear what “in the first/second temperature range” refers to; it could mean the RFM command is transmitted based on an activation count, based on the current temperature being in the first or second range, or it could mean the RFM is transmitted when the activation count reaches a threshold inside the first or second temperature range (i.e. there is a particular temperature value in the range, and when the count equals that, the RFM is transmitted). Second, both the first refresh interval time and the third threshold are associated with the first temperature range, while the second refresh interval time and fourth threshold are associated with the second temperature range; however, it is unclear how the refresh interval times and third/fourth thresholds relate to one another; for example, it could mean that the bank activations reaching a threshold is relative to the respective refresh interval, or they could be entirely independent. As Examiner is unable to determine the intended meaning of the claimed invention, this limitation is indefinite.
Claim 16, language “sum a bank activation time of a bank, which is based on the activate command transmitted to the bank” (lines 3-4). A “sum” generally requires two or more things to be added together; summing a single thing (bank activation time) is indefinite.
Claim 17, language “increase the number of occurrences of bank activation by as much as a first value […] increase the number of occurrences of bank activation as much as a second value” (lines 2-5). This limitation is indefinite, for 2 reasons. First, it is unclear what it means to increase something “as much as” a value; it could mean 1) increasing by the value, or 2) increasing by a number up to and including the value (in other words “as much as” a value could mean “potentially less than” the value). Second, a plain reading of “the number of occurrences of the bank activation” is that it represents the actual number of bank activations; accordingly, it is unclear how the number of actual bank activations would be increased by different numbers based on delay time in response to a single activate command being transmitted, as it should presumably be increased by one to account for the newly transmitted activate command.
Claim 20, language “store flag data indicating a risky situation in the register and apply a risk signal indicating the risky situation to the alert pin” (lines 11-12). This limitation is indefinite, as it appears to conflict with the limitation “including at least one of an alert pin or a register”; this limitation only requires there to be either a pin or a register, not necessarily both; accordingly, it is unclear how the system would function to indicate risk with both the pin and the register in the situation where there is only one of them, not both.
Re claims 9-10, and 17, the claims are rejected as being dependent upon one of claims 8 and 16 above, respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cowles et al (US 2022/0113868 A1).
Re claim 1, Cowles discloses the following:
A memory system comprising: a memory device including a memory cell array (Fig. 1, memory device 111; ¶ 24). The memory device is comprised of an array of cells;
and a notification circuit (Figs. 5-7; ¶ 15-17). The memory device may set a flag or pin that is readable by the memory controller, or it may send a refresh parameter to the memory controller. Any of these are a notification circuit, as they are circuitry that notifies the memory controller;
a memory controller configured to transmit a refresh management (RFM) command to the memory device, based on a number of occurrences of bank activation of a bank included in the memory cell reaching a threshold (Figs. 5-7; ¶ 15-17). The memory controller initiates a refresh command, in response to a number of bank activations reaching a threshold, as well as a confirmation from the memory device;
wherein the memory controller is configured to control a transmission frequency of the RFM command, based on a notification obtained through the notification circuit (Figs. 5-7; ¶ 15-17). The memory controller controls how often a refresh is triggered (transmission frequency of the RFM command), based on the refresh confirmation (notification circuit);
wherein the notification comprises at least one of risk information related to a row hammer risk for rows included in the bank or temperature information of the memory device, wherein the temperature information comprises a current temperature of the memory device (Figs. 5-7; ¶ 15-17). The notification provides an indication of risk information related to a row hammer risk for rows of the bank. It is noted that this limitation only requires row hammer risk OR temperature information, and as such does not require temperature information because there is a notification of row hammer risk.
Cowles discloses the claim limitations above; however, it also discloses multiple embodiments of the claimed invention; accordingly, it is not explicitly stated whether each limitation occurs in a single embodiment; nevertheless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine the embodiments of Cowles into a single embodiment, as it would be merely making the embodiments integral (MPEP § 2144.04(V)(B)).
Re claim 2, Cowles discloses the system of claim 1, and further discloses the following:
the bank includes: a plurality of rows arranged in a row direction; and (Fig. 1). Each bank is arranged into a plurality of rows (see banks 113, 115, 117). The rows are arranged a direction, as indicated by the downward arrows);
a plurality of count cells configured to store count data associated with the number of occurrences of activation of each of the plurality of rows (¶ 30). Each row is associated with a respective count, which may be stored in a cell of a given row, or in a separate location (count cells);
wherein risk information related to the row hammer risk indicates that the count data reached a reference count (¶ 16). When the row-level activation count (count data) reaches a threshold (reference) count, this indicates a row hammer risk, and is communicated to the memory controller so that it can control refresh frequency accordingly.
Re claim 3, Cowles discloses the system of claim 2, and further discloses that the notification circuit includes: at least one of: an alert pin configured to transmit a risk signal in response to the count data stored in at least one count cell among the plurality of count cells reaching the reference count to indicate a risky situation; or a first register configured to store flag data in response to the count data stored in at least one count cell among the plurality of count cells reaching the reference count to indicate the risky situation (¶ 15-17 and 30). The notification may be performed by a pin (alert pin) or flag, which may be stored in a register, to indicate that the count data has reached a threshold.
Re claim 4, Cowles discloses the system of claim 3, and further discloses that the memory controller is configured to: obtain the row hammer risk based on the flag data stored in the first register or the risk signal transmitted by the first pin (¶ 15-17). The pin/flag is readable by the memory controller.
Re claim 18, Cowles discloses the system of claim 1; accordingly, it also discloses a method implemented by that system.
Re claim 19, Cowles discloses the method of claim 18, and further discloses that controlling the transmission frequency of the RFM command includes: selectively transmitting the RFM command based on the notification or adjusting the threshold based on the notification Figs. 5-7; ¶ 15-17). The memory controller controls how often a refresh is triggered (transmission frequency of the RFM command), based on the refresh confirmation (notification circuit).
Re claim 20, Cowles discloses the following:
A memory device comprising: a memory cell array including a bank (Fig. 1, memory device 111; ¶ 24). The memory device is comprised of an array of cells arranged into banks;
a row hammer management circuit (¶ 5). The memory device maintains a row-level activation count, so it contains a row hammer management circuit;
and a notification circuit including at least one of an alert pin or a register (¶ 15-17 and 30). The notification may be performed by a pin (alert pin) or flag, which may be stored in a register, to indicate that the count data has reached a threshold.
wherein the bank includes: a plurality of rows arranged in a row direction; and (Fig. 1). Each bank is arranged into a plurality of rows (see banks 113, 115, 117). The rows are arranged a direction, as indicated by the downward arrows);
a plurality of count cells configured to store count data associated with a number of occurrences of activation of each of the plurality of rows, and (¶ 30). Each row is associated with a respective count, which may be stored in a cell of a given row, or in a separate location (count cells);
wherein the row hammer management circuit is configured to: manage count data for each of the plurality of rows (The memory device maintains a row-level activation count, so it contains a row hammer management circuit;
store flag data indicating a risky situation in the register and apply a risk signal indicating the risky situation to the alert pin, based on the count data stored in at least one of the plurality of count cells reaching a reference (¶ 15-17 and 30). This limitation is indefinite, as noted above. Examiner interprets it to mean either the flag in the register or the alert pin may indicate the risky situation. The notification may be performed by a pin (alert pin) or flag, which may be stored in a register, to indicate that the count data has reached a threshold.
Cowles discloses the claim limitations above; however, it also discloses multiple embodiments of the claimed invention; accordingly, it is not explicitly stated whether each limitation occurs in a single embodiment; nevertheless, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine the embodiments of Cowles into a single embodiment, as it would be merely making the embodiments integral (MPEP § 2144.04(V)(B)).
Claims 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Cowles in view of Bains et al (US 2014/0006703 A1).
Re claim 5, Cowles discloses the system of claim 4, and further discloses the following:
the memory controller is configured to: [operate in] one of a first mode or a second mode based on the row hammer risk (¶ 40-41). The pin or flag may be set to a low state (corresponding to a first mode) or a high state (corresponding to a second mode) based on the row hammer risk for the row;
wherein, in the first mode, the memory controller is configured to maintain operation without transmitting the RFM command irrespective of the number of occurrences of bank activation (¶ 40). When the pin state is low (first mode), the memory controller continues to operate, and count bank activations, without transmitting the refresh command (RFM);
wherein, in the second mode, the memory controller is configured to transmit the RFM command based on the number of occurrences of bank activation reaching a threshold (¶ 41). When the pin state is high (second mode), the next time a refresh command is triggered, and the bank activations have exceeded a threshold, the refresh will be confirmed by the memory device, and the memory controller will transmit the RFM.
While the process of the memory controller of Cowles ignoring the bank activation count threshold in a first scenario, and acknowledging it and sending a refresh command in a second scenario, can be considered first and second modes, respectively, Cowles does not explicitly disclose the memory controller setting a first or second mode. Accordingly, Examiner has provided Bains.
Bains discloses that he memory controller is configured to: set an operation mode to one of a first mode or a second mode (¶ 59-60). The memory controller can clear or set a mode register to disable (first mode) or enable (second mode) targeted refresh commands.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the different operation states (modes) of memory controller operation of Cowles such that the memory controller specifically set an operation mode, as in Bains, because it would be applying a known technique to improve a similar device in the same way. Cowles discloses performing row hammer refresh operations in two different ways (modes). Bains also discloses performing row hammer refresh operations in two different ways, which has been improved in a similar way to the claimed invention, to set an operation mode. It would have been obvious to one having ordinary skill in the art to delineate between the ways that the memory controller of Cowles operates using modes, as in Bains, because it would yield the predictable improvement that maintaining distinct states constraining and allowing memory controller operations would simplify the process of determining how to respond to refresh threshold triggers.
Re claim 6, Cowles and Bains disclose the system of claim 5, and Cowles further discloses that the memory controller is configured to: [operate in] the second mode based on the flag data comprising first data indicative of the risky situation; and otherwise [operate in] the first mode (40-41). When the flag/pin/register indicates that the row hammer risk is high (indicative of the risky situation), the memory controller allows refresh (RFM) commands (second mode); otherwise, when the flag/pin/register is low, it operates in the first mode, where refresh (RFM) commands are ignored.
Bains further discloses that the memory controller is configured to: set an operation mode to one of a first mode or a second mode (¶ 59-60). The memory controller can clear or set a mode register to disable (first mode) or enable (second mode) targeted refresh commands.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Cowles and Bains, for the reasons noted in claim 5 above.
Re claim 7, Cowles and Bains disclose the system of claim 6, and Cowles further discloses that the memory controller is configured to: perform a read operation on the first register to obtain the row hammer risk based on the number of occurrences of bank activation reaching the threshold (Fig. 5; ¶ 30). The memory controller may obtain the row hammer risk from the memory device (Fig. 5), which may be stored in a register (¶ 30).
Re claim 8, Cowles and Bains disclose the system of claim 6, and Cowles further discloses the following:
wherein the memory controller is configured to: perform, in the first mode, a read operation on the first register to obtain the row hammer risk based on the number of occurrences of bank activation reaching the threshold (Fig. 5). The memory controller reads the pin/flag/register based on the bank activation count reaching a threshold;
[operate in] the second mode based on obtaining the flag data indicating the risky situation (Fig. 5). In response to the flag/pin/register indicating the risky situation, the controller operates such that when a refresh is triggered, it is sent to the memory device (second mode);
[operate in] the first mode in response to transmitting a set number of the RFM commands to perform the read operation on the first register (¶ 30). This limitation is indefinite, as noted above. Examiner interprets it to mean going back to the first mode after an RFM command (set number) issues. When one (set number = 1) RFM command issues, and thus the row is refreshed, the counter for that row is reset, which causes the memory controller to go back to operating in the first mode, where refresh triggers are ignored.
Bains further discloses that the memory controller is configured to switch between a first mode and a second mode (¶ 59-60). The memory controller can clear or set a mode register to disable (first mode) or enable (second mode) targeted refresh commands.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Cowles and Bains, for the reasons noted in claim 5 above.
Re claim 9, Cowles and Bains disclose the system of claim 5, and Cowles further discloses that the memory controller is configured to: [operate in] the second mode based on the risk signal being applied through the alert pin; and otherwise [operate in] the first mode (¶ 30 and 40-41). A pin (alert pin) causes the memory controller to operate in a second mode while set, and otherwise operate in a first mode.
Bains further discloses that the memory controller is configured to: set the operation mode to the second mode […] otherwise set the operation mode to the first mode (¶ 59-60). The memory controller can clear or set a mode register to disable (first mode) or enable (second mode) targeted refresh commands.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Cowles and Bains, for the reasons noted in claim 5 above.
Re claim 10, Cowles and Bains disclose the system of claim 9, and Cowles further discloses the following: the memory controller is configured to: perform a read operation on the first register after operating in the second mode until the RFM command is transmitted no more than a predefined number of times, based on the risk signal being applied through the alert pin while the memory controller operates in the first mode (Fig. 5). This limitation is indefinite, as noted above. Examiner interprets it to mean operating in a second mode until the RFM command is transmitted, and then transitioning back to the first mode, wherein this is controlled by the pin/flag/register. Cowles discloses operating in the second mode, wherein a refresh triggers the RFM to be transmitted, until the RFM has been transmitted once (no more than a predefined number of times), at which point it switches back to the first operation mode.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Cowles in view of Chung (US 2022/0148648 A1).
Re claim 11, Cowles discloses the system of claim 4 above, but does not specifically disclose adjusting the bank activation thresholds based on row hammer risk.
Chung discloses the following:
wherein the memory controller is configured to: set an operation mode to one of a third mode or fourth mode based on the row hammer risk (¶ 4; claims 9-10). The memory controller uses a refresh management circuit to adjust the threshold value based on row hammer risk; each threshold value can be considered an “operation mode”. The adjusted threshold values may be set in a mode register circuit (¶ 4). The thresholds are selected based on monitoring activity, which correlates to row hammer risk (¶ 8);
wherein, in the third mode, the memory controller is configured to transmit the RFM command based on the number of occurrences of bank activation reaching a first threshold, wherein, in the fourth mode, the memory controller is configured to transmit the RFM command based on the number of occurrences of bank activation reaching a second threshold, and wherein the second threshold is smaller in value than the first threshold (¶ 26). The different threshold values represent different number of bank accesses between refreshes (RFM commands); since the values are different, one is lower than the other.
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention (AIA ) to modify the row hammer refreshing of Cowles to adjust bank activity thresholds, as in Chung, because Chung suggests that adjusting the threshold would mitigate row hammers and optimize performance (¶ 29).
Re claim 12, Cowles and Chung disclose the system of claim 11, and Cowles further discloses [transitioning to] the fourth mode based on the risk signal being applied through the alert pin or based on obtaining the flag data indicative of the risky situation through a read operation on the first register while the memory controller operates in the third mode (Fig. 5). The controller transitions between ways of operating (third mode, fourth mode) by checking the alert pin/flag/register.
Chung discloses to set the operation mode to the fourth mode […] while the memory controller operates in the third mode (claims 9-10). The memory controller adjusts the threshold, thus setting the operation mode to a fourth mode (with the adjusted threshold) from the third mode (with the original threshold).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention (AIA ) to combine Cowles and Chung, for the reasons noted in claim 11 above.
Re claim 13, Cowles and Chung disclose the system of claim 12, and Cowles further discloses that the memory controller is configured to: perform the read operation on the first register based on the RFM command being transmitted no more than a predefined number of times while the memory controller operates in the fourth mode; and otherwise operate in the third mode (Fig. 5). Based on the refresh command (RFM command) being sent zero (no more than a predetermined number of times) while the controller is operating with the flag set (fourth mode), the controller reads the flag/pin/register (first register) and then sends a refresh (RFM command). Otherwise, the flag is reset and the controller operates in the third mode.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Cowles in view of Kim et al (US 2022/0270672 A1).
Re claim 14, Cowles discloses the device of claim 1, but does not disclose risk related to temperature information.
Kim discloses that the notification circuit includes: a second register configured to store temperature information of the memory device, and wherein the memory controller is configured to: obtain the temperature information based on a read operation of the second register; and adjust the threshold based on the obtained temperature information (¶ 63 and 112). The activation section (threshold) is adjusted based on temperature information (¶ 63), which is stored in a register (¶ 112), which is accessible to the memory controller (¶ 117).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the row hammer mitigation of Cowles to utilize temperature information to adjust the refreshing, as in Kim, because Kim suggests that the temperature changes the row hammer risk, and accordingly, adjusting the thresholds based on temperature would allow the risk to be decreased to protect vulnerable banks or reduce protection for resistant banks (¶ 110).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Cowles in view of Emmot et al (US 2003/0067832 A1).
Re claim 16, Cowles discloses the system of claim 1, and Cowles further discloses the following:
the memory controller is configured to: count, in response to an activate command being transmitted to the bank, the number of occurrences of bank activation (¶ 15-16 and 29). The controller maintains a bank-level count of activations (¶ 15-16), and increments said count in response to a read/write command directed to a particular bank (activate command being transmitted to the bank);
transmit the RFM command based on the number of occurrences of bank activation reaching the threshold or based on the summed bank activation time reaching a time threshold (Fig. 5). The refresh (RFM) command is transmitted responsive to the count reaching the threshold.
Cowles does not specifically disclose summing a bank activation time.
Emmot discloses to sum a bank activation time of the bank, which is based on the activate command transmitted to the bank; and (¶ 3-4). The memory is aware of an activation time for a bank, and it waits a predetermined amount of time (summing the activation time) before issuing commands to the activated read/write row.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the bank activation of Cowles to sum activation time, as in Emmot, because it would be applying a known technique to improve a similar system in the same way. Cowles discloses sending bank activation commands. Emmot also discloses bank activation commands, which has been improved in a similar way to the claimed invention, to sum activation time. It would have been obvious to modify the bank activation of Cowles to sum activation time, as in Emmot, because it would yield the predictable improvement of preventing attempts to access memory before it is successfully activated, and thus avoiding memory errors.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
He et al (US 2020/0402568 A1). Modifies row hammer refresh rates based on both temperature and bank activations (¶ 25).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG S GOLDSCHMIDT whose telephone number is (571)270-3489. The examiner can normally be reached M-F 10-6.
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/CRAIG S GOLDSCHMIDT/ Primary Examiner, Art Unit 2132