DETAILED ACTION
Response to Amendment
This action is responsive to the Applicant's amendments filed on 07/24/26. Claims 1-14 remain pending in the application. Claim 1 has been amended. Any examiner's note, objection, and rejection not repeated is withdrawn due to Applicant's amendment.
Applicants’ arguments have been fully considered but they are not persuasive. Applicant's arguments are summarized below:
Response to Arguments
The applicant argues that the operations of Figs. 8, 11, and 14 of Araya et al. are directed to different word lines (i.e., WL3, WL2). In addition, Araya et al teaches that the read data and the soft bit data are generated using the results of the operations of Figs. 8, 11, and 14 (e.g., see steps S403 and S404 and associated description). By contrast, with the structure recited in amended claim 1, the control circuit performs the first, second, and third read operations targeted to the (same) memory cell transistor, to read out the first, second, and third bits therefrom, and it is submitted that Araya et al clearly fails to disclose or suggest this structure.
The Examiner respectfully disagrees. For example, Araya teaches a control circuit configured to control the word line and the sense amplifier unit, the control circuit including a plurality of latch circuits, and the latch circuits including a first latch circuit, a second latch circuit, and a third latch circuit (see col. 7, lines 32-67 to col. 8, lines 1-23), wherein the control circuit performs a plurality of read operation targeted to the memory cell transistor, the read operations including a first read operation to read out the first bit into the first latch circuit, generate a minus-side soft bit in the second latch circuit, and generate plus-side soft bit in the third latch circuit (see col. 10, lines 46-67 to col. 11, lines 1-30, col. 18, lines 2- 18), a second read operation, (col. 10, lines 46-67 to col. 11, lines 1-30, col. 18, lines 2- 18), a second read operation, performed after the first read operation, to read out the second bit into the first latch circuit, update the minus-side soft bit in the second latch circuit, and update the plus-side soft bit in the third latch circuit (col. 11, lines 30-64, col. 18, lines 23-38), and a third read operation, performed after the second read operation, to read out the third bit into the first latch circuit, update the minus-side soft bit in the second latch circuit, and update the plus-side soft bit in the third latch circuit (col. 11, lines 65-67 to col. 12, lines 1-61, and col. 18, lines 43-67). Further the Examiner respectfully disagrees, and the concepts are taught in Araya’s reference to the extent required by the actual claim language. Further, the interpretation of the claim language must be as broad as possible for the given art. If the Applicant needs a specific interpretation of the claim language, these details must be imported into the claims. These details cannot be read into the claim language when the claim language is so broad as to encompass other valid interpretations. Applicants are advised to review Araya reference in its entirety for a complete and better understanding of the prior art applied. This may enhance the Applicants ability to formulate claim language that includes novelty of the application. It is the Examiner's conclusion that the claims of the present application, as presented, are not patentably distinct or novel over the prior arts of record. Applicants are encouraged to formulate claim language that clearly differentiates the claims from the prior art of record. Therefore, the applicants’ argument, although acknowledged, has not been found to be convincing. Therefore, considering the above, the final rejection holds strong in view of the recited reference (Araya).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any
correction of the statutory basis for the rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be
the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a) (1) the claimed invention was patented, described in a printed publication, or
in public use, on sale, or otherwise available to the public before the effective
filing date of the claimed invention
Claims 1-14 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Araya et al.
"Herein as Araya" (U.S. PN: 10,839,917).
As per claim 1:
Araya substantially teaches a nonvolatile memory comprising a memory cell transistor configured to store information of a plurality of bits, the bits including a first bit, a second bit, and a third bit (see col. 4, lines 6-17, col. 6, lines 49-67 to col. 7, lines 1-9); a word line connected to a gate of the memory cell transistor; a row decoder connected to the word line; a bit line connected to one end of the memory cell transistor; a sense amplifier unit connected to the bit line (see col. 6, lines 24-29 and col. 7, lines 32-46) and a control circuit configured to control the word line and the sense amplifier unit, the control circuit including a plurality of latch circuits, and the latch circuits including a first latch circuit, a second latch circuit, and a third latch circuit (see col. 7, lines 32-67 to col. 8, lines 1-23), wherein the control circuit performs a plurality of read operation targeted to the memory cell transistor, the read operations including a first read operation to read out the first bit into the first latch circuit, generate a minus-side soft bit in the second latch circuit, and generate plus-side soft bit in the third latch circuit (see figure 8, col. 10, lines 46-67 to col. 11, lines 1-30, col. 18, lines 2- 18), a second read operation, performed after the first read operation, to read out the second bit into the first latch circuit, update the minus-side soft bit in the second latch circuit, and update the plus-side soft bit in the third latch circuit (see figure 11, col. 11, lines 30-64, col. 18, lines 23-38), and a third read operation, performed after the second read operation, to read out the third bit into the first latch circuit, update the minus-side soft bit in the second latch circuit, and update the plus-side soft bit in the third latch circuit (see figure 14, col. 11, lines 65-67 to col. 12, lines 1-61, and col. 18, lines 43-67).
As per claim 2, Araya substantially teaches, in view of above rejections, an input and output circuit configured to transmit data toward an external memory controller (see figure 1 and col. 4, lines 14-67 to col. 1-20).
As per claim 3, Araya substantially teaches, in view of above rejections, wherein: the control circuit is further configured to perform a plurality of data out operations, the data out operations including: a first data out operation, performed after the first read operation and before the second read operation, to transmit the first bit to the external memory controller, a second data out operation, performed after the second read operation and before the third read operation, to transmit the second bit to the external memory controller, a third data out operation, performed after the third read operation, to transmit the third bit to the external memory controller, a fourth data out operation, performed after the third read operation, to transmit the minus-side soft bit to
the external memory controller, and a fifth data out operation, performed after the third read operation, to transmit the plus-side soft bit to the external memory controller (see col. 17, lines 48-67 to col. 18, lines 1-67).
As per claim 4, Araya substantially teaches, in view of above rejections, wherein: the fourth data out operation is performed after the third data out operation, and the fifth data out operation is performed after the fourth data out operation (see col. 17, lines 48-67 to col. 18, lines 1-67).
As per claim 5, Araya substantially teaches, in view of above rejections, wherein: the bits further include a fourth bit, the read operations further include a fourth read operation, and the fourth data out operation is performed after the third data out operation to read out the fourth bit into the first latch circuit, update the minus-side soft bit in the second latch circuit, and update the plus-side soft bit in the third latch circuit (see col. 17, lines 48-67 to col. 18, lines 1-67).
As per claim 6, Araya substantially teaches, in view of above rejections, wherein: the data out operations further include a sixth data out operation, the sixth data out operation is performed after the fourth read operation to transmit the fourth bit to the external memory controller, the fourth data out operation is performed after the sixth data out operation, and the fifth data out operation is performed after the fourth data out operation (see col. 17, lines 48-67 to col. 18, lines 1-67).
As per claim 7, Araya substantially teaches, in view of above rejections, wherein
the input and output circuit is further configured to receive a plurality of command sets
from the external memory controller (see figure 1 and col. 4, lines 14-67 to col. 1-20).
As per claim 8, Araya substantially teaches, in view of above rejections, wherein: the command sets includes a first read command set, a second read command set, and a third read command set, and the control circuit performs: the first read operation in response to the first read command set, the second read operation in response to the second read command set, and the third read operation in response to the first third command set (see col. 7, lines 32-67 to col. 8, lines 1-23, col. 10, lines 50- 67 to col. 11, lines 1-28, col. 18, lines 2-67).
As per claim 9, Araya substantially teaches, in view of above rejections, wherein: the command sets further include a first data out command set, a second data out command set, a third data out command set, a fourth data out command set, and a fifth data out command set, and the control circuit performs: the first data out operation in response to the first data out command set, the second data out operation in response to the second data out command set, the third data out operation in response to the third data out command set, the fourth data out operation in response to the fourth data out command set, and the fifth data out operation in response to the fifth
data out command set (see col. 7, lines 32-67 to col. 8, lines 1-23, col. 10, lines 50-67 to col. 11, lines 1-28, col. 18, lines 2-67).
As per claim 10, Araya substantially teaches, in view of above rejections, wherein in the first read operation, the control circuit: controls the row decoder to apply a first read voltage to the first word line, and controls the sense amplifier to: sense data through the bit line with a first sense period to store the sensed data into the first latch circuit as the first bit, sense data through the bit line with a shortened first sense period to store the sensed data into the second latch circuit as the minus-side soft bit, and sense data through the bit line with a lengthened first sense period to store the sensed data into the third latch circuit as the plus-side soft bit (see figure 8, col. 6, lines 24-29, col. 10, lines 50-67 to col. 11, lines 1-28, col. 18, lines 2-18). circuit: controls the row decoder to apply a second read voltage different from the first read voltage to the first word line, and controls the sense amplifier to: sense data through the bit line with a second sense
period to store the sensed data into the first latch circuit as the second bit, sense data through the bit line with a shortened second sense period to update the data previously stored in the second latch circuit by performing OR operation of the sensed data and the previously stored data as the minus-side soft bit, and sense data through the bit line with a lengthened second sense period to update the data previously stored in the third latch circuit by performing OR operation of the sensed data and the previously stored data as the plus-side soft bit (see figure 8, col. 6, lines 24-29, col. 10, lines 50-67 to col. 11, lines 1-28, col. 18, lines 2-18).
As per claim 12, Araya substantially teaches, in view of above rejections, wherein in the third read operation, the control circuit: controls the row decoder to apply a third read voltage different from the first read voltage and the second read voltage to the first word line, and controls the sense amplifier to: sense data through the bit line with a third sense period to store the sensed data into the first latch circuit as the third bit, sense data through the bit line with a shortened third sense period to update the data previously stored in the second latch circuit by performing OR operation of the sensed data and the previously-stored data as the minus-side soft bit, and sense data through the bit line with a lengthened third sense period to update the data previously stored in the third latch circuit by performing OR operation of the sensed data and the previously-stored data as the plus-side soft bit(see figure 8, col. 6, lines 24-29, col. 10, lines 50-67 to col. 11, lines 1-28, col. 18, lines 2-18).
As per claim 13, Araya substantially teaches, in view of above rejections, wherein: the memory cell transistors are provided in plurality, the bit lines are provided in plurality, the sense amplifier units are provided in plurality, the word line is commonly connected to the gates of the memory cell transistors, the bit lines are respectively connected to the one ends of the memory cell transistors, and the sense amplifier units are respectively connected to the bit lines (see col. 4, lines 6-17, col. 6, lines 24-67 to col. 7, lines 1-46).
As per claim 14, Araya substantially teaches, in view of above rejections, wherein: the number of first bits transmitted to the external memory controller in the first data out operation is the same as the number of the minus-side soft bits transmitted to the external memory controller in the fourth data out operation and the number of the plus-side soft bits transmitted to the external memory controller in the fifth data out operation, the number of second bits transmitted to the external memory controller in the second data out operation is the same as the number of the minus-side soft bits transmitted to the external memory controller in the fourth data out operation and the number of the plus-side soft bits transmitted to the external memory controller in the fifth data out operation, and the number of third bits transmitted to the external memory controller in the third data out operation is the same as the number of the minus-side soft bits transmitted to the external memory controller in the fourth data out operation and the number of the plus-side soft bits transmitted to the external memory controller in the fifth data out operation (see col. 4, lines 6-17, col. 6, lines 24-67 to col. 7, lines 1- 46).
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner'ssupervisor, Albert DeCady can be reached on (571) 272-3819. The fax phonenumber for the organization where this application or proceeding is assigned is(703) 872-9306.
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/ESAW T ABRAHAM/
Primary Examiner,
Art Unit 2112
Prosecution Insights