DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 12/05/2024 for application number 18/970,818. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Claims, Drawings, Abstract, Oath/Declaration, and Certified Copy of Foreign Priority Application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over TAO et al., US 2015/0229119 A1, in view of MATTOS et al., US 2019/0278731 A1.
Regarding Claim 1, TAO discloses:
A control circuit for a universal serial bus, comprising: a blocking switch electrically connected between a power supply terminal of the universal serial bus and a bus power terminal of the universal serial bus (Fig. 5 illustrates a control circuit for a universal serial bus which includes all the components attached to USB connector 510, including switch 552 which is connected between VOUT (i.e. a power supply terminal of the universal serial bus) and VBUS (i.e. a bus power terminal of the universal serial bus); [0022] discloses an output voltage from a power supply (VOUT) (i.e. the VOUT corresponds to the power supply terminal));
a current source circuit electrically connected between the power supply terminal and the bus power terminal (Fig. 5 illustrates a current source 558 working with first and second PMOS transistors 556 and 557 (i.e. components of a current source circuit) that is connected between the VOUT (i.e. the power supply terminal) and VBUS (i.e. the bus power terminal));
a discharge circuit electrically connected between the bus power terminal and a reference low voltage (Fig. 5 illustrates the NMOS transistor 560 (i.e. a discharge circuit) connected between the VBUS (i.e. the bus power terminal) and a ground (i.e. reference low voltage)); and
a controller electrically connected to a control terminal of the blocking switch, the current source circuit, and the discharge circuit (Fig. 5 illustrates the control logic circuit 555 is connected to the switch 552 and the current source 558),
wherein before supplying power to the bus power terminal, the controller turns off the blocking switch, and controls the discharge circuit to pull down an output voltage value at the bus power terminal ([0025] discloses the switch 552 (i.e. the blocking switch) is initially OFF before detection (i.e. turning off the blocking switch) and the NMOS transistor 560 (i.e. the discharge circuit) is configured to discharge the VBUS capacitor 535 (i.e. pulling down an output voltage value at the bus power terminal) until the power-on-reset (POR) time period is over and detection is ready to proceed (i.e. discharging the VBUS capacitor is happening while the switch is OFF)),
the controller controls the discharge circuit to stop pulling down the output voltage value, and controls the current source circuit to provide a test current to the bus power terminal ([0025] discloses the NMOS transistor 560 is turned off and the detection current IDET (e.g., a constant current) (i.e. a test current) from current source 558 is sourced to VBUS after a power-on-reset (POR) time period), and
wherein the controller obtains a resistance value at the bus power terminal according to the output voltage value and a current value of the test current ([0026] discloses if the connector impedance 512 is detected as an acceptably high impedance, the voltage on VBUS will be higher than the reference voltage, indicating USB connectors are in good condition. if the connector impedance 512 is detected as an abnormally low impedance, the voltage on VBUS will be less than the reference voltage, indicating faulty USB connectors (i.e. the impedance is determined using the VBUS voltage and the constant current sourced by the current source 558)).
TAO does not explicitly disclose wherein in response to the output voltage value being lower than or equal to a first set voltage value, the controller controls the discharge circuit to stop pulling down the output voltage value.
However, MATTOS teaches wherein in response to the output voltage value being lower than or equal to a first set voltage value, the controller controls the discharge circuit to stop pulling down the output voltage value ([0058] teaches stopping the discharge when the voltage on VBUS line 201 reaches a certain non-zero voltage level (i.e. stopping the discharge in response to the voltage reaching a set voltage value)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of TAO and MATTOS before him before the effective filing date of the claimed invention, to incorporate stopping the discharge in response to voltage meeting a reference voltage as taught by MATTOS into a USB control circuit detecting impedance disclosed by TAO to have protection against high currents without requiring any external/off-chip discharge components (MATTOS [0024]).
Regarding Claim 2, TAO and MATTOS disclose the control circuit of Claim 1. TAO further discloses:
wherein the current source circuit comprises: a first current source, wherein a first terminal of the first current source is electrically connected to the power supply terminal (Fig. 5 illustrates current source 558 connected to VOUT (i.e. electrically connected to the power supply terminal) through the first PMOS transistor 556 (i.e. the current source directly connects to the first PMOS transistor, which is ends at VOUT)), and
the first current source is configured to generate the test current ([0025] discloses the current source 558 detection current IDET (e.g., a constant current) can be sourced to VBUS (i.e. generating the test current)); and
a first switch electrically connected between a second terminal of the first current source and the bus power terminal (Fig. 5 illustrates the current source 558 has a second pathway between the first and second PMOS transistors 556 and 557 (i.e. current source's second terminal electrically connected to switches), and the second PMOS transistor 557 is connected to VBUS (i.e. electrically connected to the bus power terminal)).
Regarding Claim 6, TAO and MATTOS disclose the control circuit of Claim 1. TAO further discloses:
wherein during a period when the test current is provided to the bus power terminal, in response to the output voltage value being higher than a set voltage value, the controller turns on the blocking switch ([0025] discloses after a POR time period, the NMOS transistor 560 is turned off (i.e. second switch is turned off) and the detection IDET is then sourced to VBUS using first and second PMOS transistors 556, 557 and current source; [0026] discloses if the connector impedance 512 is detected (i.e. the detection current is continuously used during the impedance detection process) as acceptably high, the voltage on VBUS (e.g., IDET*RCONN) (i.e. the output voltage value) is higher than reference voltage (VREF) (i.e. the set voltage value), it is indicating that the micro-USB and USB connector 505, 510 are in good condition and the switch 552 is turned ON (i.e. turning on the blocking switch);
MATTOS further teaches a second set voltage value ([0050] teaches that the voltage threshold detectors can monitor the voltage level and can detect a VBUS voltage with respect to multiple voltage levels (i.e. having more than one reference voltage to compare against the voltage of the VBUS)).
Regarding Claim 7, TAO and MATTOS disclose the control circuit of Claim 1. TAO further discloses:
a comparator electrically connected to the bus power terminal and the controller, and configured to receive the output voltage value and the first set voltage value (Fig. 5 illustrates a comparator 559 connected to the VBUS (i.e. the bus power terminal) and the control logic circuit 555 (i.e. the controller); the IDET*RCONN and the VREF are inputted into the comparator 559; [0026] discloses the voltage of the VBUS (e.g., IDET*RCONN) (i.e. the output voltage value) and the reference voltage (VREF) (i.e. the first set voltage value) (i.e. the comparator receives the VBUS voltage and the VREF voltage)),
wherein before supplying power to the bus power terminal, the comparator compares the output voltage value and the first set voltage value to generate a comparison signal ([0025] discloses the switch 552 is initially OFF before the VBUS detection process; if the connector impedance 152 is detected as an abnormally low impedance, for example, using a comparator 559 and a reference voltage (VREF) and the voltage on VBUS, it means the voltage on VBUS is less than the reference voltage and the switch is kept OFF (i.e. the detection process is happening before supplying power); Fig. 5 illustrates the VBUS IDET*RCONN voltage and VREF voltage are inputs in the comparator 559 (i.e. the comparator compares the output voltage value and the first set voltage value), and it outputs the comparison signal to the control logic 555).
Regarding Claim 8, TAO and MATTOS disclose the control circuit of Claim 1. TAO further discloses:
before supplying power to the bus power terminal, the controller receives a comparison signal (Fig. 5 illustrates the comparator 559 has two inputs IDET*RCONN (VBUS voltage) and VREF (reference voltage) and the output towards the control logic 555 (i.e. the controller) is VBUSOK (i.e. the control logic 555 receives the comparison signal between the VBUS voltage and the VREF); [0025] discloses that the switch 552 is OFF before detection; [0026] discloses the decision to turn the switch 552 ON or OFF is based on the connector impedance and the comparator 559 (i.e. receiving the comparison signal occurs prior to supplying power)), and
in response to the comparison signal indicating that the output voltage value is higher than the first set voltage value ([0026] discloses if the connector impedance 512 is detected as an acceptably high impedance using comparator 559, the voltage on VBUS is higher than VREF (i.e. the comparator signal output indicates that the voltage on VBUS is higher than the reference voltage)),
the controller controls the discharge circuit to pull down the output voltage value, and controls the current source circuit to stop providing the test current to the bus power terminal ([0025] discloses the detection current IDET is sourced after the POR time period and the NMOS transistor 560 is turned off (i.e. the current will not be sourced until the criteria is met for the discharging to stop)).
TAO does not explicitly disclose the combination of in response to the comparison signal indicating that the output voltage value is higher than the first set voltage value, the controller controls the discharge circuit to pull down the output voltage value.
However, MATTOS teaches in response to the comparison signal indicating that the output voltage value is higher than the first set voltage value, the controller controls the discharge circuit to pull down the output voltage value ([0058] teaches stopping the discharge when the voltage on VBUS line 201 reaches a certain non-zero voltage level (i.e. stopping the discharge in response to the voltage reaching a set voltage value) which can be detected by voltage threshold detectors; [0050] teaches the voltage threshold detectors include comparators that monitor the voltage levels of the VBUS line (i.e. the output voltage value) against a reference voltage (i.e. the first set voltage value) and will send out a signal when the VBUS voltage levels reach the reference voltage (i.e. the detector will continue to allow the discharge circuits to discharge the voltage on VBUS as long as its higher than the reference value)).
Regarding Claim 9, TAO and MATTOS disclose the control circuit of Claim 8. TAO further discloses:
the controller controls the discharge circuit to stop pulling down the output voltage value, and controls the current source circuit to provide the test current to the bus power terminal ([0025] discloses that the NMOS transistor 560 (i.e. the discharge circuit) is turned off and the detection current IDET is sourced to VBUS after a POR time period (i.e. after an event, the discharge circuit stops pulling down on the output voltage value, and the current source circuit sources the detection/test current to the bus power terminal)).
TAO does not explicitly disclose the criteria wherein in response to the comparison signal indicating that the output voltage value is lower than or equal to the first set voltage value, the controller controls the discharge circuit to stop pulling down the output voltage value,
However, MATTOS teaches wherein in response to the comparison signal indicating that the output voltage value is lower than or equal to the first set voltage value, the controller controls the discharge circuit to stop pulling down the output voltage value ([0058] teaches stopping the discharge when the voltage on VBUS line 201 reaches a certain non-zero voltage level (i.e. stopping the discharge in response to the voltage reaching a set voltage value) which can be detected by voltage threshold detectors; [0050] teaches the voltage threshold detectors having comparators that output a signal when the output voltage reaches a reference voltage (i.e. stopping the discharge is caused by the comparators detecting that the output voltage has reached the reference voltage)).
Regarding Claim 10, TAO and MATTOS disclose the control circuit of Claim 1. The combination of TAO and MATTOS as presented does not explicitly disclose:
wherein: the control circuit communicates with a power receiving device connected to the bus power terminal to obtain a communication resistance value, and
the controller determines whether to control the current source circuit to provide the test current to the bus power terminal according to the communication resistance value.
However, in a different embodiment, TAO teaches wherein: the control circuit communicates with a power receiving device connected to the bus power terminal to obtain a communication resistance value (Fig. 3 illustrates the all of the components attached to the USB connector 305 via USB cable 301 (i.e. the control circuit) connected with electronic device 340 (i.e. a power receiving device) through the VBUS terminal of the USB connector 305 (i.e. connected to the bus power termina); [0018] discloses pin-to-pin impedances of the micro-USB and USB connectors 305, 310 between VBUS and GND are micro-USB and USB connector impedances (RCONN1, RCONN2) respectively (i.e. the RCONN1 is the communication resistance value between the USB connector and electronic device)), and
the controller determines whether to control the current source circuit to provide the test current to the bus power terminal according to the communication resistance value ([0018] teaches the USB protection circuit 350 (i.e. the controller) can remove a current path between VOUT and VBUS if an abnormally low impedance is detected (i.e. determines whether to provide the current to the bus power terminal); [0019] discloses USB detection circuit 351 inside the USB protection circuit 350 can detect an impedance across one or more pins of the USB connector 310 or micro-USB connector 305).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of TAO and MATTOS before him before the effective filing date of the claimed invention, to incorporate a separate impedance value detection between a connected electronic device and the USB connector as taught by TAO into the control circuit disclosed by TAO and MATTOS to detect an impedance across one or more pins of the USB connector 310 or the micro-USB connector 305 separately (TAO [0019]).
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over TAO and MATTOS, in view of SALA et al., US 8,725,910 B1, and further in view of ZHAO, US 2016/0241135 A1.
Regarding Claim 3, TAO and MATTOS disclose the control circuit of Claim 2.
The combination of TAO and MATTOS does not explicitly disclose:
wherein the discharge circuit comprises: a second current source, wherein a first terminal of the second current source is electrically connected to the bus power terminal, and
the second current source is configured to generate a discharge current; and
a second switch electrically connected between a second terminal of the second current source and the reference low voltage.
However, SALA teaches wherein the discharge circuit comprises: a second current source, wherein a first terminal of the second current source is electrically connected to the bus power terminal (Fig. 3 illustrates two constant current sources 234, 235 and switches 234, 239; the discharging circuit comprises constant current source 235 (i.e. a second current source), wherein a first terminal of the constant current source 235 is connected to the VBUS line 204 (i.e. the bus power terminal) through switch 239, close switch 242, and line 240 (i.e. the constant current source 235 is electrically connected to VBUS 204); C7:L58-59 teaches closing switch 238 and opening switch 239 to allow current source 234 to inject current into VBUS line 204 (i.e. the first switch 238 and the first constant current source 234 act as a charging circuit for the VBUS line); C8:L18-21 teaches the cable detection controller 230 can open switch 238, and close switch 239 to connect the VBUS line 204 to ground through the constant current source 235, allowing voltage to discharge (i.e. the second switch 239 and the second constant current source 235 act as a discharging circuit for the VBUS line 204)),
the second current source is configured to generate a discharge current (C7:L60-61 teaches closing switch 239 and opening switch 238 to allow current source 235 to sink current from VBUS line 204 (i.e. the constant current source 235 is generating a discharging current by sinking the current from the VBUS line 204 to ground)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of TAO, MATTOS, and SALA before him before the effective filing date of the claimed invention, to incorporate a charging and discharging circuit having their respective current source and switch as taught by SALA into the control circuit disclosed by TAO and MATTOS to remove any residual voltage on the VBUS line before performing tests (SALA (C5:L49-50)).
While SALA does teach a second switch and a second current source, SALA does not explicitly teach a switch electrically connected between a second terminal of the current source and the reference low voltage.
However, ZHAO teaches a switch electrically connected between a second terminal of the current source and the reference low voltage (Fig. 2 illustrates a discharge circuit 220 comprising power switch K170 that is connected to the constant current source I_discharge (i.e. electronically connected between the second terminal of the second current source) and the ground (i.e. the reference low voltage)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of TAO, MATTOS, SALA, and ZHAO before him before the effective filing date of the claimed invention, to incorporate a discharge circuit with the discharging switch between the current source and ground as taught by ZHAO into the control circuit disclosed by TAO, MATTOS, and SALA to provide stable power (ZHAO [0003]).
Regarding Claim 4, TAO, MATTOS, SALA, and ZHAO disclose the control circuit of Claim 3. TAO further discloses:
wherein before supplying power to the bus power terminal, the controller turns off the blocking switch, turns off the first switch, and turns on the second switch ([0022] discloses the VBUS detection circuit detects that the impedance if above a certain threshold; based on the detection the control logic circuit can turn the switch ON or OFF; [0025] discloses the switch 552 is initially OFF before detection (i.e. before supplying power to the bus power terminal, the blocking switch is off); the NMOS transistor 560 is configured to discharge the VBUS capacitor (i.e. the second switch is on); the detection current IDET from current source 558 and PMOS transistors 556 and 557 is not sourcing until after a power-on-reset (POR) time period (i.e. the first switch is off)).
Regarding Claim 5, TAO, MATTOS, SALA, and ZHAO disclose the control circuit according to Claim 3. TAO further discloses:
the controller turns off the blocking switch, turns off the second switch, and turns on the first switch ([0025] discloses that the switch 552 is initially off before the detection process; after a POR time period, the NMOS transistor 560 is turned off (i.e. second switch is turned off) and the detection IDET is then sourced to VBUS using first and second PMOS transistors 556, 557 and current source 558 (i.e. in response to an event, the discharging stops and the transistors for the current source are turned on while the switch is already off)).
TAO does not explicitly disclose the criteria wherein in response to the output voltage value being lowered to the first set voltage value, the controller turns off the second switch.
However, MATTOS teaches wherein in response to the output voltage value being lowered to the first set voltage value, the controller turns off the second switch ([0058] teaches stopping the discharge when the voltage on VBUS line 201 reaches a certain non-zero voltage level (i.e. stopping the discharge in response to the voltage reaching a set voltage value)).
Conclusion
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/L.A./Examiner, Art Unit 2175
/ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175
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