Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on May 27, 2026 is in compliance with the provisions of 37 CFR 1.97 and have been considered by the Examiner.
Response to Arguments
Applicant's arguments filed on 05/27/2026 have been fully considered but they
are not persuasive.
The Applicant submits the following arguments:
Regarding claim 1 in the remarks on page 2-3, the Applicant stated that " Assuming Applicant's understanding of the rejection presented in the Office Action is correct, Applicant respectfully submits that such an interpretation of Saski is not reasonable and inconsistent with the teachings of Sasaki. In particular, as shown in FIG. 3 of Sasaki (reproduced below), during readout of imaging part 3, pixel information in a row of pixels is read out into two horizontal registers 4 in two streams such that every other pixel in the row is read out to a first of the horizontal registers 4 and used to produce Vouti and the remaining pixels of the row are read out to a second of the horizontal registers 4 and used to produce Vout2. As such, Applicant respectfully submits that Vouti and Vout2 in Sasaki cannot reasonably be construed as "copies of an image data signal [read out from a pixel]," as required by independent claim 1. Rather, Vout1 and Vout2 in Sasaki are two different portions of an image data stream, with each portion corresponding to different pixels of the imaging part 3 described in Sasaki."
In response to the arguments, the Examiner respectfully disagrees with the
Applicants for the reasons set forth below:
Applicants misinterpreted the Fig 3 of Sasaki by using their own interpretation. In Fig 3 of Sasaki clearly showed at least one pixel from imaging part 3 has output the pixel information into both horizontal register 4 lines to produce Vout1 and Vout2. The pixel information (dot arrow lines) output through first horizontal register (Vout1) and second horizontal register (Vout2). The specification (column 1, line 55 – 76) disclosed that “the pixel information for one scanning line transferred in each horizontal period from an imaging part 3 formed of a two-dimensional array of a photoelectric converting device is allotted to two horizontal registers 4 for each pixel and their outputs V.sub.out1 and V.sub.out2 are simultaneously read out through amplifiers 5.” Therefore, Saski teaches the all features of independent claim 1.
Regarding Double patenting Rejection of Claims 1-3, Applicants requested that the response to the double patenting rejection be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created
doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the
unjustified or improper timewise extension of the "right to exclude" granted by a patent
and to prevent possible harassment by multiple assignees. A nonstatutory double
patenting rejection is appropriate where the conflicting claims are not identical, but at
least one examined application claim is not patentably distinct from the reference
claim(s) because the examined application claim is either anticipated by, or would have
been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46
USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed.
Cir. 1993); In re Langi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Omum,
686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619
(CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321 (d)
may be used to overcome an actual or provisional rejection based on nonstatutory
double patenting provided the reference application or patent either is shown to be
commonly owned with the examined application, or claims an invention made as a
result of activities undertaken within the scope of a joint research agreement. See
MPEP § 717.02 for applications subject to examination under the first inventor to file
provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for
applications not subject to examination under the first inventor to file provisions of the
AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321 (b).
The filing of a terminal disclaimer by itself is not a complete reply to a
nonstatutory double patenting (NSDP) rejection. A complete reply requires that the
terminal disclaimer be accompanied by a reply requesting reconsideration of the prior
Office action. Even where the NSDP rejection is provisional the reply must be complete.
See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR
1.111 (a). For a reply to final Office action, see 37 CFR 1.113(c). A request for
reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for
consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the
application in which the form is filed determines what form (e.g., PTO/SB/25,
PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal
Disclaimer may be filled out completely online using web-screens. An eTerminal
Disclaimer that meets all requirements is auto-processed and approved immediately
upon submission. For more information about eTerminal Disclaimers, refer to
wvvw.usoto.gov/patents/apply/applying-online/eterminal--disdaimer.
Claims 1 - 3 are rejected on the ground of nonstatutory double patenting as
being unpatentable over claims 1, 2, and 9 of U.S. Patent No. 12,200,390 Geurts et al.
Although the claims at issue are not identical, they are not patentably distinct from each
other because the claims in this application are broader than in Geurts et al Patent
12,200,390.
Regarding claim 1 Geurts et al Patent 12,200,390 discloses of applicant's A
method, comprising: reading an image data signal out from a pixel to a sample and hold
circuit; storing a first copy of the image data signal on the sample and hold circuit; and
storing a second copy of the image data signal on the sample and hold circuit (claim 1,
A method comprising: reading out a reset level signal from a pixel to a sample and hold
circuit; storing the reset level signal to a first storage device of the sample and hold
circuit; storing the reset level signal to a second storage device of the sample and hold
circuit; reading out a signal level signal from the pixel to the sample and hold circuit;
storing the signal level signal to a third storage device of the sample and hold circuit;
and storing the signal level signal to a fourth storage device of the sample and hold
circuit, wherein the first storage device, the second storage device, the third storage
device, and the fourth storage device are different from one another, and wherein the
reset level signal and the signal level signal correspond to a same correlated double
sampling of an image data signal captured by the pixel).
Regarding claim 2 Geurts et al Patent 12,200,390 discloses of applicant's
reading the image data signal out from the pixel includes: reading a reset level signal
out from the pixel, and reading a signal level signal out from the pixel; storing the first
copy of the image data signal on the sample and hold circuit includes: storing the reset
level signal on a first storage device of the sample and hold circuit, and storing the
signal level signal on a second storage device of the sample and hold circuit; and
storing the second copy of the image data signal on the sample and hold circuit
includes: storing the reset level signal on a third storage device of the sample and hold
circuit different from the first storage device, and storing the signal level signal on a
fourth storage device of the sample and hold circuit different from the second storage
device (claim 9, wherein: the reading of the reset level signal from the pixel, the storing
of the reset level signal to the first and second storage devices, the reading of the signal
level signal from the pixel, and the storing of the signal level signal to the third and
fourth storage devices, each correspond to a first frame; and the method further
comprises resetting only those of the first storage device, the second storage device,
the third storage device, and the fourth storage device that are not used to read out the
reset level signal or the signal level signal from the sample and hold circuit by an end of
the first frame).
Regarding claim 3 Geurts et al Patent 12,200,390 discloses of applicant's further
comprising reading the first copy of the image data signal out from the sample and hold
circuit to readout circuitry, wherein reading the first copy of the image data signal out
from the sample and hold circuit to readout circuitry includes sequentially reading out (i)
a reset level signal corresponding to the image data signal from the sample and hold
circuit and (ii) a signal level signal corresponding to the image data signal from the
sample and hold circuit (claim 2, further comprising: reading out the reset level signal
from the first storage device to readout circuitry coupled to the sample and hold circuit;
reading out the signal level signal from the third storage device to the readout circuitry;
and recovering a first copy of the image data signal based at least in part on the reset
level signal and the signal level signal readout from the first storage device and the third
storage device, respectively).
Claim Rejections - 35 USC§ 102
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any
correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will
not be considered a new ground of rejection if the prior art relied upon, and the rationale
supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S. C. 102 that
form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)( 2) the claimed invention was described in a patent issued under section 151, or in an
application for patent published or deemed published under section 122(b), in which the
patent or application, as the case may be, names another inventor and was effectively filed
before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by
Sasaki et al US Patent No. 5,374,953.
Regarding claim 1 Sasaki et al discloses of Fig. 1 - 31 of applicant's a method
(column 1, line 6, line 34 - 35 image signal processing apparatus 32 process the signal
from the electronic endoscope 31, is a method, to obtain an observed image of the
examined object) comprising: reading an image data signal out from a pixel to a sample
and hold circuit (column 1, line 55 - 76 to column 2, line 1 - 24 CCD 2 is a line transfer
type CCD where the pixel information for one scanning line transferred in each
horizontal period from an imaging part 3 formed of a two-dimensional array of a
photoelectric converting device is allotted to two horizontal registers 4 for each pixel and
their outputs Vout1 and Vout2 are simultaneously read out through amplifiers 5 where the CCD reading signals of the two systems are input respectively into the first and second correlated double sampling (CDS) circuits 9 such that the image data signal of each pixel and their outputs Vout1 and Vout2 is read out from a pixel to a sample and hold circuit CDS circuit 9);
Sasaki et al further discloses of applicant's storing a first copy of the image data
signal on the sample and hold circuit; and storing a second copy of the image data
signal on the sample and hold circuit (column 1, line 55 - 76 to column 2, line 1 – 24
CCD 2 is a line transfer type CCD where the pixel information for one scanning line
transferred in each horizontal period from an imaging part 3 formed of a two- dimensional array of a photoelectric converting device is allotted to two horizontal
registers 4 for each pixel and their outputs Vout1 and Vout2 are simultaneously read out
through amplifiers 5. Column 6, line 56 - 67 to column 7, line 1 - 25 charge coupled
device (CCD) 53 as a solid state imaging device has two outputs and each output to two
correlated double sampling (CDS) circuits 57a and 57b. The respective output signals
Vout1 and Vout2 of the CCD 53 are output, respectively, to the first and second correlated double sampling (CDS) circuits 57a and 57b (represented by CDS circuits 57 in some cases). The above mentioned CDS circuits 57 correlatively doubly sample the signals by the timing of the later described CDS clock such that a first copy of the image data pixel signal is stored on the sample and hold circuit 57a and a second copy of the image data pixel signal is stored on the sample and hold 57b.
Claim Rejections - 35 USC§ 103
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any
correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will
not be considered a new ground of rejection if the prior art relied upon, and the rationale
supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the
claims the examiner presumes that the subject matter of the various claims was
commonly owned as of the effective filing date of the claimed invention(s) absent any
evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to
point out the inventor and effective filing dates of each claim that was not commonly
owned as of the effective filing date of the later invention in order for the examiner to
consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2)
prior art against the later invention.
Claim(s) 2 – 3, 11-12, 14 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al US Patent No. 5,374,953 in view of Mori et al US Publication No. 2019/0098232.
Regarding claim 2 Sasaki et al further discloses of applicant's wherein: reading
the image data signal out from the pixel includes: storing the first copy of the image data
signal on the sample and hold circuit includes: and storing the second copy of the image
data signal on the sample and hold circuit includes (column 1, line 55 - 76 to column 2,
line 1 - 24 CCD 2 is a line transfer type CCD where the pixel information for one
scanning line transferred in each horizontal period from an imaging part 3 formed of a
two-dimensional array of a photoelectric converting device is allotted to two horizontal
registers 4 for each pixel and their outputs Vout1 and Vout2 are simultaneously read out
through amplifiers 5. Column 6, line 56 - 67 to column 7, line 1 - 25 charge coupled
device (CCD) 53 as a solid state imaging device has two outputs and each output to two
correlated double sampling (CDS) circuits 57a and 57b. The respective output signals
Vout1 and Vout2 of the CCD 53 are output, respectively, to the first and second correlated double sampling (CDS) circuits 57a and 57b (represented by CDS circuits 57 in some cases). The above mentioned CDS circuits 57 correlatively doubly sample the signals by the timing of the later described CDS clock such that the image data signal is read out from the pixel of CCD 2 where a first copy of the image data pixel signal is stored on the sample and hold circuit 57a and a second copy of the image data pixel signal is stored on the sample and hold 57b);
Sasaki et al discloses a imager readout method where pixel signals are readout
to two shift registers and where each shift register output go to a sample and hold CDs
circuit but does not expressively disclose reading a reset level signal out from the pixel,
and reading a signal level signal out from the pixel; storing the reset level signal on a
first storage device of the sample and hold circuit, and storing the signal level signal on
a second storage device of the sample and hold circuit; storing the reset level signal on
a third storage device of the sample and hold circuit different from the first storage
device, and storing the signal level signal on a fourth storage device of the sample and
hold circuit different from the second storage device;
Mori et al teaches a sample and hold circuit that stores reset and sample pixel
signals. Mori et al teaches of Fig. 1 - 33 of applicant's reading a reset level signal out from the pixel, and reading a signal level signal out from the pixel; storing the reset level
signal on a first storage device of the sample and hold circuit, and storing the signal
level signal on a second storage device of the sample and hold circuit; storing the reset
level signal on a third storage device of the sample and hold circuit different from the
first storage device, and storing the signal level signal on a fourth storage device of the
sample and hold circuit different from the second storage device (paragraph 0138 -
0139 the pixel signals VRST and VSIG of the pixels 200 are read out, in the signal
holding part 220 the first read-out reset signal VRST1 is read out as the pixel signal
from the photoelectric converting and reading part 210, the first switching transistor
SHR1-Tr of the signal holding part 220 is rendered conductive for a predetermined
period, and the first signal holding capacitor CR21 is made to hold this read-out reset
signal VRST1. The first read-out signal VSIG1 is read out as the pixel signal from the
photoelectric converting and reading part 210, the second switching transistor SHS1-Tr
of the signal holding part 220 is rendered conductive for a predetermined period, and
the second signal holding capacitor CS21 is made to hold this read-out signal VSIG1;
When the second read-out signal VSIG2 is read out as the pixel signal from the
photoelectric converting and reading part 210, the fourth switching transistor SHS2-Tr of
the signal holding part 220 is rendered conductive for a predetermined period, and the
fourth signal holding capacitor CS22 is made to hold this read-out signal VSIG2. The
second read-out reset signal VRST2 is read out as the pixel signal from the
photoelectric converting and reading part 210, the third switching transistor SHR2-Tr of
the signal holding part 220 is rendered conductive for a predetermined period, and the third signal holding capacitor CR22 is made to hold this read-out reset signal VRST2
such that reading a VRST1 reset level signal out from the pixel 200, and reading a
VSIG1 signal level signal out from the pixel 200; storing the VRST1 reset level signal on
a first storage device CR21 of the sample and hold circuit 220, and storing the VSIG1
signal level signal on a second storage device CS21 of the sample and hold circuit 220;
storing the VRST2 reset level signal on a third storage device CR22 of the sample and
hold circuit 220 different from the first storage device CR21, and storing the VSIG2
signal level signal on a fourth storage device CS22 of the sample and hold circuit 220
different from the second storage device CS21 ).
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date to modify the circuitry of Sasaki et al in a manner similar to Mori et
al. Doing so would result improving Sasaki et al invention in a similar way as Mori et al -
namely the ability to provide a sample and hold circuit that stores reset and sample pixel
signals, in Mori et al invention, to the imager readout method where pixel signals are
readout to two shift registers and where each shift register output go to a sample and
hold CDs circuit in Sasaki et al invention.
Regarding claim 3 the combination of Sasaki et al in view of Mori et al further
teach of applicant's further comprising reading the first copy of the image data signal out
from the sample and hold circuit to readout circuitry, wherein reading the first copy of
the image data signal out from the sample and hold circuit to readout circuitry includes
sequentially reading out (i) a reset level signal corresponding to the image data signal from the sample and hold circuit and (ii) a signal level signal corresponding to the image
data signal from the sample and hold circuit (Sasaki et al in column 1, line 55 - 76 to
column 2, line 1 - 24 CCD 2 is a line transfer type CCD where the pixel information for
one scanning line transferred in each horizontal period from an imaging part 3 formed of
a two-dimensional array of a photoelectric converting device is allotted to two horizontal
registers 4 for each pixel with an outputs Vout1.Column 6, line 56 - 67 to column 7, line 1- 25 charge coupled device (CCD) 53 as a solid state imaging device has two outputs
and each output to two correlated double sampling (CDS) circuits 57a and 57b. The
respective output signals Vout1 of the CCD 53 are output, respectively, to the first
correlated double sampling (CDS) circuits 57a;
Mori et in paragraph 0138 - 0139 the pixel signals VRST and VSIG of the pixels
200 are read out, in the signal holding part 220 the first read-out reset signal VRST1 is
read out as the pixel signal from the photoelectric converting and reading part 210, the
first switching transistor SHR1-Tr of the signal holding part 220 is rendered conductive
for a predetermined period, and the first signal holding capacitor CR21 is made to hold
this read-out reset signal VRST1. The first read-out signal VSIG1 is read out as the
pixel signal from the photoelectric converting and reading part 210, the second
switching transistor SHS1-Tr of the signal holding part 220 is rendered conductive for a
predetermined period, and the second signal holding capacitor CS21 is made to hold
this read-out signal VSIG1. Paragraph 0058 conversion signals corresponding to the
read-out signals held in the first to fourth signal holding capacitors are read out to a
predetermined signal line, and conversion signals corresponding to the read-out reset
signals are read out to a predetermined signal line simultaneously and in parallel and
are supplied to the column read-out circuit 40 such that reading the first copy of the
image data pixel signal, Sasaki et al output Vout1, out from the sample and hold circuit
220 to readout circuitry 40, in Mori et al, wherein reading the first copy of the image data
signal, output Vout1, out from the sample and hold circuit 220 to readout circuitry 40
includes sequentially reading out first a reset level signal VRST1 corresponding to the
image data pixel signal from the sample and hold circuit 220 and then reading out a
signal level signal VSIG1 corresponding to the image data pixel signal from the sample
and hold circuit 220).
Regarding claim 11, the combination of Sasaki et al in view of Mori et al further teach of applicant's further comprising resetting only storage devices of the sample and hold circuit that are not used to read out the first copy of the image data signal or the second copy of the image data signal from the sample and hold circuit (see claims 2-3 comments).
Regarding claim 12, the combination of Sasaki et al in view of Mori et al further teach of applicant's further comprising wherein the pixel is a first pixel, and wherein the method further comprises reading a second image data signal out from a second pixel to the sample and hold circuit, wherein the first pixel and the second pixel share the sample and hold circuit (See claims 2-3 comments).
Regarding claim 14, the combination of Sasaki et al in view of Mori et al further teach of applicant's further comprising an imaging system, comprising: a pixel array including a plurality of pixels, individual ones of the pixels configured to generate an image data signal in response to incident light; a sample and hold circuit array including a plurality of sample and hold circuits, individual ones of the sample and hold circuits corresponding to at least one of the pixels and including a plurality of storage devices; and control circuitry coupled to the pixel array and the sample and hold circuit array, the control circuitry configured to: cause a reset level signal and a signal level signal corresponding to an image data signal of a pixel to be stored to a first pair of storage devices of a corresponding sample and hold circuit, and cause the reset level signal and the signal level signal to be stored to a second pair of storage devices of the corresponding sample and hold circuit different from the first pair of storage devices (See comments claims1-2).
Regarding claim 19, the combination of Sasaki et al in view of Mori et al further teach of applicant's further comprising wherein individual ones of the sample and hold circuits comprise: a first storage device and a second storage device forming the first pair of storage devices; a third storage device and a fourth storage device forming the second pair of storage devices; and a plurality of storage transistors configured to selectively couple the first storage device,the second storage device, the third storage device, and the fourth storage device to a pixel level connection (See comments claims 1-2 and 14).
Regarding claim 20, the combination of Sasaki et al in view of Mori et al further teach of applicant's further comprising wherein: the first pair of storage devices is configured to store a first copy of the reset level signal and a first copy of the signal level signal; and the second pair of storage devices is configured to store a second copy of the reset level signal and a second copy of the signal level signal (See comments claims 1-3 and 14).
.
Claim(s) 10 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al US Patent No. 5,374,953 and Mori et al US Publication No. 2019/0098232 in view of Takayanagi US Publication No. 2004/0036785.
Regarding claim 10, the combination of Sasaki et al in view of Mori et al discloses method of claim 3, but fails to explicitly disclose further comprising recovering the first copy of the image data signal by subtracting the reset level signal from the signal level signal.
In analogous art, Takayanagi discloses recovering the first copy of the image data signal by subtracting the reset level signal from the signal level signal (see [0023]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the combination of Sasaki et al in view of Mori et al reference such further comprising recovering the first copy of the image data signal by subtracting the reset level signal from the signal level signal, in order to reduce noise signal level.
Regarding claim 15, the combination of Sasaki et al and Mori et al in view of Takayanagi further teach of applicant's further comprising readout circuitry coupled to the sample and hold circuit array, the readout circuitry configured to: receive the reset level signal and the signal level signal from the first pair of storage devices; and recover a first copy of the image data signal based at least in part on the reset level signal and the signal level signal received from the first pair of storage devices (See comments claim 10 and 14).
Regarding claim 16, the combination of Sasaki et al and Mori et al in view of Takayanagi further teach of applicant's further comprising wherein the readout circuitry is further configured to: receive the reset level signal and the signal level signal from the second pair of storage devices; and recover a second copy of the image data signal based at least in part on the reset level signal and the signal level signal received from the second pair of storage devices (See comments claims 1-2, 10 and 14).
.
Allowable Subject Matter
Claims 4 – 9, 13 and 17-18 are objected to as being dependent upon or ultimately dependent on a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE
MONTHS from the mailing date of this action. In the event a first reply is filed within
TWO MONTHS of the mailing date of this final action and the advisory action is not
mailed until after the end of the THREE-MONTH shortened statutory period, then the
shortened statutory period will expire on the date the advisory action is mailed, and any
nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be
calculated from the mailing date of the advisory action. In no event, however, will the
statutory period for reply expire later than SIX MONTHS from the mailing date of this
final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lin Ye whose telephone number is (571)272- 7372. The examiner can normally be reached M-F 9:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the TC director, James Kramer can be reached on (571) 272-6783. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LIN YE/Supervisory Patent Examiner, Art Unit 2638
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