DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-15 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings were received on 12/06/24. These drawings are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 6-7 are rejected under 35 U.S.C. 102102 (a)(2) as being anticipated by Bruset et al. (US 20250004493 A1), hereinafter Bruset.
Regarding claim 1, Bruset discloses a low- dropout regulator (fig 2, voltage regulation circuitry 300 including voltage regulation portion 320 and voltage regulator component 322), comprising: a control circuit (fig 2, control circuitry portion 350), generating a plurality of bypass control signals (fig 2 and par [0067] “The digital logic core 354 outputs control signals to the rest of the voltage regulation circuitry 300. Only four control signals (PWRUP_FB; PWRUP_CMP, PWRUP_VREG and BYPASS) are shown in FIG. 2, although more control signals may be implemented by the digital logic core 354 in practice”) according to a first output voltage on an output node (fig 2, Vout input to 330 and VOUT_CMP input to 354) and a bypass mode signal (fig 2, BYPASS signal high; fig 3, BYPASS 410; par [0069]), and generating a plurality of power control signals according to the first output voltage and a low power mode signal (fig 2 and fig 3, REF_LP; par [0070, 0072-0074] “low power mode”); and a voltage regulator circuit (fig 2, voltage regulation portion 320), reducing a value of a current flowing through the output node according to the plurality of power control signals (par [0001] “output a reduced voltage”; [0063] “power supply 310 outputs a supply voltage V.sub.IN to a voltage regulation portion 320. The voltage regulation portion 320 in turn provides an output voltage V.sub.OUT”; fig 2, see control signals input to 320), and selectively adjusting a power supply voltage according to the plurality of bypass control signals to generate the first output voltage (fig 5, input control logic 536; par [0100] logic-high voltage level, logic-low voltage level, and 0V).
Regarding claim 2, Bruset discloses the low-dropout regulator according to claim 1, wherein the control circuit converts a level of the bypass mode signal according to a core voltage (fig 2, reference generator 340; par [0079] “The reference voltage VREF generated by the reference generator 340 during the low-power mode is generated from references which are always on from the rest of the chip”; par [0073] REF_LP or BIAS_HP; examiner interprets the “core voltage” to be a voltage generated from another source such as the example given in par [0020] of the instant application) and the first output voltage (fig 2, Vout input to 330 and VOUT_CMP input to 354) to generate a first bypass control signal among the plurality of bypass control signals (fig 2, BYPASS signal and fig 3, BYPASS 410), and generates a second bypass control signal among the plurality of bypass control signals according to the first output voltage, the power supply voltage and the first bypass control signal (fig 2, PWRUP_VREG).
Regarding claim 3, Bruset discloses the low-dropout regulator according to claim 1, wherein the control circuit comprises: a first level shifter, converting a level of the bypass mode signal from a core voltage to the first output voltage to generate a first bypass control signal among the plurality of bypass control signals; and a second level shifter, selectively outputting the power supply voltage or a ground voltage as a second bypass control signal among the plurality of bypass control signals according to the first bypass control signal (Bruset does not implicitly disclose a “level shifter” in their control circuitry portion 350 in fig 2. Bruset does disclose digital logic core 354 which receives signals PWRUP_FB, PWRUP_CMP, and VOUT_CMP as seen in fig 2; par [0068] “intermediate circuitry for converting the control signals from the digital logic core 354, operating in the regulated power domain, to the unregulated power domain”; examiner interprets the intermediate circuitry to be level shifters as those skilled in the art should understand clearly that digital logic core 354 operating in its own power domain, using the described intermediate circuitry is indeed “level-shifting” circuitry to securely transmit the PWRUP_VREG and BYPASS control signals to the analog voltage regulator; par [0094])
Regarding claim 4, Bruset discloses the low-dropout regulator according to claim 1, wherein the control circuit converts a level of the low power mode signal according to a core voltage and the first output voltage to generate a first power control signal among the plurality of power control signals (par [0073] “The reference generator 340 uses always-on references (REF_LP) from the system on chip to generate VREF when the voltage regulation circuitry is operating in the low-power mode”; par[0074] and fig 3 describe the control signals generated and switched during low power mode; pars [0078,0079,0088] describe the circuit operating in low-power mode with reference generator utilizing chip power REF_LP to implement the low power reference signal used to compare output voltage and implement idle, reset, or low voltage regulation control signals; also see pars [0026-0033] for idle, reset, and low power mode operations), and generates a second power control signal among the plurality of power control signals according to the first output voltage, the power supply voltage and the first power control signal (par [0030, 0073-0074] in high power mode the BIAS_HP reference signal is utilized and compared to feedback signal to generate signals PWRUP_VREG and BYPASS which are utilized in high-power mode).
Regarding claim 6, Bruset discloses the low-dropout regulator according to claim 1, wherein the voltage regulator circuit further adjusts a compensation frequency of the voltage regulator circuit according to the plurality of power control signals (fig 5, RCOMP and CCOMP form a Miller compensation network to serve as an internal frequency compensation network for the voltage regulator circuit to stabilizes the control loop and manage the compensation frequency relative to active power control signals, varying load conditions, and power states of the surrounding signals).
Regarding claim 7, Bruset discloses the low-dropout regulator according to claim 1, wherein the voltage regulator circuit comprises: an input-stage circuit (fig 5, error amplifier portion 522 and gate drive circuit 526), selectively outputting the first output voltage or a ground voltage as a feedback voltage according to a first bypass control signal among the plurality of bypass control signals (fig 5, block 536 selective BYPASS, ARST, VSSF(ground) signals and pMOS input pair 530 for receiving the feedback voltage VFB_VREG and reference voltage VREF; pars [0098-0099] describe the functions of 522 and 536), and comparing a reference voltage with the feedback voltage to regulate the first output voltage (fig 5, see block 530 connected to VOUT).
Claims 8-15 are rejected under 35 U.S.C. 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Bruset et al. (US 20250004493 A1) as applied to claim 1 above and further in view of Wang et al (US 11962307 B2), hereinafter Wang.
Regarding claim 8, Bruset discloses the low-dropout regulator according to claim 1, wherein the voltage regulator circuit (fig 2, voltage regulation portion 320; fig 5, 320) comprises: a first current mirror circuit (fig 5, block 522), adjusting a first bias voltage and a second bias voltage according to the power supply voltage and a first power control signal among the plurality of power control signals (fig 5, block 522 adjusts bias voltages via the upper network using the power supply voltage V_IN and a first power control signal PWRUP_VREG); a second current mirror circuit (fig 5, circuit block 524), adjusting the first bias voltage and the second bias voltage according to a ground voltage and a second power control signal among the plurality of power control signals (fig 5, circuit block 524 adjusts bias voltages via the lower network connected to the ground voltage VSS and a second power control signal PWRDN_3V0); a regulator circuit (fig 5, gate drive circuit 526), generating a first current according to the first power control signal, the first bias voltage and the power supply voltage, and generating a second current according to the second power control signal, the second bias voltage and the ground voltage, wherein a value of a current flowing through the output node is determined based on the first current and the second current (fig 5, 526 generates and mirrors currents to the output pass transistor 528 to regulate the output node V_OUT; pars [0098-0099]); and a bypass circuit (fig 5, lower portion of gate drive circuit 526), transmitting the power supply voltage to the output node according to a first bypass control signal among the plurality of bypass control signals, and outputting the ground voltage as a second output voltage according to a second bypass control signal among the plurality of bypass control signals, or outputting the first output voltage as the second output voltage (fig 5, 526 along with inputs from 536 uses a logic gate architecture with BYPASS and ARST control signals to bypass or pass specific voltage levels directly to the output path; pars [0069-0071,0098]).
Alternatively, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine prior art elements according to known methods to yield predictable results. Wang discloses a voltage conversion circuit that adjusts a level of an output voltage from a low-dropout regulator and detects varying operating modes utilizing a level adjustment circuit that adjusts a level of a digital signal according to the first voltage, the second voltage, a first bias voltage, a second bias voltage and the first supply voltage so as to generate a digital output signal corresponding to the operating mode (fig 4B, col 8 lines 4-11 and 58+).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Bruset and incorporate the level adjustments and multiple bias voltages as taught by Wang. Bruset appears to be vague with the description of the voltage regulation portion of their invention and relies on what is known in the art The advantage of this design is to bias the control signals according to the operating mode to effectively control the output voltage.
Regarding claim 9, Bruset and Wang disclose the low-dropout regulator according to claim 8, wherein as a number of transistors turned on in the first current mirror circuit according to the first power control signal increases, a number of transistors turned on in the regulator circuit according to the first power control signal decreases and the value of the current flowing through the output node gets lower (Bruset fig 5, Block 534 current mirror circuit controls the active current replication. Under the first power control signal PWRUP_VREG, the number of operational transistors in the mirror increases to adaptively adjust the internal bias currents. Block 524 Governs the loop regulation and feedback comparison (VFB_VREG vs VREF). As PWRUP_VREG changes state, the active transistor count inside the regulation loop drops to transition into a low-power mode. Block 526 & Transistor 528 delivers the stabilized output voltage V_OUT and load current. The combined adjustment across the mirror and regulator stages consequently lowers the output driver current dynamically).
Regarding claim 10, Bruset and Wang disclose the low-dropout regulator according to claim 8, wherein the first current mirror circuit (Bruset fig 5, block 522) comprises: a plurality of transistors (Bruset fig 5, transistors in block 522 but not individually labelled); and a plurality of switches (Bruset fig 5, selective power control switches e.g. PWRUP_VREG, VFB_VREG), coupled to a first transistor among the plurality of transistors (Bruset fig 5, selective power control switch with PWRUP_VREG control input), and selectively turned on according to the first power control signal to turn off the first transistor by using the power supply voltage (Bruset fig 5, first switch to shut off the primary transistor using the supply voltage V_IN and a second switch in 540 that configures the auxiliary transistor as a diode-connected device under power control).
Regarding claim 11, Bruset and Wang disclose the low-dropout regulator according to claim 10, wherein a second transistor among the plurality of transistors is a diode-connected transistor (Bruset fig 5, block 540 left transistor is diode connected).
Regarding claim 12, Bruset and Wang disclose the low-dropout regulator according to claim 10, wherein the plurality of switches comprise: a first switch, selectively turned on according to the first power control signal to turn off the first transistor by using the power supply voltage (Bruset fig 5,PMOS transistor block 540 that has its gate connected to the PWRUP_VREG control line. It selectively pulls the gate of the main mirror transistor up to V_IN “power supply voltage” to shut it off during power control events); and a second switch, selectively turned on according to the first power control signal to configure a second transistor among the plurality of transistors as a diode-connected transistor (Bruset fig 5, PMOS transistor block 540 that is diode-connected; The core mirror pair in block 532 at the bottom of block 534 has a first transistor as the mirror output FET, and a second is the input FET configured as a diode-connected reference).
Regarding claim 13, Bruset and Wang disclose the low-dropout regulator according to claim 8, wherein the regulator circuit (Bruset fig 5, Block 526) comprises: a plurality of transistors, generating the first current according to the power supply voltage and the first bias voltage; and a plurality of switches, selectively turned on according to the first power control signal to turn off a first transistor among the plurality of transistors by using the power supply voltage (Bruset fig 5, Block 526 power-down logic transistors in sub-block 538 receive control signals to turn off the main pass gate path or pull the nodes high during power-saving states).
Regarding claim 14, Bruset and Wang disclose the low-dropout regulator according to claim 13, wherein a second transistor among the plurality of transistors is a diode-connected transistor (Bruset fig 5, block 540 left transistor is diode connected).
Regarding claim 15, Bruset and Wang disclose the low-dropout regulator according to claim 13, wherein the plurality of switches comprise: a first switch, selectively turned on according to the first power control signal to turn off the first transistor by using the power supply voltage (Bruset fig 5,PMOS transistor block 540 that has its gate connected to the PWRUP_VREG control line. It selectively pulls the gate of the main mirror transistor up to V_IN “power supply voltage” to shut it off during power control events); and a second switch, selectively turned on according to the first power control signal to configure a second transistor among the plurality of transistors as a diode-connected transistor (Bruset fig 5, PMOS transistor block 540 that is diode-connected; The core mirror pair in block 532 at the bottom of block 534 has a first transistor as the mirror output FET, and a second is the input FET configured as a diode-connected reference).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Bruset et al. (US 20250004493 A1) as applied to claim 1 above, and further in view of Gasparini (US 20140139029 A1).
Regarding claim 5, Bruset discloses the low-dropout regulator according to claim 1.
Bruset fails to offer detailed description of its digital logic core 354 that outputs control signals to the rest of the voltage regulation circuitry 300 in fig 2. It would be obvious to one skilled in the art to implement logic control block 354 to manages power-up and bypass sequencing between different operating domains. Because these control signals interface across distinct voltage levels and complementary logic states, implementing standard level shifters for voltage translation and inverters for signal inversion represents routine, conventional engineering design. Because Bruset does not teach the conventional design in its disclosure we rely on a secondary reference.
Gasparini discloses a low-dropout regulator that utilizes a control circuit with level shifters and inverter for receiving a control signal and outputting a control voltage. Gasparini discloses wherein the control circuit (fig 3, control logic 13 and level shifters 22 and 24) comprises: a first level shifter (fig 3, LS 22), converting a level of the low power mode signal from a core voltage to the first output voltage to generate a first signal (par [0027-0028] “level shifters 22 and 24 adapt the voltage value of the control signal S.sub.CTR' and S.sub.CTR'' (e.g., in the range 1.8V-3.6V) to the value accepted by the gate terminals G of the transistors 16a, 16b, 17a, 17b. The level shifters 22 and 24 are of a known type, and thus they are not described in detail”); an inverter (fig 3, inverter 26), generating a first power control signal among the plurality of power control signals according to the first signal (par [0028]” output signal S.sub.CMP.sub.--.sub.1 from the first comparator 11 is inverted before being inputted to the second level shifter 24”); and a second level shifter (fig 3, LS 24), converting a level of the first power control signal from the first output voltage to the power supply voltage to generate a second power control signal among the plurality of power control signals (par [0027-0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Bruset and incorporate the use of level shifters and inverter as taught by Gasparini. The advantage of this design is to receive a control signal and provide a control voltage having a value accepted by the gate terminals of the transistors.
Conclusion
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838 /THIENVU V TRAN/Supervisory Patent Examiner, Art Unit 2838
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