DETAILED ACTION
Claims 1-16 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 12/06/2024 for application number 18/971,302.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a corresponding module” in claims 6 and 12.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5, 7, 9-11, 13, 15, 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 2015/0113192 A1).
Regarding claim 1, Xie teaches power management system (Figure 5), comprising:
a system power management interface (SPMI) master circuit (Figure 5, master device 31 and “system includes a Master, a slave device, and a PMBus, where the Master accesses the slave device by using the PMBus, so as to perform power management;” par 0014);
a SPMI slave circuit (Figure 5, slave device 32 and paragraphs 14, 65); and
an interface bus, connected between the SPMI master circuit and the SPMI slave circuit, wherein the interface bus is a SPMI (Figure 5, power management bus PMBus 33 and “PMBus is a specified digital communications protocol for controlling power conversion and managing a component. In power management, the PMBus is used as a management interface of a power supply chip of the slave device. The Master may configure, monitor, and operate a power converter of the slave device according to a standard command set. Specifically, by using the PMBus command, the Master may configure a working parameter of a power supply, monitor work of the power supply, perform correct measurement according to a failure and an alarm, and so on.” Par 0032);
wherein the SPMI master circuit is configured to:
transmit a command to the SPMI slave circuit through the interface bus (“a command sending unit 3111 configured to send a PMBus command to the slave device 32 by using the PMBus 33;” par 0066 and Figure 5); and
perform a retransmission process (Figures 2 and 3) which comprises:
retransmitting the command to the SPMI slave circuit through the interface bus, in response to not receiving an acknowledgement message from the SPMI slave circuit for longer than a pre-determined period of time after transmission of the command (“When the power supply chip cannot respond to the Master, the data bus is kept at a low level, so as to enable the Master to learn that there is an error in sending of the data,” par 0051 and “the power supply chip is a slave device” par 0048 and “start timing when the number of times that the PMBus command fails to be sent is less than the preset value; and the command sending unit is further configured to resend the PMBus command when timing duration of the timing unit reaches resending time.” Par 0014 and “The Master starts timing for the PMBus command, waits for the timing to reach resending time, and then performs step 201 again.” Par 0056 and Figures 2 and 3) [the master detects lack of an acknowledgement signal and waits for a set time period before retransmitting the command].
Claims 7 and 13 correspond to claim 1 and are rejected accordingly.
Regarding claim 4, Xie teaches the power management system as claimed in claim 1, wherein the retransmission process further comprises: determining not to retransmit the command to the SPMI slave circuit in response to receiving the acknowledgement message from the SPMI slave circuit (“The Master obtains a response from the power supply chip each time when sending data of one byte to the power supply chip.” Par 0051 and “if the PMBus command has no error, the process is ended after the PMBus command is sent.” Par 0050 and Figures 2 and 3).
Claims 10 and 16 correspond to claim 4 and are rejected accordingly.
Regarding claim 3, Xie teaches the power management system as claimed in claim 1, wherein the retransmission process further comprises:
recording a number of times that the command is retransmitted (“Determine whether the number of times that the PMBus command has an error is less than a preset value configured by the system.” par 0053 and Figure 2, step 202-203); and
determining not to retransmit the command to the SPMI slave circuit in response to the number of times that the command is retransmitted being higher than a pre-determined number (“if resending is not successful, step 4, step 5, and step 6 in FIG. 3 are circularly performed until a maximum number of error times is reached, and step 7, step 8, and step 3 are performed, and then the process is ended.” Par 0062 and Figures 2 and 3).
Claims 9 and 15 correspond to claim 3 and are rejected accordingly.
Regarding claim 5, Xie teaches the power management system as claimed in claim 1, wherein the SPMI slave circuit is a power management integrated circuit (PMIC) (“a management interface of a power supply chip of the slave device.” Par 0032 and “As a management interface of a power supply chip, the PMBus is more widely used … master … control a power supply chip in a same slave device is used as an example.” par 0005) [the slave device is a power supply chip that utilizes a management interface for control which is functionally equivalent to a PMIC].
Claim 11 corresponds to claim 5 and is rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 6, 8, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Graif et al. (US 10,572,439 B1).
Regarding claim 2, Xie teaches the power management system as claimed in claim. However, Xie does not explicitly teach wherein the command comprises a control bit that instructs whether the SPMI master circuit has to perform the retransmission process on the command.
In the analogous art, Graif teaches wherein the command comprises a control bit (Figure 13, bit 1358) that instructs whether the SPMI master circuit has to perform the retransmission process on the command (“Some slave devices may be unable to respond within the one-clock cycle limit and may provide a negative acknowledgement, causing the master device to resend the read command.” Col. 4, ll. 13-16 and Figures 4 and 13 (ACK/NACK bit 1358) and column 12-13) [the negative acknowledgement (NACK) is part of the command because it is a single bit that is in a single clock interval following the master’s transmission of the address and write/read bit; the NACK (high logic state) is a signal that informs the master that the command failed which informs of a retransmission that is required].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Xie and Graif before him before the effective filing date of the claimed invention, to have modified Xie to incorporate the teachings of Graif to incorporate a control bit in the command to provide immediate feedback on the status of the command being sent, allow the master to resend the command if necessary and reduce the number of idle period occurrences. (Graif, column 8)
Claims 8 and 14 correspond to claim 2 and are rejected accordingly.
Regarding claim 6, Xie teaches the power management system as claimed in claim 1. However, Xie does not explicitly teach further comprising: a power management interface (PMIF) connected to the SPMI master circuit; wherein the PMIF includes a plurality of channels, each of the channel receives the command from a corresponding module and transmits the command to the SPMI master circuit.
In the analogous art, Graif teaches further comprising:
a power management interface (PMIF) connected to the SPMI master circuit (“The processing circuit 102 [master] may include or control a power management function that configures and manages the operation of the apparatus 100.” Col. 5, ll. 27-29);
wherein the PMIF includes a plurality of channels, each of the channel receives the command from a corresponding module and transmits the command to the SPMI master circuit (“The processing circuit 102 may provide one or more buses 118 a, 118 b, 120 that certain enable certain devices 104, 106, and/or 108 [hardware circuit chips] to communicate … the ASIC 104 may include a bus interface circuit 116 that includes a combination of circuits, counters, timers, control logic and other configurable circuits or modules.” Col. 5, ll. 19-25 and “The processing circuit 102 may be controlled by an operating system that may provide an application programming interface (API) layer that enables the one or more processors 112 to execute software modules” col. 4, ll. 56-59 and Figure 1) [the buses and API layer correspond to the channels through which circuit chips and software programs send their commands to be received and managed by the power management function].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Xie and Graif before him before the effective filing date of the claimed invention, to have modified Xie to incorporate the teachings of Graif to include a power management system to manage the operations of the system and to oversee the interactions between hardware and software components. (Graif, column 5)
Claim 12 is covered by claim 6 and is rejected accordingly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Tsai (US 2022/0113787 A1) teaches a master-slave power supply device that supplies power to a master device in response to a start command, where a power control module switches to a slave mode and operates therein in response to acquiring data. The power control module enables the power supply unit to supply power to the master device only when the power control module operates in the slave mode.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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