DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed 18 September 2026 have been fully considered but they are not persuasive.
Applicant argues Td of Lee is only for the center region and not the upper and lower regions. The examiner disagrees with applicant. Lee discloses dielectric layers 111 are used in both the central region and the upper and lower regions and further teaches the thickness, Td, can be 0.6 microns or less ([0046-0047]). As 111 is used for all regions the thickness will be identical. Furthermore, fig. 2 clearly shows the thickness of the dielectric layers in the central region (120A) has a thickness of Td and the dielectric layers in the upper and lower regions (120B) have a thickness of Td. Thus, Lee discloses independent claims 1 & 15 as amended. Applicant further argues Kim fails to disclose a ratio of the thickness of the central region and the upper and lower regions and thus fails to disclose the claims as currently presented. The examiner disagrees. Kim discloses the dielectric layers (which would be all dielectric layers) have a thickness of 2 times the thickness of the internal electrodes. Finally, new grounds of rejection have been made based on the amendments. All claims stand rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 7-8, 10-11, 15, 17-18, & 20-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2015/0136462).
In regards to claim 1, Lee ‘462 discloses
A multilayer electronic component, comprising:
a body (110 – fig. 2; [0034]) including a capacitance formation portion including a dielectric layer (111 – fig. 2; [0034]) and first and second internal electrodes (121-122 – fig. 2; [0034]) disposed alternately in a first direction with the dielectric layer interposed therebetween, and cover portions (fig. 2) disposed in an upper portion and a lower portion of the capacitance formation portion in the first direction; and
external electrodes (131-132 – fig. 2; [0036]) disposed on the body,
wherein the capacitance formation portion includes outer regions (120B – fig. 2; [0063]) adjacent to the cover portion and a central region (120A – fig. 2; [0063]) other than the outer region, and
wherein an average thickness of the first internal electrode included in the outer regions is greater than an average thickness of the first internal electrode included in the central region, and an average thickness of the second internal electrode included in the outer regions is greater than an average thickness of the second internal electrode included in the central region (table 1 – sample 1-2 & [0063]),
wherein, when an average thickness of the dielectric layer included in the central region is defined as tda and an average thickness of the dielectric layer included in the outer regions is defined as tdb, 0.9 ≤ tdb/tda ≤ 1.1 is satisfied (fig. 2; [0071])
In regards to claim 4, Lee ‘462 discloses
The multilayer electronic component of claim 1, wherein the cover portion includes an upper cover portion (uppermost dielectric layer – fig. 2) disposed in an upper portion of the capacitance formation portion in the first direction and a lower cover portion (lowermost dielectric layer – fig. 2) disposed in a lower portion of the capacitance formation portion in the first direction,
wherein the outer regions includes an upper outer region (seen in fig. 2) adjacent to the upper cover portion and a lower outer region (seen in fig. 2) adjacent to the lower cover portion, and
wherein the upper outer region includes one or more of each of the first and second internal electrodes, and the lower outer region includes one or more of each of the first and second internal electrodes (seen in fig. 2).
In regards to claim 7, Lee ‘462 discloses
The multilayer electronic component of claim 1, wherein, when a sum of a number of first and second internal electrodes included in the central region is defined as Na (fig. 2 – 6 shown), and a sum of a number of first and second internal electrodes included in the outer regions is defined as Nb, Nb/Na is 0.04 or more (fig. 2 – 12 shown; thus Nb/Na=12/6=2).
In regards to claim 8, Lee ‘462 discloses
The multilayer electronic component of claim 1, wherein, when a sum of a number of first and second internal electrodes included in the central region is defined as Na and a sum of a number of first and second internal electrodes included in the outer regions is defined as Nb, Nb/Na is 0.04 or more and 25 or less (fig. 2 – Nb/Na=12/6=2).
In regards to claim 10, Lee ‘462 discloses
The multilayer electronic component of claim 1, wherein the cover portion includes the dielectric layer and does not include the first and second internal electrodes (fig. 2).
In regards to claim 11, Lee ‘462 discloses
The multilayer electronic component of claim 1, wherein the cover portion includes the dielectric layer (fig. 2).
In regards to claim 12, Lee ‘462 discloses
The multilayer electronic component of claim 1, wherein the cover portion includes an upper cover portion (fig. 2) disposed in an upper portion of the capacitance formation portion in the first direction and a lower cover portion (fig. 2) disposed in a lower portion of the capacitance formation portion in the first direction, and the outer regions includes an upper outer region (fig. 2) adjacent to the upper cover portion and a lower outer region (fig. 2) adjacent to the lower cover portion, and
wherein, when an average thickness of the upper outer region in the first direction is defined as tb1 and an average thickness of the lower outer region in the first direction is defined as tb2, 0.9 ≤ tb1/tb2 ≤ 1.1 is satisfied (fig. 2; the upper and lower regions each include 6 electrodes with thickness of b and 6 dielectric layers with thickness Td and thus the thickness the overall thicknesses of each region will be equal (i.e. tb1/tb2=1)).
In regards to claim 13, Lee ‘462 discloses
The multilayer electronic component of claim 1, wherein, when an average thickness in the first direction of the outer regions is defined as tb and an average thickness in the first direction of the central region is defined as ta, tb/ta is 0.03 or more fig. 2; table 1 – sample 1 – thickness of central region is 5Td+6a and thickness of outer region is 12Td+12b and a=0.95b therefore thickness of the central portion is 5Td+5.7b and it is noted that the value of (12Td+12b)(5Td+5.7b) will be greater than 0.03).
In regards to claim 15, Lee ‘462 discloses
A multilayer electronic component, comprising:
a top cover portion and a bottom cover portion disposed above and below a capacitance forming portion in a stacking direction (seen in fig. 2), the capacitance forming portion comprising:
an uppermost pair of internal electrodes (121-122 – fig. 2; [0034]) with a dielectric layer (111 – fig. 2; [0034]) disposed therein, disposed adjacent the top cover portion,
a lowermost pair of internal electrodes (121-122 – fig. 2; [0034]) with a dielectric layer (111 – fig. 2; [0034]) disposed therein, disposed adjacent the bottom cover portion, and
central pairs of internal electrodes (121-122 – fig. 2; [0034]) disposed between the uppermost and lowermost pairs,
wherein an average thickness of the central pairs of internal electrodes is smaller than an average thickness of the uppermost and/or lowermost pairs of internal electrodes (table 1 – sample 1-2 & [0063]),
wherein an average thickness of the dielectric layers disposed between the central pairs of internal electrodes is substantially the same as an average thickness of the dielectric layers disposed between the uppermost and/or lowermost pairs of internal electrodes (fig. 2; [0071]).
In regards to claim 17, Lee ‘462 discloses
The multilayer electronic component of claim 15, wherein the average thickness of central pairs of internal electrodes is substantially the same among the central pairs (fig. 2; [0062]).
In regards to claim 18, Lee ‘462 discloses
The multilayer electronic component of claim 15, wherein the average thickness of the uppermost and/or lowermost pairs of internal electrodes is substantially the same among the uppermost and/or lowermost pairs (fig. 2; [0062]).
In regards to claim 20, Lee ‘462 discloses
The multilayer electronic component of claim 1, wherein the external electrodes comprise a first external electrode (131) and a second external electrode (132), and
wherein the first internal electrode is connected to the first external electrode, and the second internal electrode is connected to the second external electrode (fig. 2; [0080]).
In regards to claim 21, Lee ‘462 discloses
The multilayer electronic component of claim 15, further comprising external electrodes disposed on a body and including a first external electrode (131 – fig. 2; [0036]) and a second external electrode (131 – fig. 2; [0036]),
wherein the internal electrodes of the uppermost pair, the lowermost pair, and the central pairs are alternately connected to the first external electrode and the second external electrode (fig. 2; [0080]).
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)2 as being anticipated by Nishibayashi et al. (US 2025/0372312).
In regards to claim 15, Nishibayashi ‘312 discloses
A multilayer electronic component, comprising:
a top cover portion (12 – fig. 3; [0028]) and a bottom cover portion (12 – fig. 3; [0028]) disposed above and below a capacitance forming portion in a stacking direction (seen in fig. 2), the capacitance forming portion comprising:
an uppermost pair of internal electrodes (topmost 20 & 50 – fig. 2; [0026-0027]) with a dielectric layer (14 – fig. 2-3; [0023]) disposed therein, disposed adjacent the top cover portion,
a lowermost pair of internal electrodes (20A & 50A – fig. 2; [0032-0033]) with a dielectric layer (14 – fig. 2-3; [0023]) disposed therein, disposed adjacent the bottom cover portion, and
central pairs of internal electrodes (middle 20s & 50s – fig. 2; [0026-0027]) disposed between the uppermost and lowermost pairs,
wherein an average thickness of the central pairs of internal electrodes is smaller than an average thickness of the uppermost and/or lowermost pairs of internal electrodes (fig. 2; [0044-0045] – less than lowermost pair),
wherein an average thickness of the dielectric layers disposed between the central pairs of internal electrodes is substantially the same as an average thickness of the dielectric layers disposed between the uppermost and/or lowermost pairs of internal electrodes (fig. 2; [0022-0023] & [0059-0061] – noting the thickness of the dielectric layers are substantially the same).
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2020/0118748).
In regards to claim 1, Kim ‘748 discloses
A multilayer electronic component, comprising:
a body (110 – fig. 3; [0016]) including a capacitance formation portion (La & Lb portions – fig. 3) including a dielectric layer and first and second internal electrodes (121-122 & 125-126 – fig. 3; [0057]) disposed alternately in a first direction with the dielectric layer interposed therebetween, and cover portions (Lc – fig. 3) disposed in an upper portion and a lower portion of the capacitance formation portion in the first direction; and
external electrodes (131-132 – fig. 3; [0016]) disposed on the body,
wherein the capacitance formation portion includes outer regions (Lb – fig. 3) adjacent to the cover portion and a central region (La – fig. 3) other than the outer region, and
wherein an average thickness of the first internal electrode included in the outer regions is greater than an average thickness of the first internal electrode included in the central region, and an average thickness of the second internal electrode included in the outer regions is greater than an average thickness of the second internal electrode included in the central region (fig. 3; table 1 & [0058]),
wherein, when an average thickness of the dielectric layer included in the central region is defined as tda and an average thickness of the dielectric layer included in the outer regions is defined as tdb, 0.9 ≤ tdb/tda ≤ 1.1 is satisfied (fig. 3; [0020], [0022], & [0042] – dielectric layers used to form stack have substantially the same thickness of 2 times the thickness of the electrodes 121 & 122).
In regards to claim 12, Kim ‘748 discloses
The multilayer electronic component of claim 1, wherein the cover portion includes an upper cover portion (region of Lc – fig. 3) disposed in an upper portion of the capacitance formation portion in the first direction and a lower cover portion (region of Lc – fig. 3) disposed in a lower portion of the capacitance formation portion in the first direction, and the outer regions includes an upper outer region (region of Lb – fig. 3) adjacent to the upper cover portion and a lower outer region (region of Lb – fig. 3) adjacent to the lower cover portion, and
wherein, when an average thickness of the upper outer region in the first direction is defined as tb1 and an average thickness of the lower outer region in the first direction is defined as tb2, 0.9 ≤ tb1/tb2 ≤ 1.1 is satisfied (fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-3, 5-6, & 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘748.
In regards to claim 2,
Kim ‘748 discloses wherein, when an average thickness of a first internal electrode included in the central region is defined as tea, and an average thickness of the first internal electrode included in the outer regions is defined as teb, 1.2 ≤ teb/tea is satisfied ([0058]). Kim ‘748 fails to explicitly discloses 1.6 ≤ teb/tea ≤ 2.0 is satisfied.
However, Kim ‘748 discloses that teb/tea is a result effective variable, particularly for ensuring strong strength from external impacts such as warpage while also preventing delamination ([0055-0056]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Kim ‘748 such that 1.6 ≤ teb/tea ≤ 2.0 is satisfied to obtain a capacitor with good protection from warpage and delamination, as taught by Kim ‘748. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regards to claim 3,
Kim ‘748 further discloses wherein tea is 300nm or more 937.5nm or less, and a teb is 480nm or more 1500nm ([0038] – tea is 400 nm or less therefore teb is 800 nm or less).
In regards to claim 5,
Kim ‘748 discloses wherein, wherein, when an average thickness of the second internal electrode included in the central region is defined as tea’ and an average thickness of the second internal electrode included in the outer region is defined as teb’, 1.2 ≤ teb’/tea’ is satisfied ([0058]). Kim ‘748 fails to explicitly discloses 1.6 ≤ teb’/tea’ ≤ 2.0 is satisfied.
However, Kim ‘748 discloses that teb’/tea’ is a result effective variable, particularly for ensuring strong strength from external impacts such as warpage while also preventing delamination ([0055-0056]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Kim ‘748 such that 1.6 ≤ teb/tea ≤ 2.0 is satisfied to obtain a capacitor with good protection from warpage and delamination, as taught by Kim ‘748. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regards to claim 6,
Kim ‘748 discloses wherein tea and tea’ satisfy 0.9 ≤ tea/tea’ ≤ 1.1, and teb and teb’ satisfy 0.9 ≤ teb/teb’ ≤ 1.1 (fig. 3; [0057]).
In regards to claim 9,
Kim ‘748 discloses wherein, when an average thickness of a first internal electrode included in the central region is defined as tea, and an average thickness of the first internal electrode included in the outer regions is defined as teb, 1.2 ≤ teb/tea is satisfied ([0058]),
wherein, when a sum of numbers of the first and second internal electrodes included in the central region is defined as Na and a sum of numbers of the first and second internal electrodes included in the outer regions is defined as Nb, Nb/Na is 0.04 or more and 2.59 or less (fig. 3; Nb=4, Na=4; thus Nb/Na=1). Kim ‘748 fails to explicitly discloses 1.8 ≤ teb/tea ≤ 2.0 is satisfied.
However, Kim ‘748 discloses that teb/tea is a result effective variable, particularly for ensuring strong strength from external impacts such as warpage while also preventing delamination ([0055-0056]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Kim ‘748 such that 1.8 ≤ teb/tea ≤ 2.0 is satisfied to obtain a capacitor with good protection from warpage and delamination, as taught by Kim ‘748. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishibayashi ‘312.
In regards to claim 16,
Nishibayashi ‘312 discloses wherein the average thickness of the uppermost and/or lowermost pairs of internal electrodes is 1.5 times or more of that of the central pairs of internal electrodes ([0044-0045]). Nishibayashi ‘312 fails to explicitly discloses 1.6 times to 2.0 times.
However, Nishibayashi ‘312 discloses that ratio of the internal electrode thicknesses is a result effective variable, particularly for ensuring low ESL while ensuring large capacitance ([0044-0045]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Nishibayashi ‘312 such that the ratio is 1.6-2.0 to obtain a capacitor with low ESL and large capacitance, as taught by Nishibayashi ‘312. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JP2007158266A – fig. 2
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David M Sinclair/Primary Examiner, Art Unit 2847
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