DETAILED ACTION
Claims 1-20 are pending.
The office acknowledges the following papers:
Patent application filed on 12/6/2024.
Priority
The effective filing date for the subject matter defined in the pending claims in this application is 6/25/2021.
Drawings
The Examiner contends that the drawings submitted on 12/6/2024 are acceptable for examination proceedings.
Specification
The disclosure is objected to because of the following informalities:
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The Applicant’s cooperation is requested in correcting any errors of which the Applicant may become aware.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Applicants can file an eTerminal Disclaimer (eTD) in utility applications filed under 35 U.S.C. 111(a) or in compliance with 35 U.S.C. 371, and design applications. Filing an eTD via EFS-Web is highly recommended due to an extensive backlog for processing paper TDs. However, applicants may still file a TD for manual review.
Claims 1-10 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1 and 3-10 of U.S. Patent No. 12,248,333. Although the conflicting claims are not identical, they are not patentably distinct from each other because U.S. Patent No. 12,248,333 contains every element of claims 1-10 of the instant application and thus anticipates the claims of the instant application. Claims of the instant application therefore are not patently distinct from earlier patent claims and as such are unpatentable over obvious-type double patenting. A later application claim is not patently distinct from an earlier claim if the later claim is anticipated by the earlier claim.
Instant Application
Patent 12,248,333
1. An array processor, comprising:
1. A vector processing unit, comprising:
a buffer configured to store a set of data samples that are retrieved from a register of the array processor; and
a buffer configured to store a set of vector data samples that are retrieved from one or more vector registers; and
processor circuitry configured to:
vector processing circuitry configured to:
for a first processor instruction, perform a first processing operation using a first subset of the set of data samples; and
for a first vector processor instruction that is executed during a first one of a plurality of clock cycles, perform a first vector processing operation using a first portion of the stored set of vector data samples,
for a second processor instruction, perform a second processing operation using a second subset of the set of data samples,
for a second vector processor instruction that is executed during a second one of the plurality of clock cycles, perform a second vector processing operation using a second portion of the stored set of vector data samples,
wherein a portion of the first subset of the set of data samples used to perform the first processing operation are provided as a portion of the second subset of the set of data samples used to perform the second processing operation.
wherein a predetermined number of the first portion of the stored set of vector data samples used to perform the first vector processing operation are the same as the second portion of the stored set of vector data samples used to perform the second vector processing operation.
Dependent claims 2-10 are read upon by the dependent claims 3-10 of U.S. Patent No. 12,248,333.
Claims 11-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11-20 of U.S. Patent No. 12,248,333 in view of Official Notice.
Instant Application
Patent 12,248,333
11. A computing device, comprising:
11. A system on a chip (SoC), comprising:
an array processor, comprising:
a plurality of registers; and
a plurality of vector registers; and
a plurality of processing units, each one of the plurality of processing units comprising (i) a buffer configured to store a set of data samples that are retrieved from one or more of the plurality of registers, and (ii) array processor circuitry;
a plurality of vector processing units, each one of the plurality of vector processing units comprising: a buffer configured to store a set of vector data samples that are retrieved from one or more of the plurality of vector registers; and
a memory configured to store executable instructions; and
processing circuitry configured to execute the executable instructions stored in the memory to control data processing of the array processor and to enable a processing unit from among the plurality of processing units to:
vector processing circuitry configured to:
for a first processor instruction, perform a first processing operation using a first subset of the set of data samples; and
for a first vector processor instruction that is executed during a first one of a plurality of clock cycles, perform a first vector processing operation using a first portion of the stored set of vector data samples, and
for a second processor instruction, perform a second processing operation using a second subset of the set of data samples,
for a second vector processor instruction that is executed during a second one of the plurality of clock cycles, perform a second vector processing operation using a second portion of the stored set of vector data samples,
wherein a portion of the first subset of the set of data samples used to perform the first processing operation are provided as a portion of the second subset of the set of data samples used to perform the second processing operation.
wherein a predetermined number of the first portion of the stored set of vector data samples used to perform the first vector processing operation are the same as the second portion of the stored set of vector data samples used to perform the second vector processing operation.
Additionally, Official Notice disclosed:
an array processor (Official notice is given that processing systems can include array processors for the advantage of high performance execution of parallel tasks. Thus, it would have been obvious to one of ordinary skill in the art to incorporate array processors in the claim of the above patent.);
a memory configured to store executable instructions (Official notice is given that processing systems include memory to store executable instructions for the advantage of processing software tasks. Thus, it would have been obvious to one of ordinary skill in the art to incorporate memory in the claim of the above patent.).
Dependent claims 12-20 are read upon by the dependent claims 12-20 of U.S. Patent No. 12,248,333.
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Luo et al. (U.S. 2020/0264921), taught vector scheduling.
Muralimanohar (U.S. 2018/0173677), taught sparse matrix processing.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183