DETAILED ACTION
This is in response to communication filed on 6/25/2026.
Status of Claims
Claims 1 – 20 are pending, of which claims 1, 17, and 18 are in independent form.
Claim Rejections - 35 USC § 112
In light of applicant’s amendments to the claims, the examiner withdraws the previous rejection to the claims under 35 USC 112.
Claim Objections
In light of applicant’s amendments to the claims, the examiner withdraws the previous objection to the claims.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 11, 12, 17, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arimilli et al., U.S. Patent Application 2005/0132148 (hereinafter referred to as Arimilli).
Referring to claim 1, Arimilli discloses “A data processing apparatus” (Fig. 1) “comprising: receive circuitry configured to receive a memory access instruction” (Fig. 9 and [0045] the process begins at block 100 in response to receipt by IMC 18 of a request transaction) “comprising an indication of a target address” ([0045] “The request transaction preferably includes a transaction type (e.g., read, read-with-intent-to-modify, flush, kill, etc.), a thread ID of the instruction that generated the request transaction, and a request address”), “wherein the target address is associated with one of a plurality of memory targets” ([0048] IMC 18 also determines the memory bank 56 in the attached system memory 22 to which the specified request address maps); “prediction circuitry” ([0043] the row prediction algorithm employed by IMC 18, Fig. 5A steps 108-110 speculating) “configured to perform a prediction of one of the plurality of memory targets to which the memory access instruction is associated, based on an address associated with the memory access instruction” ([0059] IMC determines via a speculation algorithm ('prediction') whether or not to hold open the row containing the request address following the access. Fig. 5A step 106 determines memory bank to which request address maps and step 108 determines whether to initiate speculative memory access); “and forward circuitry configured to forward a memory access request based on the memory access instruction to the one of the plurality of memory targets” (Fig. 5A after speculating is determined initiate access to memory at 120. [0033] “IMC 18 initiates a memory access to a DIMM 26 by asserting or deasserting a read/write (R/W) control line and supplying a real address to an RD chip 24, which in turn, supplies the control signal and real address to the DIMM 26.” Fig. 9 and [0069] “once a memory access request is transferred from request buffer 300 to MC queues 302 by central state machine 306, central state machine 306 will (absent an intervening message) direct an access to system memory 22 in accordance with the memory access request and historical access information provided by RAS state machines (SM) 304 and memory speculation table (MST) 310”).
As per claim 2, Arimilli discloses “the prediction circuitry is configured to perform the prediction by performing a hashing algorithm that uses the address associated with the memory access instruction” ([0046], [0048], [0055], [0057] determining whether or not the request address specified is assigned to a storage location in the attached system memory, this determination is made by hashing the request address specified by the request transaction. Also [0048] “IMC 18 then applies a selected timing speculation algorithm to the historical information contained within timing speculation field 84 to determine whether or not to initiate a speculative memory access”).
As per claim 11, Arimilli discloses “determination circuitry configured to perform a determination of which of the plurality of memory targets the target address is associated, based on the target address” ([0059] IMC determines via a speculation algorithm ('prediction') whether or not to hold open the row containing the request address following the access. Fig. 5A step 106 determines memory bank to which request address maps and step 108 determines whether to initiate speculative memory access), “wherein the prediction is completed before the determination is completed” ([0045] IMC 18 determines whether the IMC is responsible for servicing the request transaction, this is, the speculation was correct or not).
As per claim 12, Arimilli discloses “in response to the determination differing from the prediction, the determination circuitry is configured to cause a corrective action to be taken” ([0045] if the speculation was incorrect, discard any erroneous data associated with the request transaction).
Referring to claim 17, claim 1 recites the corresponding limitations as that of claim 17. Therefore, the rejection of claim 1 applies to claim 17.
Referring to claim 18, claim 1 recites the corresponding limitations as that of claim 18. Therefore, the rejection of claim 1 applies to claim 18.
Further, Arimilli discloses “A non-transitory computer-readable medium to storing computer-readable code for fabrication of a data processing apparatus comprising” the features of claim 1 (IMC integrated memory controller, [0026] cache hierarchy 16 provides storage for data and instructions, [0066] software executed by cores).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Arimilli in view of Ishii et al., U.S. Patent Application 2021/0232400 (hereinafter referred to as Ishii).
As per claim 3, Arimilli discloses “the address associated with the memory access instruction” ([0045] request address); “and the hashing algorithm takes” the address “as an input” ([0048] IMC 18 also determines the memory bank 56 in the attached system memory 22 to which the specified request address maps. Fig. 5A step 106 determines memory bank to which request address maps and step 108 determines whether to initiate speculative memory access. [0046], [0048], [0055], [0057] determining whether or not the request address specified is assigned to a storage location in the attached system memory, this determination is made by hashing the request address specified by the request transaction).
Arimilli does not appear to explicitly disclose “the address associated with the memory access instruction is a program counter value; and the hashing algorithm takes a subset of bits of the program counter value as an input.”
However, Ishii discloses another prediction mechanism (Fig. 1 branch predictor 40 includes a branch target buffer (BTB) 42 and a branch direction predictor (BDP) 44. [0002] allowing subsequent instructions beyond the branch to be fetched for decoding and execution before the actual outcome of the branch is determined), wherein “the address associated with the memory access instruction is a program counter value; and the hashing algorithm takes a subset of bits of the program counter value as an input” ([0024] In some implementations, the branch predictor may perform a separate lookup for each instruction, and in this case the current block may comprise a single instruction. [0026] the indexing information could include a program counter address identifying the current block of one or more instructions. [0057] FIG. 2 shows an example of the BTB 42, which acts as a cache comprising a number of entries 46 which are indexed based on program counter address representing the address of a current block of one or more instructions for which the prediction lookup is to be made. Fig. 4 and [0066] The base predictor T0 is indexed based on the program counter PC alone, while the TAGE tables T1 to T4 are indexed based on a hash value generated by applying a hash function to the PC 64 and successively increasing lengths of history information 66). Also note that “a subset of bits of the program counter value” may include the entire program counter value. In mathematical and computing terms, a ‘subset’ may include the entire set.
Arimilli and Ishii are analogous art because they are from the same field of endeavor, which is memory access with prediction.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Arimilli and Ishii before him or her, to modify the teachings of Arimilli to include the teachings of Ishii so that the hashing algorithm takes the program counter value as an input.
The motivation for doing so would have been to provide a means for determining which instruction to be fetched next (and which instruction memory to access) (as stated by Ishii at [0057], [0063], and [0094]).
Therefore, it would have been obvious to combine Ishii with Arimilli to obtain the invention as specified in the instant claim.
Claims 7 – 9 are rejected under 35 U.S.C. 103 as being unpatentable over Arimilli in view of Yalavarti et al., U.S. Patent Application 2020/0081716 (hereinafter referred to as Yalavarti).
As per claim 7, Arimilli discloses “the hashing algorithm takes at least one” input
([0048] IMC 18 also determines the memory bank 56 in the attached system memory 22 to which the specified request address maps. Fig. 5A step 106 determines memory bank to which request address maps and step 108 determines whether to initiate speculative memory access. [0046], [0048], [0055], [0057] determining whether or not the request address specified is assigned to a storage location in the attached system memory, this determination is made by hashing the request address specified by the request transaction).
Arimilli does not appear to explicitly disclose “the hashing algorithm takes at least one characteristic bit as an input to indicate a characteristic of a register used to store the target address.”
However, Yalavarti discloses “the hashing algorithm takes at least one characteristic bit as an input to indicate a characteristic of a register used to store the target address” ([0039] table entry has metadata for the count and/or the CTI (branch), such as valid bits, permission bits, etc. [0073] hash value from the program counter (fetch address)).
Arimilli and Yalavarti are analogous art because they are from the same field of endeavor, which is memory access with prediction.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Arimilli and Yalavarti before him or her, to modify the teachings of Arimilli to include the teachings of Yalavarti so that the hashing algorithm takes at least one characteristic bit as an input to indicate a characteristic of a register used to store the target address.
The motivation for doing so would have been to provide a means for conveying further data, such as permissions and validity (as stated by Yalavarti at [0039]).
Therefore, it would have been obvious to combine Yalavarti with Arimilli to obtain the invention as specified in the instant claim.
As per claim 8, Arimilli discloses “each of the target predictions relates to one of the plurality of memory targets” ([0059] IMC determines via a speculation algorithm ('prediction') whether or not to hold open the row containing the request address following the access. Fig. 5A step 106 determines memory bank to which request address maps and step 108 determines whether to initiate speculative memory access).
Arimilli further discloses “storage circuitry configured to store a plurality of mappings” (Fig. 9 MST 310 and Fig. 10 along with [0072] History bit field 322 is preferably implemented as a multiple bit (e.g., four-bit) history field in which each bit represents a respective one of the immediately previous request transactions received by IMC 18 that had a real address mapping to the associated bank and row ID indicated within row ID field 320).
Arimilli does not appear to explicitly disclose “storage circuitry configured to store a plurality of mappings from hashes to target predictions.”
However, Yalavarti discloses “storage circuitry configured to store a plurality of mappings from hashes to target [instruction] predictions” ([0073] hash of PC compared to entries in fetch table).
Arimilli and Yalavarti are analogous art because they are from the same field of endeavor, which is memory access with prediction.
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the teachings of Yalavarti with Arimilli so that a table stores mappings from hashes to memory targets.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Arimilli and Yalavarti before him or her, to modify the teachings of Arimilli to include the teachings of Yalavarti so that the hashing algorithm utilizes stored mappings from hashes to memory target predictions.
The motivation for doing so would have been to provide a means for a central state machine to direct an access to system memory in accordance with the memory access request and mappings/tables (as stated by Yalavarti at [0069]).
Therefore, it would have been obvious to combine Yalavarti with Arimilli to obtain the invention as specified in the instant claim.
As per claim 9, Arimilli discloses “each of the mappings is associated with a confidence value; and the confidence value is used to determine whether the target predictions should be used” ([0059] past prediction success).
Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Arimilli in view of Bouzguarrou et al., U.S. Patent Application 2023/0385066 (hereinafter referred to as Bouzguarrou).
As per claim 10, Arimilli does not appear to explicitly disclose “training circuitry configured to perform training to produce the mappings from hashes to target predictions.”
However, Bouzguarrou discloses “training circuitry configured to perform training to produce the mappings from hashes to target predictions” ([0048] The prediction circuitry may look up the first prediction table based on a hash value derived from a program counter address. [0091] “the polymorphic branch target prediction circuitry 46 may have been trained, based on legitimate execution of instructions.” An “entry is tagged with the EL1 context identifier and specifies a predicted target address 128 of T_Y1, which is one of the legitimate targets of branch X. Similarly, the legitimate training of the polymorphic branch target prediction circuitry 46 causes another entry to be allocated for branch X, tagged with the EL1 context identifier, a tag value, e.g. 0xF4, (derived from the PC of branch X and a pattern of branch history from register 100 that was seen preceding branch X) and the predicted target address of T_X1, which is again one of the legitimate targets of branch X”).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the teachings of Bouzguarrou with Arimilli so that a table stores mappings from hashes to memory targets.
Arimilli and Bouzguarrou are analogous art because they are from the same field of endeavor, which is memory access with prediction.
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the teachings of Bouzguarrou with Arimilli so that training produces mappings from hashes to memory targets.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Arimilli and Bouzguarrou before him or her, to modify the teachings of Arimilli to include the teachings of Bouzguarrou so that training produces mappings from hashes to memory targets.
The motivation for doing so would have been to provide a means for learning from the past to train predictions and improve performance (as stated by Bouzguarrou at [0002]).
Therefore, it would have been obvious to combine Bouzguarrou with Arimilli to obtain the invention as specified in the instant claim.
As per claim 13, Arimilli does not appear to explicitly disclose “the corrective action comprises at least one of: replaying the memory access instruction, correcting the prediction, and stalling execution of one or more instructions.”
However, Bouzguarrou discloses “the corrective action comprises at least one of: replaying the memory access instruction, correcting the prediction, and stalling execution of one or more instructions” ([0064] incorrect prediction, table updating circuitry adjusts).
Arimilli and Bouzguarrou are analogous art because they are from the same field of endeavor, which is memory access with prediction.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Arimilli and Bouzguarrou before him or her, to modify the teachings of Arimilli to include the teachings of Bouzguarrou so that a misprediction is followed by correcting the prediction.
The motivation for doing so would have been to provide a means for learning from the past to train predictions and improve performance (as stated by Bouzguarrou at [0002]).
Therefore, it would have been obvious to combine Bouzguarrou with Arimilli to obtain the invention as specified in the instant claim.
Claims 14 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Arimilli in view of ‘Armv8-M Memory Model and Memory Protection User Guide - Version 1.1’ (hereinafter referred to as Arm).
As per claim 14, Arimilli discloses “the plurality of memory targets include” RAMs ([0102] the present invention is equally applicable to other memory technologies such as NVRAM, EDRAM, etc.).
Arimilli does not appear to explicitly disclose “the plurality of memory targets include SRAMs.”
However, Arm discloses “the plurality of memory targets include SRAMs” (Tightly Coupled Memory (TCM) section states “Typically, RAM or RAM-like memory (for example SRAM or FRAM) are connected to the TCM port, that is Normal-type memory in Arm architecture”).
Arimilli and Arm are analogous art because they are from the same field of endeavor, which is memory access methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Arimilli and Arm before him or her, to modify the teachings of Arimilli to include the teachings of Arm so that the memory targets include SRAMs.
The motivation for doing so would have been to provide low-latency memory that can be used by the processor and configured to capture or return data in a single cycle (as stated by Arm in the first paragraph of Tightly Coupled Memory (TCM) section).
Therefore, it would have been obvious to combine Arm with Arimilli to obtain the invention as specified in the instant claim.
As per claim 15, Applicant’s specification states on page 8 lines 16 – 19 “In some examples, there is a two cycle load-use period for executing the memory access instruction. In these examples, the execution of the memory access instruction (i.e. from the time that it is issued) to the time that the data is returned is two processor cycles or less.”
Arm discloses “there is a two cycle load-use period for executing the memory access instruction” (Tightly Coupled Memory (TCM) section states “Typically, RAM or RAM-like memory (for example SRAM or FRAM) are connected to the TCM port, that is Normal-type memory in Arm architecture” and “and configured to capture or return data in a single cycle”).
Arimilli and Arm are analogous art because they are from the same field of endeavor, which is memory access methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Arimilli and Arm before him or her, to modify the teachings of Arimilli to include the teachings of Arm so that there is a two cycle load-use period for executing the memory access instruction.
The motivation for doing so would have been to provide low-latency memory that can be used by the processor and configured to capture or return data in a single cycle (as stated by Arm in the first paragraph of Tightly Coupled Memory (TCM) section).
Therefore, it would have been obvious to combine Arm with Arimilli to obtain the invention as specified in the instant claim.
As per claim 16, Arimilli does not appear to explicitly disclose “the plurality of memory targets include one or more of: a data tightly coupled memory, an instruction tightly coupled memory, an instruction cache, and a data side cache, and an external peripheral bus.”
However, Arm discloses “the plurality of memory targets include one or more of: a data tightly coupled memory, an instruction tightly coupled memory, an instruction cache, and a data side cache, and an external peripheral bus” (Tightly Coupled Memory (TCM) section states “Typically, RAM or RAM-like memory (for example SRAM or FRAM) are connected to the TCM port, that is Normal-type memory in Arm architecture” and “and configured to capture or return data in a single cycle”).
Arimilli and Arm are analogous art because they are from the same field of endeavor, which is memory access methods.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Arimilli and Arm before him or her, to modify the teachings of Arimilli to include the teachings of Arm so that there is a tightly coupled memory.
The motivation for doing so would have been to provide low-latency memory that can be used by the processor and configured to capture or return data in a single cycle (as stated by Arm in the first paragraph of Tightly Coupled Memory (TCM) section).
Therefore, it would have been obvious to combine Arm with Arimilli to obtain the invention as specified in the instant claim.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Arimilli in view of Castro et al., U.S. Patent Application 2023/0221771 (hereinafter referred to as Castro).
As per claim 19, Arimilli discloses “A system comprising: the data processing apparatus of claim 1, implemented in at least one packaged chip” (Fig. 1 and claim 2 memory controller and processing cores integrated in a same integrated circuit chip); “at least one system component” (Fig. 1 memory 22a).
Arimilli does not appear to explicitly disclose “a board, wherein the at least one packaged chip and the at least one system component are assembled on the board.”
However, assembling integrated circuits, processors, etc. on a printed circuit board is known in the art at the time of Applicant’s filing. For example, Castro discloses another computing system with processing logic accessing memory ([0067] memory 306 storing programs, modules, and data structures) including “a board, wherein the at least one packaged chip and the at least one system component are assembled on the board” (Fig. 7A main logic board 740).
Arimilli and Castro are analogous art because they are from the same field of endeavor, which is computing devices with processing logic and memory access.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Arimilli and Castro before him or her, to modify the teachings of Arimilli to include the teachings of Castro so that the data processing apparatus of claim 1 is implemented in at least one chip on a circuit board.
The motivation for doing so would have been to take advantage of the features of a printed circuit board, such as durability and copper traces that are cheaper than wiring.
Therefore, it would have been obvious to combine Castro with Arimilli to obtain the invention as specified in the instant claim.
As per claim 20, Arimilli does not appear to explicitly disclose “the system is assembled on a further board with at least one other product component.”
However, computing systems with multiple interconnected circuit boards are known in the art at the time of Applicant’s filing. For example, Castro discloses “the system is assembled on a further board with at least one other product component” (Fig. 7A and [0138] – [0140] main logic board and a plurality or secondary boards including daughter board 1004 and control board 734).
Arimilli and Castro are analogous art because they are from the same field of endeavor, which is computing devices with processing logic and memory access.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Arimilli and Castro before him or her, to modify the teachings of Arimilli to include the teachings of Castro so that the system is assembled on a further board with at least one other product component.
The motivation for doing so would have been to provide a modular approach, which can provide easier upgrading, flexible usage of space, and/or customization.
Therefore, it would have been obvious to combine Castro with Arimilli to obtain the invention as specified in the instant claim.
Allowable Subject Matter
Claims 4 – 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 6/25/2026 have been fully considered but they are not persuasive.
Applicant argues, on page 7 line 1 – page 8 line 3 that
Arimilli [0048] states the IMC 18 also determines the memory bank 56 in the attached system memory 22 to which the specified request address maps (and that Fig. 5A step 106 also shows this determining). Applicant argues that a determination is not the same as a prediction.
Applicant continues that Arimilli’s ‘speculative memory access’ does not disclose the claimed prediction circuitry because the speculation steps are determining whether to initiate a memory access in advance of receipt of a coherency message. Applicant states that this speculation “has nothing to do with memory targets. In fact, the target memory bank has already been determined in previous step 106 in Fig. 5A. Thus, 108-110 of Fig. 5A and paragraph [0048] do not disclose "prediction of one of the plurality of memory targets."
The examiner disagrees. Arimilli clearly discusses memory targets and speculation. This speculation has to do with memory access, therefore has to do with memory targets. This appears to be the disconnect between the Examiner’s reading of the claim language and Applicant’s reading of the claim language. Under the broadest reasonable interpretation of the claim, "perform a prediction of one of the plurality of memory targets to which the memory access is associated" is equivalent to any prediction involving a memory that can be targeted (not needing to be predicting which memory is targeted). While Arimilli does describe determining a memory bank to which an address maps, Arimilli also discloses performing a prediction/speculation. This prediction is of one of the memory targets and is associated with one of the memory targets. The examiner recommends amending the claim language to state “prediction circuitry configured to perform a prediction of which one of the plurality of memory targets targeting” or the like.
Applicant’s further arguments on pages 8 – 9 are answered with the same reasoning as above.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application 20200151100 and Patent 11243884 teach hashing the program counter to determine a predicted target memory location.
U.S. Patent Application 20170286119 and Patent 11709679 teach determining if a predicted memory address exists in a cache or in system memory.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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