DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6 December, 2024 and 28 October, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 11- 20 are objected to because of the following informalities:
In claim 11, line 2, “row of a memory cell” should read “row of memory cells”.
In claim 12, line 3, “an hardware” should read “hardware”.
In claim 20, lines 2-3, “row of a memory cell” should read “row of memory cells”.
Claims 13-19 are objected to because they depend from claim 12, and are therefore seen to contain the same deficiencies.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "calculating the minimum number" in line 1. There is insufficient antecedent basis for this limitation in the claim. No minimum number of processing elements is calculated in claim 1 on which claim 3 depends, but a minimum number is calculated in claim 2.
Allowable Subject Matter
Claims 1-2 and 6-10 are allowed.
Claim 1 includes the limitations a method for arranging a matrix in an analog processing element, comprising: determining a number of analog processing elements in which each of one or more matrices is to be arranged; generating sub-matrices by dividing each of the one or more matrices by the determined number of analog processing elements; and determining respective positions of the analog processing elements at which the sub-matrices resulting from division are to be arranged. Particularly, the limitations of determining a number of analog processing elements in which each of one or more matrices is to be arranged; generating sub-matrices by dividing each of the one or more matrices by the determined number of analog processing elements differentiate the claim from prior art including Kodavanji et al (U.S. Patent Pub. No. 2021/0334335), hereinafter referred to as Kodavanji, which discloses dividing matrices for processing in an array of analog processing elements, and determining positions of the elements. However, Kodavanji does not teach dividing matrices by a separately determined number of analog processing elements. Instead, as shown in Fig. 3A (step 304), matrices are divided by the shape of analog processing elements before a number of utilized processing elements is determined. Other fields of invention may disclose the claimed step, but no prior art was found which a person of ordinary skill in the art would reasonably decide to combine with Kodavanji. No prior art was found to teach the entirety of the limitations of claim 1, alone or in combination. As such, claim 1 is found allowable.
Claims 2 and 6 are allowable by virtue of dependence on allowable claim 1.
Claim 7 includes the limitations a method for performing a write operation on memory cells in consideration of endurance, comprising: as an update of matrix data stored in an analog processing element occurs, determining a position of a next reference memory cell among internal memory cells of the analog processing element; and writing updated matrix data to memory cells selected based on the determined position of the next reference memory cell. Particularly, the limitation of performing the method as an update of matrix data stored in an analog processing element occurs differentiates the claim from prior art including Ambrogio et al (U.S. Patent Pub. No. 2023/0306252), hereinafter referred to as Ambrogio, which discloses modifying weight values in a resistive processing unit array by selecting a row and updating the cells in the row (¶ 0129 and following discussion of “calibration” steps). However, Ambrogio does not explicitly disclose performing this operation as an update of matrix data stored in an analog processing element occurs or determining an update by selecting a reference cell. No prior art was found to teach the entirety of the limitations of claim 7, alone or in combination. As such, claim 7 is found allowable.
Claims 8-10 are found allowable by virtue of dependence on allowable claim 7.
Additionally, in the interest of compact prosecution:
Claim 11 would be allowable if the objection under informality is overcome, by virtue of dependence on allowable claim 7.
Claims 12-20 would also be allowable if the objection under informality is overcome. Claim 12 includes the limitations an apparatus for managing memory cell endurance of an analog computing system, comprising: an hardware based on analog compute-in-memory including multiple analog processing elements; and an endurance manager configured to manage the hardware based on analog compute-in-memory, wherein the endurance manager is configured to: determine analog processing elements in which matrix data is to be arranged and write matrix data to the determined analog processing elements, and wherein as an update for matrix data stored in the analog processing elements occurs, write updated matrix data to memory cells selected based on a number of write operations on internal memory cells of each of the analog processing elements. Particularly, the limitation of an endurance manager configured to manage the hardware based on analog compute-in-memory was not found to be sufficiently taught by any prior art. Therefore, no prior art was found to teach the entirety of the limitations of claim 12, alone or in combination.
Claims 13-20 would be found allowable by virtue of dependence on allowable claim 12, if objections under informality are overcome.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
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/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139