DETAILED ACTION
Claims 1-20 are currently pending in the application and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 12/06/2024 and 08/14/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 8-13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 9:
This claim recites the limitations “A pseudo-launch-off-shift (PLOS) circuit comprising: the scan flip-flop device according to claim 1; and a PLOS synchronizer…”. This PLOS circuit is represented by Fig. 5 of the current application. This claim is rejected for failing to comply with the enablement requirement because the scan flip-flop device of claim 1 (Fig. 3a, 300a and b, same flip-flop output connected to both first and second logic gates) is not represented by Fig. 5 nor enabled in the specification. The scan flip-flop device 200 shown is the one shown in Fig. 5 (two different flip-flop outputs connected to each logic gate respectively) with PLOS circuit 501 are disclosed in the specification. It is noted that the scan flip-flop device 200 inFig. 2 is not claimed at all in the current set of claims. Clarification and correction are required.
Claim 8:
This claim is rejected for the same reason as claim 9 because the integrated synchronizer is not part of the flip-flop of claims 1 or 5.
Claim 11:
This claim is rejected for the same reasons as claim 9 because claim 5 also uses the scan flip-flop device of claim 1.
Claims 10, 12 and 13:
These claims are also rejected because they depend on a base rejected claim and have the same problems of failing to comply with the enablement requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1:
The first logic gate and the second logic gate are both defined as being "configured to output a first/second output based on a comparison of the flip-flop signal and a first/second test signal"; therefore, both logic gates can be the same type of logic gate, which is not according to the invention (see Fig. 1, see claims 2 and 3) and which leads to a clarity objection; both logic gates are defined as "doing" a comparison, which is not according to the functions carried out by an OR gate and an AND gate and which leads to a clarity objection; neither an OR gate or an AND gate perform a pure comparison of two signals (the AND operation outputs a logic zero, instead of a logic one, when both inputs are equal to zero; therefore, the AND gate does not perform a pure comparison), thus, the present formulation enlarges the scope of the invention to implementations not defined by the description and drawings (Fig. 1), which leads to a clarity objection. This renders this claim indefinite. Clarification and correction are required.
Claims 5 and 14:
These claims exhibit similar ambiguities as claim 1 and are rejected as such.
Claims 2-13 and 15-20:
These claims are also rejected because they depend on a base rejected claim and have the same problems of indefiniteness.
Claim 12:
This claim recites the limitation "the third logic gate" in line 2. There is insufficient antecedent basis for this limitation in the claim.
This claim recites the limitation "the second scan flip-flop device" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim.
This claim recites the limitation "the fourth logic gate" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Examiner’s Note
It appears that the scan flip-flop device of Figs. 1 (200) and 5 (200) are different than what is claimed. The claimed scan flip-flop device appears to be that of Figs. 3a and 3b (300). Therefore, for purpose of examination, the scan flip-flop device 200 will not be considered part of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Goh (US-20150015317), hereinafter Goh.
Claim 1:
Goh teaches a scan flip-flop device (Fig. 1A, flip-flop cell 10) comprising:
a multiplexer (Fig. 1A, multiplexer 14) configured to receive a data signal (Fig. 1A, data input D 20), a scan input signal (Fig. 1A, test input TI 22) and a scan enable signal (Fig. 1A, scan enable input TE 24), the multiplexer being configured to selectively output either the data signal or the scan input signal based upon the scan enable signal (The multiplexed output of multiplexer 14 (i.e., either D 20 or TI 22, depending on which mode is currently being signaled) is provided to D(int) 32 of flip-flop 12, ¶ [0028]);
a flip-flop (Fig. 1A, flip-flop 12) configured to receive the output of the multiplexer (D(int) 32) and a clock signal (clock input CP 26), the flip-flop being configured to output a flip-flop signal based on a state of the flip-flop (¶ [0027]);
a first logic gate (Fig. 1A, NOR gate 16) configured to receive the flip-flop signal (Fig. 1A, Q(int) 36) and a first test signal (Fig. 1A, Signal 42), the first logic gate being configured to output a first output (Q 28) based on a comparison of the flip-flop signal and the first test signal (see that the gate 16 receives the output of the flip-flop, the signal TE and also an additional input signal 42); and
a second logic gate (Fig. 1A, NAND gate 18, INV 40) configured to receive the flip-flop signal (Fig. 1A, Q(int) 36) and a second test signal (Fig. 1A, Signal 41), the second logic gate being configured to output a second output (TQ 30) based on a comparison of the flip-flop signal and the second test signal (see that the gate 18 receives the output of the flipflop, the signal TE and also an additional input signal 41),
wherein the scan enable signal, first test signal and second test signal are independently configurable (the signals TE, 41, and 42 are independently configurable, see ¶¶ [0028] and [0030]).
Goh does not explicitly teach that signals 41 and 42 and test signals. However, Goh does teach spare inputs 41 and 42--which are supplied by gate inputs D and C, respectively--receive external signals from circuitry of an IC outside of flip-flop cell 12. (¶ [0028]). It would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to use Goh’s spare inputs 41 and 42 as additional test signals. The artisan would be motivated to do so because it would enable Goh to have more control of the testing modes of the scan flip-flop circuit.
Claim 2:
Goh teaches the first logic gate is an OR gate (Fig. 1A, NOR gate 16).
Claim 3:
Goh teaches the second logic gate is an AND gate (Fig. 1A, NAND gate 18, INV 40).
Claim 4:
Goh teaches the flip-flop (Fig. 1A, flip-flop 12) comprises a reset pin (Fig. 1A, 38) configured to reset the state of the flip-flop in response to a reset signal (Fig. 1A, reset input 38 provides a way to clear Q(int) 36 from an outside source).
Claim 5:
Goh teaches a multi-bit scan flip-flop device comprising the scan flip-flop device according to claim 1 and further comprising a second scan flip-flop device comprising: a second multiplexer configured to receive a second data signal, a second scan input signal and the second scan enable signal, the second multiplexer being configured to selectively output either the second data signal or the second scan input signal based upon the second scan enable signal; a second flip-flop configured to receive the output of the second multiplexer and a second clock signal, the second flip-flop being configured to output a second flip-flop signal based on a state of the second flip-flop; a third logic gate configured to receive the second flip-flop signal and a third test signal, the third logic gate being configured to output a third output based on a comparison of the second flip-flop signal and the third test signal; and a fourth logic gate configured to receive the second flip-flop signal and a fourth test signal, the fourth logic gate being configured to output a fourth output based on a comparison of the second flip-flop signal and the fourth test signal, wherein the first output of the scan flip-flop device and the second data signal received by the second scan flip-flop device are coupled to combinational logic such that the scan flip-flop device outputs to the combinational logic and the second scan flip-flop device receives an input from the combinational logic when the multi-bit scan flip-flop device is operated in a functional or scan capture mode. (Fig. 2 and discussion therein. Fig. 2 represents multiple flip-flop cells connected in series to each other in a scan chain configuration. Design 48 includes three flip-flop cells 13a, 13b, and 13c connected to logic 56).
Claim 6:
Goh teaches each of the scan flip-flop devices (Fig. 2, flip-flop cells 13a, 13b, and 13c) are provided with an individual scan input signal (Fig. 2, test input TI (22a, 22b, 22c)).
Claim 7:
Goh teaches the second output of the scan flip-flop device (Fig. 2, TQ 30a) is provided as the second scan input signal received by the second scan flip-flop device (Fig. 2, test input TI 22b).
Claim 14:
Goh teaches a method of operating a circuit comprising a scan flip-flop device, the scan flip-flop device comprising: a multiplexer configured to receive a data signal, a scan input signal and a scan enable signal, the multiplexer being configured to selectively output either the data signal or the scan input signal based upon the scan enable signal; a flip-flop configured to receive the output of the multiplexer and a clock signal, the flip-flop being configured to output a flip-flop signal based on a state of the flip-flop; a first logic gate configured to receive the flip-flop signal and a first test signal, the first logic gate being configured to output a first output based on a comparison of the flip-flop signal and the first test signal; and a second logic gate configured to receive the flip-flop signal and a second test signal, the second logic gate being configured to output a second output based on a comparison of the flip-flop signal and the second test signal, the method comprising: individually configuring each of the scan enable signal, the first test signal and the second test signal such that a desired operating condition is applied to the scan flip-flop device; and analysing at least one of the first output and the second output to determine an operational status of the scan flip-flop device in the same way as the rejection of claim 1.
Claim 15:
Goh teaches the desired operating condition corresponds to one of: a functional mode (capture mode, ¶ [0003] and throughout) wherein the first output (Fig. 2, standard function flip-flop cell output Q 28a) is provided to combinational logic (Fig. 2, logic 56).
Claim 16:
Goh teaches individually configuring each of the scan enable signal, the first test signal and the second test signal comprises using Automatic Test Pattern Generation (ATPG) software to produce desired test bits. (The disclosed shift and capture modes imply that that an ATPG system configures the scan enable signal, the first test signal and the second test signal and produces desired test bits.)
Claim 17:
the circuit comprises at least a first scan flip-flop device and a second scan flip-flop device.
Claim 18:
Goh teaches the first logic gate is an OR gate (Fig. 1A, NOR gate 16).
Claim 19:
Goh teaches the second logic gate is an AND gate (Fig. 1A, NAND gate 18, INV 40).
Claim 20:
Goh teaches the flip-flop (Fig. 1A, flip-flop 12) comprises a reset pin (Fig. 1A, 38) configured to reset the state of the flip-flop in response to a reset signal (Fig. 1A, reset input 38 provides a way to clear Q(int) 36 from an outside source).
Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Goh (US-20150015317), hereinafter Goh, in view of Jajodia et al. (US-9188640), hereinafter Jajodia.
Claim 8:
Goh does not explicitly teach the scan enable signals provided to the scan flip-flop device and second scan flip-flop device are synchronised using an integrated synchroniser. However, Jajodia teaches in an analogous art the pipeline flip-flop 102 has a data input terminal that receives a scan enable signal (SEN) from a scan enable port (SEN_port), which is a tester pad, a clock input terminal that receives a clock signal (CLK), and a data output terminal that generates a scan enable pipeline signal (SEN_pipeline). A first input terminal of the OR gate 106 is connected to the data input terminal of the pipeline flip-flop 102 for receiving the scan enable signal (SEN) and a second input terminal of the OR gate 106 is connected to the data output terminal of the pipeline flip-flop 102 for receiving the scan enable pipeline signal (SEN_pipeline). The OR gate 106 outputs a local scan enable signal (SEN_local). (Fig. 1A and discussion therein. Also, see Fig. 1B and discussion therein; the scan flip-flop 104 receives the local scan enable signal (SEN_local) that is synchronized with the launch clock pulse 110). It would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to use Jajodia’s the pipeline flip-flop 102 and OR gate 106, as connected, to synchronize the scan enable signal of Goh’s flip-flop cell 10. The artisan would be motivated to do so because it would provide Goh with a Launch On Shift (LOS) circuit, which would enable Goh to switch the scan enable signal (TE 24) at speed.
Claim 9:
Goh teaches the scan flip-flop device according to claim 1 (see the rejection of claim 1).
Goh does not explicitly teach a pseudo-launch-off-shift (PLOS) circuit comprising: a PLOS synchroniser configured to provide a synchronised scan enable signal to the scan flip-flop device such that the selective output of multiplexer is synchronised with the clock signal. However, Jajodia teaches in an analogous art the pipeline flip-flop 102 has a data input terminal that receives a scan enable signal (SEN) from a scan enable port (SEN_port), which is a tester pad, a clock input terminal that receives a clock signal (CLK), and a data output terminal that generates a scan enable pipeline signal (SEN_pipeline). A first input terminal of the OR gate 106 is connected to the data input terminal of the pipeline flip-flop 102 for receiving the scan enable signal (SEN) and a second input terminal of the OR gate 106 is connected to the data output terminal of the pipeline flip-flop 102 for receiving the scan enable pipeline signal (SEN_pipeline). The OR gate 106 outputs a local scan enable signal (SEN_local). (Fig. 1A and discussion therein. Also, see Fig. 1B and discussion therein; the scan flip-flop 104 receives the local scan enable signal (SEN_local) that is synchronized with the launch clock pulse 110). It would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to use Jajodia’s the pipeline flip-flop 102 and OR gate 106, as connected, to synchronize the scan enable signal of Goh’s flip-flop cell 10. The artisan would be motivated to do so because it would provide Goh with a Launch On Shift (LOS) circuit, which would enable Goh to switch the scan enable signal (TE 24) at speed.
Claim 10:
Goh teaches the first logic gate is an OR gate (Fig. 1A, NOR gate 16) and the second logic gate is an AND gate (Fig. 1A, NAND gate 18, INV 40).
Claim 11:
Goh teaches the multi-bit scan flip-flop device according to claim 5 (see the rejection of claim 5).
Goh does not explicitly teach A multi-bit pseudo-launch-off-shift (PLOS) circuit comprising: a PLOS synchroniser configured to provide a synchronised scan enable signal to the scan flip-flop device of the multi-bit scan flip-flop device such that the selective output of multiplexer is synchronised with the clock signal. However, Jajodia teaches in an analogous art the pipeline flip-flop 102 has a data input terminal that receives a scan enable signal (SEN) from a scan enable port (SEN_port), which is a tester pad, a clock input terminal that receives a clock signal (CLK), and a data output terminal that generates a scan enable pipeline signal (SEN_pipeline). A first input terminal of the OR gate 106 is connected to the data input terminal of the pipeline flip-flop 102 for receiving the scan enable signal (SEN) and a second input terminal of the OR gate 106 is connected to the data output terminal of the pipeline flip-flop 102 for receiving the scan enable pipeline signal (SEN_pipeline). The OR gate 106 outputs a local scan enable signal (SEN_local). (Fig. 1A and discussion therein. Also, see Fig. 1B and discussion therein; the scan flip-flop 104 receives the local scan enable signal (SEN_local) that is synchronized with the launch clock pulse 110). It would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to use Jajodia’s the pipeline flip-flop 102 and OR gate 106, as connected, to synchronize the scan enable signal of Goh’s flip-flop cell 10. The artisan would be motivated to do so because it would provide Goh with a Launch On Shift (LOS) circuit, which would enable Goh to switch the scan enable signal (TE 24) at speed.
Claim 12:
Goh teaches the each of the first logic gate of the scan flip-flop device and the third logic gate of the second scan flip-flop devices is an OR gate (Fig. 1A, NOR gate 16) and each of the second logic gate of the scan flip-flop device and the fourth logic gate of the second scan flip-flop device is an AND gate (Fig. 1A, NAND gate 18, INV 40).
Claim 13:
Goh does not explicitly teach the PLOS synchroniser is further configured to provide the synchronised scan enable signal to the second scan flip-flop device of the multi-bit scan flip-flop device. However, Jajodia teaches in an analogous art the pipeline flip-flop 102 has a data input terminal that receives a scan enable signal (SEN) from a scan enable port (SEN_port), which is a tester pad, a clock input terminal that receives a clock signal (CLK), and a data output terminal that generates a scan enable pipeline signal (SEN_pipeline). A first input terminal of the OR gate 106 is connected to the data input terminal of the pipeline flip-flop 102 for receiving the scan enable signal (SEN) and a second input terminal of the OR gate 106 is connected to the data output terminal of the pipeline flip-flop 102 for receiving the scan enable pipeline signal (SEN_pipeline). The OR gate 106 outputs a local scan enable signal (SEN_local). (Fig. 1A and discussion therein. Also, see Fig. 1B and discussion therein; the scan flip-flop 104 receives the local scan enable signal (SEN_local) that is synchronized with the launch clock pulse 110). It would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to use Jajodia’s the pipeline flip-flop 102 and OR gate 106, as connected, to synchronize the scan enable signal of Goh’s flip-flop cell 10. The artisan would be motivated to do so because it would provide Goh with a Launch On Shift (LOS) circuit, which would enable Goh to switch the scan enable signal (TE 24) at speed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Goh (US-20150039956) teaches a new flip-flop cell that is more efficient in scan chain configuration includes a multiplexer, storage element (e.g., a flip-flop), an inverter, and multiple logic gates. The flip-flop cell is configured to receive both a test signal and a data input signal and select one of the two to pass to the storage element based on a scan enable signal that indicates either a capture mode or a scan shift mode. In capture mode, the data input signal is passed to the storage element, and the internal outputs of the flip-flop are supplied to the logic gates. Based on the internal outputs and scan enable signal, the logic gates disable either one of two outputs of the flip-flop cell. In capture mode, a test flip-flop cell output is disabled. In scan shift mode, a standard function flip-flop cell output is disabled. (Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN J TABONE JR whose telephone number is (571)272-3827. The examiner can normally be reached M-F 9 AM to 7 PM EST.
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/JOHN J TABONE JR/Primary Examiner, Art Unit 2111 03/07/2026