DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Information Disclosure Statement
An information disclosure statement (IDS) was submitted on 06 December 2024 and 09 April 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Madan (US 20230205706 A1) in view of Seo (US 20210110876 A1).
Referring to claims 1, 12, 13, and 20, taking claim 13 as exemplary, Madan teaches
A memory device for performing a processing in-memory (PIM) computation, the memory device ([Madan abstract, 0030-0031, Fig. 1B] An approach is provided for managing PIM commands and non-PIM commands at a memory controller. A memory controller enqueues PIM commands and non-PIM commands and selects the next command to process based upon various selection criteria.) comprising: a memory module comprising at least one of a plurality of PIM computation banks; ([Madan 0037, Fig. 1B] FIG. 1B is a block diagram that depicts a computing arrangement 120. The computing arrangement 120 includes a memory controller 130 and a memory module 140.) and a processor configured to control the memory module, ([Madan 0037, 0040-0042, Fig. 1C] The computing arrangement 120 is implemented in any type of computing device including, for example, processors and a System on a Chip (SoC). The memory controller 130 and the memory module 140 are communicatively coupled via a command bus 150 and a data bus 160. The memory controller 130 manages the flow of data going to and coming from the memory module 140 and is implemented as a stand-alone element, for example on a separate die from a microprocessor, implemented separate from but on the same die as a microprocessor, or integrated into a microprocessor as an integrated memory controller.) wherein the processor is configured to: monitor, based on a first command and an address, an open state of a PIM row of one of the PIM computation banks in the memory module ([Madan abstract, 0031, 0045, 0051, Fig. 2A, 2E] The page table tracks the status of memory elements as of the most recent memory command that was issued. The page table includes an “All Bank” entry that indicates the status of banks after processing the most recent PIM command. For example, the All Banks entry indicates whether all the banks have a row open and if so, specifies the open row for all the banks. , the selection criteria include the presence of a specific marker. For example, a switch is made between processing PIM commands and non-PIM commands based upon the presence in the command queue 170 of a command with a specified marker. The marker indicates, for example, the endpoint of a group of PIM or non-PIM commands and may be specified by software, e.g., added by a software developer, or inserted by the memory controller 130 when a memory address dependency) generate a PIM computation command signal when it is determined as a result of the monitor that a PIM row of each of the PIM computation banks is in the open state; ([Madan 0057-0060, Figs. 2A-2I] Metadata for PIM commands is used by the memory controller 130 or forwarded to the PIM device while the PIM commands are issued. Alternatively, if sufficient signaling is available, then PIM command metadata may be provided to the memory controller 130 via the signaling. Example Page Table with “all Banks” Status. The first entry in the page table 200 is a novel All Banks entry that specifies whether the banks currently have a row open as a result of processing the most recent PIM command and if so, which row. For example, suppose that the memory controller 130 issues a broadcast PIM command that specifies Row 6, i.e., all of the banks are to perform a particular memory operation, which may include a local computation, at Row 6 and a particular column. The processing logic 174 updates the All Banks entry with a status value of “Valid,” a row open value of “Y” and a row ID of 6.) and control the memory module so that a second command received while the PIM computation command signal is generated is processed using a PIM computation ([Madan 0002, 0060, Figs. 2A-2I] The first entry in the page table 200 is a novel All Banks entry that specifies whether the banks currently have a row open as a result of processing the most recent PIM command and if so, which row. For example, suppose that the memory controller 130 issues a broadcast PIM command that specifies Row 6, i.e., all of the banks are to perform a particular memory operation, which may include a local computation, at Row 6 and a particular column. The processing logic 174 updates the All Banks entry with a status value of “Valid,” a row open value of “Y” and a row ID of 6.).
Madan does not explicitly disclose corresponding to the address. Madan does disclose processing PIM commands and non-PIM commands based upon the presence in the command queue 170 of a command with a specified marker inserted by the memory controller 130 when a memory address dependency ([Madan 0051]).
Seo teaches corresponding to the address ([Seo 0055, 0058-0059, 0076] A row decoder 320 and a column decoder 330 may be provided to select a specific memory cell included in the DRAM cell array 310 of the memory bank 30. When the row decoder 320 selects a row direction word line based on a received row address, and the column decoder 330 selects a column direction bit line based on a received column address, a memory cell corresponding to the selected row direction word line and column direction bit line may be selected. The PIM operator 40 may include a command generator unit 47 that receives a DRAM command and an address transmitted from a control circuit (e.g., the control circuits Control circuit 0 or Control circuit 1 of FIG. 2) and then converts the command into more detailed subcommands.).
Madan and Seo are analogous art because they are from the same field of endeavor in memory systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Madan and Seo before him or her to modify the computing arrangement of Madan to include the PIM operation and command address handling of Seo, thereafter the computing arrangement is connected to PIM operation and command address handling. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the computing arrangement to incorporate addresses into its PIM command metadata to allow for additional command handling robustness. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Madan with Seo to obtain the invention as specified in the instant application claims.
Referring to claims 2 and 14, taking claim 14 as exemplary, Madan in view of Seo teaches
The memory device of claim 13, wherein, in the monitor of the open state, the processor is configured to: monitor the open state of the PIM row of the PIM computation bank in the memory module corresponding to the address when a received command is an activation command and the address is within a PIM operator address range ([Madan 0045, 0062-0063 Figs. 2A-2I] The page table 178 includes data that specifies the current state of one or more memory elements within a memory module and is used by the processing logic 174 to configure memory elements to process memory commands. For example, the page table 178 includes an entry for each bank of the memory module 140, where each entry specifies whether the corresponding bank currently has an open (activated) row from the most recent non-PIM command directed to that bank, if any, and if so, which row is currently open, e.g., via a row ID. When a row is opened or closed (deactivated) the processing logic 174 updates the corresponding entry in the page table 178. According to an implementation, the page table 178 also includes an All banks entry that specifies whether the banks have a row open from the most recent PIM command and if so, which row. The use of the All banks entry by the memory controller 130 to manage PIM and non-PIM commands is described in more detail hereinafter. In the present example, the processing logic 174 issues an activate command to open Row 4 in Bank 3. Control then proceeds to step 212 and the processing logic 174 updates the page table to record the change in status for Bank 3, namely, by changing the Status field from “Invalid” to “Valid,” changing the Row Open field from “N” to “Y” and the Row ID field from “n/a” to “4.” The processing logic 212 then issues the command.).
Referring to claims 3 and 15, taking claim 15 as exemplary, Madan in view of Seo teaches
The memory device of claim 13, wherein, in the monitor of the open state, the processor is configured to: update a count value stored in a register in accordance with the PIM computation bank ([Madan 0002, 0039, 0042, 0050] an example PIM configuration includes vector compute elements and local registers. The vector compute elements and the local registers allow a memory module to perform some computations locally, such as arithmetic computations. he PIM execution units include processing logic and storage, such as local registers, for processing PIM commands, e.g., to perform logical operations, arithmetic operations, etc. According to another implementation, the selection criteria include a number of pending commands threshold. In this implementation, the first stage picker 180 switches between processing PIM commands and non-PIM commands when the number of pending PIM commands or non-PIM commands, respectively, reaches a threshold. The same pending command threshold is used for both PIM commands and non-PIM commands, or separate thresholds are used) for every clock cycle; and determine that the PIM row of the PIM computation bank in the memory module corresponding to the address is in an open state, based on the count value ([Seo 0007-0009, 0078-0079] The control circuit may include a request counter to count memory requests for each of the plurality of memory banks according to a predetermined period, and the control circuit may, based on numbers counted by the request counter, perform scheduling on the processing of the memory requests and the PIM operation. A command “p-PRE” is a command issued from the memory controller and may indicate a command for notifying the pause of the PIM operation by the target bank together with the precharge. The timing at which the corresponding operation is executed after the issuance of the command “p-PRE” needs to be at least tRC. In the present example, the timing of “p-PRE” is set to tRC+tRP as an example for guaranteeing the performance of the PIM operation most. tRC is Row Cycle Time that represents the minimum time interval between successive activation ACTIVE (i.e. open) commands with respect to the same bank, and tRP is Row Precharge Time which is the number of clock cycles taken between the issuance of the precharge PRE command and the activation ACT command. In “p-PRE”, p may refer to a pause.).
Referring to claim 4, Madan in view of Seo teaches
The method of claim 3, further comprising setting the count value corresponding to a first PIM computation bank to a value indicating a time until a PIM row of the first PIM computation bank is opened after an activation command corresponding to an address of the first PIM computation bank is processed ([Madan 0030, 0048] An approach is provided for managing PIM commands and non-PIM commands at a memory controller. A memory controller enqueues PIM commands and non-PIM commands and selects the next command to process based upon various selection criteria. Examples of selection criteria include, without limitation, command allocation bandwidth, a number of pending commands, an amount of time or number of cycles since a most recent command was issued, a presence of a marker, or global age, etc.).
Referring to claims 5 and 16, taking claim 16 as exemplary, Madan in view of Seo teaches
The memory device of claim 13, wherein the processor is configured to: store a number of times that PIM computations need to be processed in the memory module, wherein the second command is processed using the PIM computation when the number of times is non-zero ([Madan 0030, 0050, Fig. 1A] According to another implementation, the selection criteria include a number of pending commands threshold. In this implementation, the first stage picker 180 switches between processing PIM commands and non-PIM commands when the number of pending PIM commands or non-PIM commands, respectively, reaches a threshold. The same pending command threshold is used for both PIM commands and non-PIM commands, or separate thresholds are used, depending upon a particular implementation, and thresholds may be specified either via configuration information of programmatically. For example, a programmer may specify a lower pending PIM command threshold for workloads that include large PIM code regions. According to another implementation, the selection criteria include a number of cycles or time since a particular type of command was issued. For example, the first stage picker 180 switches from processing PIM commands to processing non-PIM commands when a specified number of cycles or amount of time has elapsed since the last non-PIM command was processed, and vice versa. This is useful in situations to satisfy a quality of service requirement.).
Referring to claims 6 and 17, taking claim 17 as exemplary, Madan in view of Seo teaches
The memory device of claim 13, wherein the processor is configured to: stop generation of the PIM computation command signal based on whether a number of times a PIM computation is performed in the memory module reaches a threshold number ([Madan 0030, 0050, Fig. 1A] According to another implementation, the selection criteria include a number of pending commands threshold. In this implementation, the first stage picker 180 switches between processing PIM commands and non-PIM commands when the number of pending PIM commands or non-PIM commands, respectively, reaches a threshold. The same pending command threshold is used for both PIM commands and non-PIM commands, or separate thresholds are used, depending upon a particular implementation, and thresholds may be specified either via configuration information of programmatically. For example, a programmer may specify a lower pending PIM command threshold for workloads that include large PIM code regions. According to another implementation, the selection criteria include a number of cycles or time since a particular type of command was issued. For example, the first stage picker 180 switches from processing PIM commands to processing non-PIM commands when a specified number of cycles or amount of time has elapsed since the last non-PIM command was processed, and vice versa. This is useful in situations to satisfy a quality of service requirement.).
Referring to claims 7 and 18, taking claim 18 as exemplary, Madan in view of Seo teaches
The memory device of claim 13, wherein, in the control of the memory module, the processor is configured to: control the memory module so that a read command or a write command received while the PIM computation command signal is generated is processed using a PIM computation ([Madan 0051-0052] According to another implementation, the selection criteria include the presence of a specific marker. For example, a switch is made between processing PIM commands and non-PIM commands based upon the presence in the command queue 170 of a command with a specified marker. The marker indicates, for example, the endpoint of a group of PIM or non-PIM commands and may be specified by software, e.g., added by a software developer, or inserted by the memory controller 130 when a memory address dependency, e.g., Write-After-Read (WAR), Write-After-Write (WAW), Read-After-Write (RAW), etc., is detected between a PIM command and a non-PIM command, even from different processor threads.).
Referring to claims 8, 9, 10, and 19, taking claim 19 as exemplary, Madan in view of Seo teaches
The memory device of claim 13, wherein the processor is configured to: stop generation of the PIM computation command signal based on receipt of a precharge command; ([Madan 0063, 0067] If, in step 204, Row 4 of Bank 3 was currently open, then this represents a page hit and control proceeds to step 212. If, however, in step 204, a different row of Bank 3 is currently open, then this is a page conflict and in step 208, the processing logic 174 closes the currently open row, for example by issuing a precharge command to Bank 3. In step 210, the processing logic 174 then opens the row needed to process the selected command, which in the present example is Row 3, by issuing an activate command to open Row 4 in Bank 3. Control then proceeds to step 212 as previously described.) initialize, based on receipt of the precharge command, a count value stored in a register in accordance with a PIM computation bank of an address corresponding to the precharge command; ([Madan 0063, 0067] For example, the processing logic 174 accomplishes this by issuing an all banks precharge command or a separate precharge command to each bank with an open row. The decision of whether to use an all banks precharge command or a separate precharge command to each bank with an open row may be made based upon the costs of issuing an all banks precharge command versus separate precharge commands to banks with open rows. Example costs include computational costs, power consumption, etc. For example, in situations where only a small number of banks have open rows and it is less expensive to issue separate precharge commands to those banks, then separate precharge commands are used instead of an all banks precharge command. If however, a large number of banks have open rows and it is less computationally expensive to issue a single all banks precharge command, then the all banks precharge command is issued instead of a separate precharge command to each bank.) and control the memory module so that a command received after stopping generation of the PIM computation command signal is processed using a normal memory operation ([Seo 0078-0079] A command “p-PRE” is a command issued from the memory controller and may indicate a command for notifying the pause of the PIM operation by the target bank together with the precharge. The timing at which the corresponding operation is executed after the issuance of the command “p-PRE” needs to be at least tRC. In the present example, the timing of “p-PRE” is set to tRC+tRP as an example for guaranteeing the performance of the PIM operation most. tRC is Row Cycle Time that represents the minimum time interval between successive activation ACTIVE commands with respect to the same bank, and tRP is Row Precharge Time which is the number of clock cycles taken between the issuance of the precharge PRE command and the activation ACT command. In “p-PRE”, p may refer to a pause.).
Conclusion
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132