CTNF 18/971,767 CTNF 79294 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION 2. This action is in response to the Preliminary Amendment filed May 28, 2025. 3. Claims 1-20 have been cancelled and new claims 21-40 have been added. 4. Claims 21-40 have been examined and are pending with this action. 5. The Information Disclosure Statement filed August 13, 2025 has been considered. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA 6. Claim(s ) 21-23, 26-35, and 38-40 are re jected under 35 U.S.C. 102(a) (1) and 102(a)(2) a s being an ticipated by Li tichever et al. (US 2018/0225230 A1). IN DEPENDENT: As per claim 21 , Litichever teaches a communication system, comprising: a first network device (see Litichever, [ 0140 ]: “A bus may support master/slave configuration, where one connected node is typically a bus master (e.g., the processor or the processor-side), and other nodes (or node) are bussed slaves.”; and [ 0149 ]: “Due to its shared bus topology, access to the older PCI bus is arbitrated (in the case of multiple masters), and limited to 1 master at a time, in a single direction.”) ; and N second network devices, wherein the first network device is a master device in the communication system, the N second network devices are slave devices in the communication system, and N is a positive integer (see Litichever, [ 0140 ]: “A bus may support master/slave configuration, where one connected node is typically a bus master (e.g., the processor or the processor-side), and other nodes (or node) are bussed slaves.”; and [ 0170 ]: “where master node is a node that generates the clock and initiates communication with slaves, and a slave node is a node that receives the clock and responds when addressed by the master.”) ; wherein the first network device is configured to adjust at least one of a bus scale, a channel capacity, or a power state, wherein the bus scale comprises at least one of a quantity of devices accessing a bus or a link length, the channel capacity comprises a bandwidth, and the power state comprises at least one of sequential power-on, power-on of a new node, or power-off of a faulty node (see Litichever, [ 0140 ]: “A bus may be defined to carry a power signal, either in separate dedicated cable (using separate and dedicated connectors), or commonly over the same cable carrying the digital data (using the same connector)... A slave may not connect or transmit to the bus until given permission by the bus master. A bus timing, strobing, synchronization, or clocking information may be carried as a separate signal (e.g., clock signal) over a dedicated channel, such as separate and dedicated wired in a cable, or alternatively may use embedded clocking (a.k.a. self-clocking), where the timing information is encoded with the data s”; and [ 0149 ]: “PCI slots and PCIe slots are not interchangeable. The PCIe link between 2 devices can consist of anywhere from 1 to 32 lanes. In a multi-lane link, the packet data is striped across lanes, and peak data-throughput scales with the overall link width. The lane count is automatically negotiated during device initialization, and can be restricted by either endpoint. For example, a single-lane PCIe (x1) card can be inserted into a multi-lane slot (x4, x8, etc.), and the initialization cycle auto-negotiates the highest mutually supported lane count. The link can dynamically down-configure the link to use fewer lanes, thus providing some measure of failure tolerance in the presence of bad or unreliable lanes.”) ; and wherein the first network device is configured to connect paths between the first network device and M second network devices in the N second network devices in a same time period, to enable the first network device to establish communication connections to the M second network devices, and reduce a quantity of devices accessing the bus in the same time period, wherein M is a positive integer less than N (see Litichever, [ 0139 ]: “Recent buses are self-repairable, where a spare connection (net) is provided which is used in the event of a malfunction in a connection. Some buses support hot-plugging (sometimes known as hot swapping), where a connection or a replacement can be made, without significant interruption to the system, or without the need to shut-off any power. A well-known example of this functionality is the Universal Serial Bus (USB) that allows users to add or remove peripheral components such as a mouse, keyboard, or printer”; [ 0149 ]: “Due to its shared bus topology, access to the older PCI bus is arbitrated (in the case of multiple masters), and limited to 1 master at a time, in a single direction.”; and [ 0170 ]: “The bus uses a clock (SCL) and data (SDA) lines with 7-bit addressing, and has two roles for nodes: master and slave, where master node is a node that generates the clock and initiates communication with slaves, and a slave node is a node that receives the clock and responds when addressed by the master.”) . As per claim 30 , Litichever teaches a method, applied to a network device, the method comprising: adjusting at least one of a bus scale, a channel capacity, or a power state, wherein the bus scale comprises at least one of a quantity of devices accessing a bus or a link length, the channel capacity comprises a bandwidth, and the power state comprises at least one of sequential power- on, power-on of a new node, or power-off of a faulty node (see claim 21 rejection above) . As per claim 40 , Litichever teaches a network device, comprising: at least one processor (see Litichever, [ 0007 ]: “The term “processor” is used herein to include, but not limited to, any integrated circuit or any other electronic device (or collection of electronic devices) capable of performing an operation on at least one instruction, including, without limitation, a microprocessor (μP), a microcontroller (μC), a Digital Signal Processor (DSP), or any combination thereof.”) ; and a memory storing computer instructions, wherein the at least one processor is configured to invoke the computer instructions, to enable the network device to (see Litichever, [ 0417 ]: “Any of the disclosed flow charts or methods, or any step thereof, may be implemented in the form of software stored on a memory or a computer-readable non-transitory information storage medium such as an optical or magnetic disk, a non-volatile memory (e.g., Flash or ROM), RAM, and other forms of volatile memory. The information storage medium may be an internal part of the computer, a removable external element coupled to the computer, or unit that is remotely accessible via a wired or wireless network.”) : adjust at least one of a bus scale, a channel capacity, or a power state, wherein the bus scale comprises at least one of a quantity of devices accessing a bus or a link length, the channel capacity comprises a bandwidth, and the power state comprises at least one of sequential power-on, power-on of a new node, or power-off of a faulty node (see claim 21 rejection above) . DEPENDENT: As per claims 22 and 33 , which respectively depend on claims 21 and 30, Litichever further teaches wherein the first network device is further configured to allocate a spectrum resource transmitted on the bus (see Litichever, [ 0004 ]: “An operating system commonly processes system data and user input, and responds by allocating and managing tasks and internal system resources, such as controlling and allocating memory, prioritizing system requests, controlling input and output devices, facilitating networking and managing files. Non-limiting examples of operating systems are Microsoft Windows, Mac OS X, and Linux.”) . As per claims 23 and 35 , which respectively depend on claims 21 and 30, Litichever further teaches wherein the first network device is further configured to: obtain a topology type of a target link, wherein the topology type comprises a point-to- point topology or a point-to-multipoint topology (see Litichever, [ 0131 ]: “The connection may further be wired in various topologies such as multi-drop (electrical parallel), point-to-point, or daisy-chain. A memory may be powered via a dedicated port or connector, or may be powered via a power signal carried over the bus, such as SATA or USB.”; and [ 0139 ]: “The bus topology may use point-to-point, multi-drop (electrical parallel) and daisy-chain, and may further be based on hubs or switches. A point-to-point bus may be full-duplex, providing simultaneous, two-way transmission (and sometimes independent) in both directions, or alternatively a bus may be half-duplex, where the transmission can be in either direction, but only in one direction at a time. Buses are further commonly characterized by their throughput (data bit-rate), signaling rate, medium length, connectors, and medium types, latency, scalability, quality-of-service, devices per connection or channel, and supported bus-width. A configuration of a bus for a specific environment may be automatic (hardware or software based, or both), or may involve user or installer activities such as software settings or jumpers.”) ; and determine a working mode of the first network device based on the topology type (see Litichever, [ 0170 ]: “The master is initially in master transmit mode by sending a start bit followed by the 7-bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write(0) to or read(1) from the slave. The I.sup.2C is described in NXP Semiconductors N.V. user manual document Number UM10204 Rev. 6 released 4 Apr. 2014, entitled: “UM10204-I.sup.2C-bus specification and user manual”, which is incorporated in its entirety for all purposes as if fully set forth herein”; and [ 0171 ]: “SPI devices communicate in full duplex mode using a master-slave architecture with a single master, where the master device originates the frame for reading and writing, and multiple slave devices are supported through selection with individual slave select (SS) lines.”) . As per claim 26 , which depends on claim 23, Litichever further teaches wherein the first network device is configured to determine the working mode of the first network device based on link transmission information and the topology type (see claims 23 and 35 rejections above) . As per claims 27 and 39 , which respectively depend on claims 26 and 38, Litichever further teaches wherein the link transmission information comprises a signal transmission feature, and the first network device is configured to: when the signal transmission feature indicates that a frequency band in which the first network device sends a first signal to at least one of the M second network devices overlaps a frequency band in which the first network device receives a second signal from the at least one of the M second network devices, and the topology type is the point-to-multipoint topology, determine that the working mode comprises that a first time period corresponding to the first signal does not intersect with a second time period corresponding to the second signal (see Litichever, [ 0099 ]: “A multitasking is a method where multiple tasks (also known as processes or programs) are performed during the same period of time—they are executed concurrently (in overlapping time periods, new tasks starting before others have ended) instead of sequentially (one completing before the next starts). The tasks share common processing resources, such as a CPU and main memory. Multitasking does not necessarily mean that multiple tasks are executing at exactly the same instant. In other words, multitasking does not imply parallelism, but it does mean that more than one task can be part-way through execution at the same time, and more than one task is advancing over a given period of time.”) . As per claim 28 , which depends on claim 26, Litichever further teaches wherein the link transmission information comprises a signal transmission feature, and the first network device is configured to: when the signal transmission feature indicates that a time period in which the first network device sends a first signal to at least one of the M second network devices overlaps a time period in which the first network device receives a second signal from the at least one of the M second network devices, and the topology type is the point-to-multipoint topology, determine that the working mode comprises that a first frequency band corresponding to the first signal does not intersect with a second frequency band corresponding to the second signal (see Litichever, [ 0099 ]: “A multitasking is a method where multiple tasks (also known as processes or programs) are performed during the same period of time—they are executed concurrently (in overlapping time periods, new tasks starting before others have ended) instead of sequentially (one completing before the next starts). The tasks share common processing resources, such as a CPU and main memory. Multitasking does not necessarily mean that multiple tasks are executing at exactly the same instant. In other words, multitasking does not imply parallelism, but it does mean that more than one task can be part-way through execution at the same time, and more than one task is advancing over a given period of time.”) . As per claims 29 and 38 , which respectively depend on claims 21 and 30, Litichever further teaches wherein the first network device is further configured to: obtain link transmission information (see Litichever, [ 0063 ]: “A bus driver services a bus controller, adapter, or bridge. Microsoft provides bus drivers for most common buses, such as Advanced configuration and Power Interface (ACPI), Peripheral Component Interconnect (PCI), PnPISA, SCSI, Universal Serial Bus (USB), and FireWire. A bus driver can service more than one bus if there is more than one bus of the same type on the machine. The ACPI bus driver interacts with the ACPI BIOS to enumerate the devices in the system and control their power use, the PCI bus driver (such as pci.sys) enumerates and configures devices connected via the PCI bus, the FireWire and the USB bus driver respectively enumerates and controls devices connected via the IEEE 1394 high speed bus and the USB.”; and [ 0138 ]: “A configuration of a bus for a specific environment may be automatic (hardware or software based, or both), or may involve user or installer activities such as software settings or jumpers. Recent buses are self-repairable, where a spare connection (net) is provided which is used in the event of a malfunction in a connection. Some buses support hot-plugging (sometimes known as hot swapping), where a connection or a replacement can be made, without significant interruption to the system, or without the need to shut-off any power. A well-known example of this functionality is the Universal Serial Bus (USB) that allows users to add or remove peripheral components such as a mouse, keyboard, or printer.”) ; and when the link transmission information indicates that the first network device corresponds to a low-latency target link, determine that a working mode of the first network device comprises disabling an error correction encoding and decoding function (see Litichever, [ 0137 ]: “Functions performed by the controller include Error correction (ECC),”; [ 0138 ]: “Recent buses are self-repairable, where a spare connection (net) is provided which is used in the event of a malfunction in a connection. Some buses support hot-plugging (sometimes known as hot swapping), where a connection or a replacement can be made, without significant interruption to the system, or without the need to shut-off any power. A well-known example of this functionality is the Universal Serial Bus (USB) that allows users to add or remove peripheral components such as a mouse, keyboard, or printer.”; [ 0170 ]: “he master is initially in master transmit mode by sending a start bit followed by the 7-bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write(0) to or read(1) from the slave. The I.sup.2C is described in NXP Semiconductors N.V. user manual document Number UM10204 Rev. 6 released 4 Apr. 2014, entitled: “UM10204-I.sup.2C-bus specification and user manual”, which is incorporated in its entirety for all purposes as if fully set forth herein”; and [ 0171 ]: “SPI devices communicate in full duplex mode using a master-slave architecture with a single master, where the master device originates the frame for reading and writing, and multiple slave devices are supported through selection with individual slave select (SS) lines.”) . As per claim 31 , which depends on claim 30, Litichever further teaches wherein adjusting the bus scale comprises: reducing a quantity of devices accessing the bus in a same time period (see Litichever, [ 0035 ]: “A number of processes being executed over a period instead of at the same time, is called concurrent execution. A multiprogramming or multitasking OS is a system executing many processes concurrently. A multiprogramming requires that the processor be allocated to each process for a period, and de-allocated at an appropriate moment. If the processor is de-allocated during the execution of a process, it must be done in such a way that it can be restarted later as easily as possible.”) . As per claim 32 , which depends on claim 31, Litichever further teaches wherein reducing the quantity of devices accessing the bus in the same time period comprises: connecting paths between the network device and a part of a group of devices in the same time period, to reduce the quantity of devices accessing the bus in the same time period (see claim 21 rejection above) . As per claim 34 , which depends on claim 33, Litichever further teaches wherein allocating the spectrum resource transmitted on the bus comprises: allocating different frequency band resources or a same frequency band resource to different services (see claims 27 and 39 above) . As per claim 38 , which depends on claim 35, Litichever teaches further comprising: obtaining link transmission information of the target link (see claims 23 and 35 above) ; and wherein determining the working mode of the network device based on the topology type comprises: determining the working mode of the network device based on the link transmission information and the topology type (see claims 23 and 35 above) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 7. Claim s 24 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Litichever et al. (US 2018/0225230 A1) in view of Pandey (US 2020/0072889 A1) . As per claims 24 and 36 , which respectively depend on claims 23 and 35, Litichever does not explicitly teach wherein the first network device is configured to: when it is determined that the topology type is the point-to-point topology, determine that the working mode comprises enabling an echo cancellation function. Pandey teaches when it is determined that the topology type is the point-to-point topology, determine that the working mode comprises enabling an echo cancellation function (see, [ 0070 ]: “FIG. 5 depicts an embodiment of a point-to-point communications network 500 that includes an expanded view of the transceivers 510 shown in FIG. 1 in which both transceivers include a voltage detection circuit 520… Although not shown in FIG. 5, the receivers 514 may each include a DSP that is configured to perform digital processing functions such as, for example, equalizer functions, echo cancellation functions, automatic gain control (AGC) functions, clock data recovery (CDR) functions, baseline wander (BLW) functions, and/or data recovery functions.”) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the system of Litichever in view of Pandey so that when it is determined that the topology type is the point-to-point topology, determine that the working mode comprises enabling an echo cancellation function. One would be motivated to do so because echo cancellation is well-known, routine, and conventional for improving clarity, efficiency, and stability by removing reflected versions of signals . 07-21-aia AIA 8. Claim s 25 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Litichever et al. (US 2018/0225230 A1) in view of Bunker (US 2001/0045914 A1) . As per claims 25 and 37 , which respectively depend on claims 23 and 35, Litichever does not explicitly teach teaches wherein the first network device is configured to: when the topology type is the point-to-multipoint topology, determine that the working mode comprises a modulation scheme of multi-carrier modulation; or when the topology type is the point-to-point topology, determine that the working mode comprises a modulation scheme of single-carrier modulation. Bunker teaches wherein the first network device is configured to: when the topology type is the point-to-multipoint topology, determine that the working mode comprises a modulation scheme of multi-carrier modulation; or when the topology type is the point-to-point topology, determine that the working mode comprises a modulation scheme of single-carrier modulation (see Bunker, [ 0034 ]: “Generally, wireless point-to-point and point-to-multipoint networks operate within a single frequency, or deploy a means of creating channels within the frequency utilizing expensive modulation technologies such as spread spectrum, frequency shift keying, multiple carrier, phase shift keying (PSK), amplitude shift keying (AKS) or other techniques known in the art.”) . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the system of Litichever in view of Bunker so that when the topology type is the point-to-multipoint topology, determine that the working mode comprises a modulation scheme of multi-carrier modulation. One would be motivated to do so because such an implementation would enable handling diversity naturally. Conclusion 9. For the reasons above, claims 21-40 have been rejected and remain pending. 10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL Y WON whose telephone number is (571)272-3993. The examiner can normally be reached on Wk.1: M-F: 8-5 PST & Wk.2: M-Th: 8-7 PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nicholas R Taylor can be reached on 571-272-3889. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michael Won/Primary Examiner, Art Unit 2443 Application/Control Number: 18/971,767 Page 2 Art Unit: 2443 Application/Control Number: 18/971,767 Page 3 Art Unit: 2443
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