DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on September 8, 2025 and November 25, 2025 were filed after the filing date of the application on December 6, 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings were received on December 6, 2024. These drawings are accepted.
Claim Objections
Claims 1, 16, and 19 are objected to because of the following informalities:
Claims 1 and 16 similarly recite, “…an interconnect to a host processor…a plurality of multiprocessors coupled via an interconnect…” where the claim does not distinguish between each interconnect. A possible amendment may be “…a first interconnect to a host processor…a plurality of multiprocessors coupled via a second interconnect…”
Claim 19 does not, but should, properly end with a period punctuation (.)
Appropriate correction is required.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,198,221. Although the claims at issue are not identical, they are not patentably distinct from each other as shown in the tables below.
Present Application #18/971,949
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U.S. Patent #12,198,221
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Present Application #18/971,949
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U.S. Patent #12,198,221
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Present Application #18/971,949 Claim 1
U.S. Patent #12,198,221 Claim 1
A graphics processing apparatus comprising:
A graphics processing apparatus comprising:
an interconnect to a host processor; and
a system interconnect to a host processor; and
a plurality of graphics processing clusters respectively including a plurality of multiprocessors coupled via an interconnect,
a plurality of graphics processing clusters, each of the plurality of graphics processing clusters including a plurality of multiprocessors coupled via a crossbar interconnect,
the crossbar interconnect to enable transfer of data from a first multiprocessor of the plurality of multiprocessors to a second multiprocessor of the plurality of multiprocessors,
a graphics processing cluster of the plurality of graphics processing clusters including:
a graphics processing cluster of the plurality of graphics processing clusters including:
a register file to store a plurality of different types of operands;
a register file to store a plurality of different types of operands;
a first plurality of processing resources of a first type configurable to process a first number of threads having operands stored in a first number of registers of the register file; and
a first plurality of processing resources of a first type configurable to process a first number of threads having operands stored in a first number of registers of the register file; and
a second plurality of processing resources of a second type configurable to process a second number of threads having operands stored in a second number of registers of the register file,
a second plurality of processing resources of a second type configurable to process a second number of threads having operands stored in a second number of registers of the register file,
the first number of threads greater than the second number of threads and the second number of registers greater than the first number of registers.
the first number of threads greater than the second number of threads and the second number of registers greater than the first number of registers.
Claim 1 of the present application differs from claim 1 of the patent application in that claim 1 of the present application is broader in scope than claim 1 of the patent application, thus encompasses that of the patent application.
Present Application #18/971,949 Claim 2
U.S. Patent #12,198,221 Claim 2
The graphics processing apparatus of claim 1, wherein
The graphics processing apparatus of claim 1, wherein
the first plurality of processing resources is configured to perform multi-dimensional matrix operations on the operands stored in the first number of registers.
the first plurality of processing resources is configured to perform multi-dimensional matrix operations on the operands stored in the first number of registers.
Present Application #18/971,949 Claim 3
U.S. Patent #12,198,221 Claim 3
The graphics processing apparatus of claim 1, wherein
The graphics processing apparatus of claim 1, wherein
the second plurality of processing resources is configured to perform graphics operations on the operands stored in the second number of registers.
the second plurality of processing resources is configured to perform graphics operations on the operands stored in the second number of registers.
Present Application #18/971,949 Claim 4
U.S. Patent #12,198,221 Claim 4
The graphics processing apparatus of claim 1, further comprising
The graphics processing apparatus of claim 1, further comprising
compute circuitry to select processing resources to execute a workload.
compute circuitry to select processing resources from the first plurality of processing resources and the second plurality of processing resources to execute a workload.
Present Application #18/971,949 Claim 5
U.S. Patent #12,198,221 Claim 5
The graphics processing apparatus of claim 4, wherein
The graphics processing apparatus of claim 4, wherein
the compute circuitry is to select processing resources of the first type to process a first type of application workload and to select the processing resources of the second type to process a second type of application workload.
the compute circuitry is to select processing resources of the first type to process a first type of application workload and to select the processing resources of the second type to process a second type of application workload.
Present Application #18/971,949 Claim 6
U.S. Patent #12,198,221 Claim 6
The graphics processing apparatus of claim 1, further comprising
The graphics processing apparatus of claim 1, further comprising
a memory device coupled with the plurality of graphics processing clusters.
a memory device coupled with the plurality of graphics processing clusters.
Present Application #18/971,949 Claim 7
U.S. Patent #12,198,221 Claim 7
The graphics processing apparatus of claim 6, wherein
The graphics processing apparatus of claim 6, wherein
the memory device includes a high bandwidth memory (HBM) including a plurality of memory channels.
the memory device includes a high bandwidth memory (HBM) including a plurality of memory channels.
Present Application #18/971,949 Claim 8
U.S. Patent #12,198,221 Claim 8
The graphics processing apparatus of claim 7, wherein
The graphics processing apparatus of claim 7, wherein
a first memory channel of the HBM is configured to couple with one or more processing resources of the first plurality of processing resources of a first type and a second memory channel of the HBM is configured to couple with one or more processing resources of the second plurality of processing resources of a second type.
a first memory channel of the HBM is configured to couple with one or more processing resources of the first plurality of processing resources of a first type and a second memory channel of the HBM is configured to couple with one or more processing resources of the second plurality of processing resources of a second type, the second memory channel distinct from the first memory channel.
Present Application #18/971,949 Claim 9
U.S. Patent #12,198,221 Claim 9
The graphics processing apparatus of claim 1, wherein
The graphics processing apparatus of claim 1, wherein
the register file is configured to perform matrix-vector transformations.
the register file is configured to perform matrix-vector transformations.
Present Application #18/971,949 Claim 10
U.S. Patent #12,198,221 Claim 10
The graphics processing apparatus of claim 1, further comprising
The graphics processing apparatus of claim 1, further comprising
a shared local memory (SLM) configured to perform matrix-vector transformations.
a shared local memory (SLM) configured to perform matrix-vector transformations.
Present Application #18/971,949 Claim 11
U.S. Patent #12,198,221 Claim 11
A method comprising:
A method comprising:
storing operands for a plurality of different types of operations to a register file of a graphics processing including a plurality of graphics processing clusters of a graphics processor,
storing operands for a plurality of different types of operations to a register file of a graphics processor including a plurality of graphics processing clusters,
each of the plurality of graphics processing clusters including a plurality of multiprocessors coupled via an interconnect;
each of the plurality of graphics processing clusters including a plurality of multiprocessors coupled via a crossbar interconnect,
the crossbar interconnect to enable transfer of data from a first multiprocessor of the plurality of multiprocessors to a second multiprocessor of the plurality of multiprocessors;
processing a first number of threads having operands stored in a first number of registers of the register file via a first plurality of processing resources of a first type; and
processing a first number of threads having operands stored in a first number of registers of the register file via a first plurality of processing resources of a first type; and
processing second number of threads having operands stored in a second number of registers of the register file via a second plurality of processing resources of a second type,
processing second number of threads having operands stored in a second number of registers of the register file via a second plurality of processing resources of a second type,
the first number of threads greater than the second number of threads and the second number of registers greater than the first number of registers.
the first number of threads greater than the second number of threads and the second number of registers greater than the first number of registers.
Claim 11 of the present application differs from claim 11 of the patent application in that claim 11 of the present application is broader in scope than claim 11 of the patent application, thus encompasses that of the patent application.
Present Application #18/971,949 Claim 12
U.S. Patent #12,198,221 Claim 12
The method of claim 11, comprising:
The method of claim 11, comprising:
performing multi-dimensional matrix operations on the operands stored in the first number of registers via the first plurality of processing resources; and
performing multi-dimensional matrix operations on the operands stored in the first number of registers via the first plurality of processing resources; and
performing graphics operations on the operands stored in the second number of registers via the second plurality of processing resources.
performing graphics operations on the operands stored in the second number of registers via the second plurality of processing resources.
Present Application #18/971,949 Claim 13
U.S. Patent #12,198,221 Claim 13
The method of claim 11, further comprising
The method of claim 11, further comprising
selecting processing resources to execute a workload via compute circuitry of the graphics processor, including selecting processing resources of the first type to process a first type of application workload and selecting the processing resources of the second type to process a second type of application workload.
selecting processing resources to execute a workload via compute circuitry of the graphics processor, including selecting processing resources of the first type to process a first type of application workload and selecting the processing resources of the second type to process a second type of application workload.
Present Application #18/971,949 Claim 14
U.S. Patent #12,198,221 Claim 14
The method of claim 11, further comprising
The method of claim 11, further comprising
performing matrix-vector transformations via the register file of the graphics processor.
performing matrix-vector transformations via the register file of the graphics processor.
Present Application #18/971,949 Claim 15
U.S. Patent #12,198,221 Claim 15
The method of claim 11, further comprising
The method of claim 11, further comprising
performing matrix-vector transformations via shared local memory (SLM) of the graphics processor.
performing matrix-vector transformations via shared local memory (SLM) of the graphics processor.
Present Application #18/971,949 Claim 16
U.S. Patent #12,198,221 Claim 16
A graphics processing system comprising:
A graphics processing system comprising:
an interconnect to a host processor;
a system interconnect to a host processor;
a memory device coupled with the interconnect; and
a memory device coupled with the system interconnect; and
a graphics processor coupled with the interconnect and the memory device, the graphics processor including a plurality of graphics processing clusters,
a graphics processor coupled with the system interconnect and the memory device, the graphics processor including a plurality of graphics processing clusters,
each of the plurality of graphics processing clusters including a plurality of multiprocessors coupled via an interconnect,
each of the plurality of graphics processing clusters including a plurality of multiprocessors coupled via a crossbar interconnect,
the crossbar interconnect to enable transfer of data from a first multiprocessor of the plurality of multiprocessors to a second multiprocessor of the plurality of multiprocessors,
a graphics processing cluster of the plurality of graphics processing clusters including:
a graphics processing cluster of the plurality of graphics processing clusters including:
a register file to store a plurality of different types of operands;
a register file to store a plurality of different types of operands;
a first plurality of processing resources of a first type configurable to process a first number of threads having operands stored in a first number of registers of the register file; and
a first plurality of processing resources of a first type configurable to process a first number of threads having operands stored in a first number of registers of the register file; and
a second plurality of processing resources of a second type configurable to process a second number of threads having operands stored in a second number of registers of the register file,
a second plurality of processing resources of a second type configurable to process a second number of threads having operands stored in a second number of registers of the register file,
the first number of threads greater than the second number of threads and the second number of registers greater than the first number of registers.
the first number of threads greater than the second number of threads and the second number of registers from greater than the first number of registers.
Claim 16 of the present application differs from claim 16 of the patent application in that claim 16 of the present application is broader in scope than claim 16 of the patent application, thus encompasses that of the patent application.
Present Application #18/971,949 Claim 17
U.S. Patent #12,198,221 Claim 17
The graphics processing system of claim 16, wherein
The graphics processing system of claim 16, wherein
the first plurality of processing resources is configured to perform multi-dimensional matrix operations on the operands stored in the first number of registers and the second plurality of processing resources is configured to perform graphics operations on the operands stored in the second number of registers.
the first plurality of processing resources is configured to perform multi-dimensional matrix operations on the operands stored in the first number of registers and the second plurality of processing resources is configured to perform graphics operations on the operands stored in the second number of registers.
Present Application #18/971,949 Claim 18
U.S. Patent #12,198,221 Claim 18
The graphics processing system of claim 16, further comprising
The graphics processing system of claim 16, further comprising
compute circuitry to select processing resources to execute a workload, the compute circuitry to select processing resources of the first type to process a first type of application workload and to select the processing resources of the second type to process a second type of application workload.
compute circuitry to select processing resources to execute a workload, the compute circuitry to select processing resources of the first type to process a first type of application workload and to select the processing resources of the second type to process a second type of application workload.
Present Application #18/971,949 Claim 19
U.S. Patent #12,198,221 Claim 19
The graphics processing system of claim 16, wherein
The graphics processing system of claim 16, wherein
the memory device includes a high bandwidth memory (HBM) including a plurality of memory channels,
the memory device includes a high bandwidth memory (HBM) including a plurality of memory channels,
a first memory channel of the HBM is configured to couple with one or more processing resources of the first plurality of processing resources of a first type, and
a first memory channel of the HBM is configured to couple with one or more processing resources of the first plurality of processing resources of a first type, and
a second memory channel of the HBM is configured to couple with one or more processing resources of the second plurality of processing resources of a second type
a second memory channel of the HBM is configured to couple with one or more processing resources of the second plurality of processing resources of a second type, the second memory channel distinct from the first memory channel.
Present Application #18/971,949 Claim 20
U.S. Patent #12,198,221 Claim 20
The graphics processing system of claim 16, wherein
The graphics processing system of claim 16, wherein
the register file is configured to perform matrix-vector transformations and further comprising a shared local memory (SLM) configured to perform matrix-vector transformations.
the register file is configured to perform matrix-vector transformations and further comprising a shared local memory (SLM) configured to perform matrix-vector transformations.
Allowable Subject Matter
Claims 1-20 would be allowable if the Double Patenting rejection set forth above may be overcome.
The following is a statement of reasons for the indication of allowable subject matter: The present invention relates to a system having processing resources of different types and a method of processing different number of threads having operands stored in different registers of a register file. Prior art includes:
Sun et al. (US 10,424,069) disclose a graphics processing apparatus (Figure 3, parallel processing unit (PPU) 300, where column 11, lines 4-9 notes PPU 300 is a graphics processing unit (GPU)) comprising: an interconnect to a host processor (e.g. interconnect 302 and/or NVLink 310, where column 11, lines 29-37 notes PPU 300 may be connected to a host processor via one or more high-speed NVLink 310 interconnect or may further be connected to a host processor via an interconnect 302); and a plurality of graphics processing clusters (e.g. general purpose clusters (GPCs) 350X) respectively including a plurality of multiprocessors coupled via an interconnect (Figure 4A further illustrates GPCs to further include a plurality of streaming multiprocessors (SMs) 440, where interconnects considered denoted by arrows), a graphics processing cluster of the plurality of graphics processing clusters (e.g. a GPC 350, further comprising SMs 440) including: a register file (Figure 5A, register file 520) to store a plurality of different types of operands (column 17, lines 30-32 notes register file 520 provides temporary storage for operands connected to the data paths of the functional units of SM 440, e.g. processing cores 550, special functional units (SFUs) 552, and load store units (LSUs) 554); a first plurality of processing resources of a first type (L processing cores 550 as tensor cores, column 17, lines 33 and 45-47) configurable to process a first number of threads (e.g. to process a first number of threads, e.g. as a warp) having operands stored in a first number of registers of the register file (e.g. having operands stored in a first number of registers of register file 520)(column 14, lines 40-67 notes SMs 440 may be configured to process tasks represented by a number of threads, e.g. as a warp, where column 17, lines 24-32 notes each SM 440 includes register file 520 that provides a set of registers for the functional units of the SM 440, the register file is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file 520, and/or the register file 520 is divided between different warps being executed by the SM 440, the register file storing operands for the functional units); and a second plurality of processing resources of a second type (L processing cores 550 as arithmetic cores, column 17, lines 33-44) configurable to process a second number of threads (e.g. to process a second number of threads, e.g. as a warp) having operands stored in a second number of registers of the register file (e.g. having operands stored in a second number of registers of register file 520)(as noted above, SMs 440 to process tasks represented by a number of threads, e.g. as a warp, considered a “second number of threads” since executed by a different set of L processing cores 550 than the tensor cores, and further to be allocated a different dedicated portion of register file 520 than the tensor cores noted above), the second number of registers different from the first number of registers (e.g. the second number of registers different from the first number of registers in that dedicated portions are allocated to the functional units, thus may be allocated to processing cores as tensor cores and processing cores as arithmetic cores, respectively);
Nystad (US 10,559,055) disclose a system comprising a programmable execution unit and method of using at least two different register file mapping configurations for mapping registers to execution threads, e.g. when a shader program is to be executed, how the shader program will use the registers is considered and the register file mapping configuration to use for the shader program is then selected based on the assessment of the register use by the shader program, and appropriate state information is then set to cause the threads being executed by the programmable execution unit to use the registers according to the selected register file mapping configuration when executing the shader program; and
Rawson, III et al. (US 9,501,285) disclose a system and method of dynamically allocating and deallocating physical registers to threads.
Although the prior art of record discloses certain features of the claimed invention as outlined above, the prior art of record fails to explicitly teach or suggest, singly or combined, “…the first number of threads greater than the second number of threads and the second number of registers greater than the first number of registers” as recited by independent claims 1, 11, and 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACINTA M CRAWFORD whose telephone number is (571)270-1539. The examiner can normally be reached 8:30a.m. to 4:30p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, King Y. Poon can be reached at (571)272-7440. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617
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