DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6-10, 16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 9,917,607 B1, hereinafter, “Zhang”) in view of HADAR et al. (US 2022/0014400 A1, hereinafter, “Hadar”).
Consider claim 16, Zhang teaches an optical transceiver (see figure 1, col. 2 lines 39-60 and col. 10 lines 49-54) , comprising: a temperature tracking component (see at least figure 1 (120, 160) and col. 4 lines 14-47, Zhang teaches a component that tracks changes in temperature); and a clock and data recovery (CDR) component (see at least figure 1 (130) and description thereof), the CDR component including: a continuous time linear equalizer (CTLE) circuit (figure 1 (242, 244) and description thereof), wherein the CTLE circuit is set with a variable gain value (see at least figure 2 (242, 244) and col. 4 lines 48-58, Zhang teaches CTLE circuit set with a variable gain value via VGA), wherein the variable gain value is set based on a temperature tracking/changes performed by the temperature tracking component (see col. 4 lines 42-58, Zhang teaches track gain variation due to temperature changes).
Zhang teaches a temperature tracking component (see above), however, did not particularly teach a temperature measuring component and wherein the variable gain value is set based on a temperature measurement performed by the temperature measurement component. Hadar teaches said limitation (see at least figure 2 (204-206), figure 3 (302-304) and paras. 25-27, Hadar teaches setting gain value based on temperature measurement (via temperature reading component)).
It would have been obvious to one of ordinary skill in the art at the time of the application to modify the invention of Zhang and teach a temperature measuring component and wherein the variable gain value is set based on a temperature measurement performed by the temperature measurement component, as taught by Hadar, thereby, allowing compensation of lost signal/data.
Zhang teaches a clock and data recovery (CDR) component (see above), however, did not explicitly teach a CDR chip. Hadar teaches said component (see at least paras. 27, 34 and figure 7 (700)).
It would have been obvious to one of ordinary skill in the art at the time of the application to modify the invention of Zhang and a CDR chip, as taught by Hadar, thereby, allowing compensation of lost signal/data.
Consider claim 1: all of the limitations indicated in apparatus claim 1 are included in the system claim 16, therefore, claim 1 is subjected to the same rejection applied to claim 16.
Consider claim 9, Zhang teaches a method (see abstract, figures 1-3 and description thereof), comprising: receiving, by a controller, information identifying a temperature tracking of a clock and data recovery (CDR) component (see figure 1 (130) and col. 4 lines 22-47) ; a clock and data recovery (CDR) component (see at least figure 1 (130) and description thereof), the CDR component including: a continuous time linear equalizer (CTLE) circuit (figure 1 (242, 244) and description thereof), wherein the CTLE circuit is set with a variable gain value (see at least figure 2 (242, 244) and col. 4 lines 48-58, Zhang teaches CTLE circuit set with a variable gain value via VGA),
Zhang teaches a clock and data recovery (CDR) component (see above), however, did not explicitly teach a CDR chip. Hadar teaches said component (see at least paras. 27, 34 and figure 7 (700)).
It would have been obvious to one of ordinary skill in the art at the time of the application to modify the invention of Zhang and a CDR chip, as taught by Hadar, thereby, allowing compensation of lost signal/data.
Zhang teaches a clock and data recovery (CDR) component (see above), however, did not particularly teach determining, by the controller, a control signal based on the temperature measurement. Hadar teaches said technique (see at least figure 3 (302-304), paras. 23-26 and 34-37, Hadar teaches sending/reading via signal or information data, temperature measurement, thus control signal).
It would have been obvious to one of ordinary skill in the art at the time of the application to modify the invention of Zhang and teach determining, by the controller, a control signal based on the temperature measurement, as taught by Hadar, thereby, allowing compensation of lost signal/data.
Zhang teaches the CTLE circuit is set with a variable gain value (see above), however, did not particularly teach providing, by the controller, the control signal to configure a gain value of a continuous time linear equalizer (CTLE) circuit of the CDR chip. Hadar teaches said limitation (see at least figure 2 (204-206), figure 3 (302-304) and paras. 25-27, Hadar teaches setting gain value of CTLE via a signal based on temperature measurement (via temperature reading component)).
It would have been obvious to one of ordinary skill in the art at the time of the application to modify the invention of Zhang and teach providing, by the controller, the control signal to configure a gain value of a continuous time linear equalizer (CTLE) circuit of the CDR chip, as taught by Hadar, thereby, allowing compensation of lost signal/data.
Consider claim 2, Zhang in view of Hadar teaches wherein the variable gain value is based on a temperature measurement performed by the temperature measurement component see at least figure 1 (120, 160) and col. 4 lines 14-47 in Zhang; see at least figure 2 (204-206), figure 3 (302-304) and paras. 25-27 in Hadar).
Consider claims 3 and 19, Zhang in view of Hadar teaches the variable gain value is based on at least one of: a bit error rate (see at least para. 20 and figure 3 in Hadar).
Consider claim 6, Zhang in view of Hadar teaches the variable gain value is based on an output of a feedback loop (see figure 2 (output from 160 to 140) and description thereof in Zhang).
Consider claim 7, Zhang in view of Hadar teaches the variable gain value is based on a mapping of possible outputs of the temperature measurement component to possible variable gain values (see at least figure 3 and description thereof in Hadar, where Hadar teaches iterations/interpolations of mapping possible output temperature measurement to possible gain values).
Consider claim 8, Zhang in view of Hadar teaches an interpolation component configured to set the variable gain value based on an interpolation within a set of possible variable gain values (see at least figure 3 and description thereof in Hadar, where Hadar teaches iterations/interpolations of mapping possible output temperature measurement to possible gain values).
Consider claim 10, Zhang in view of Hadar teaches performing a linear interpolation procedure to identify the gain value, between two possible gain values for the CTLE circuit (see at least figure 3 and description thereof in Hadar, where Hadar teaches iterations/interpolations of mapping possible output temperature measurement to possible gain values).
Allowable Subject Matter
Claims 4, 5, 11-15, 17, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FITWI Y HAILEGIORGIS whose telephone number is (571)270-1881. The examiner can normally be reached M-F 10AM-6PM.
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FITWI Y. HAILEGIORGIS
Primary Examiner
Art Unit 2632
/FITWI Y HAILEGIORGIS/ Examiner, Art Unit 2632
Prosecution Insights