Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh (US 2018/0188584) in view of Kim (US 2023/0329051)
Regarding claim 1, Yeh teaches a display panel (Fig. 6-7B, Fig. 9A-9G and Fig. 1, [0054-0101]) comprising:
a substrate (the first/TFT substrate of 100 in Fig. 6-7B and Fig. 1, [0054, 0005]) having a display area (the area corresponding to 101 in Fig. 1 and Fig. 6) and a non-display area (the area corresponding to 102 in Fig. 1 and Fig. 6, [0005, 0055]) that surrounds the display area (Fig. 1 and Fig. 6, [0005, 0055]);
a plurality of gate lines (the lines corresponding to 430/G1-G4 in Fig. 6 and Fig. 1) and a plurality of data lines (the lines corresponding to 431/D1-D4 in Fig. 6 and Fig. 1) on the substrate, the plurality of gate lines and the plurality of data lines intersecting each other in the display area (Fig. 1 and Fig. 6) and define a plurality of pixel areas (the pixels corresponding to P11-P44 in Fig. 1, Fig. 6);
a plurality of pixel electrodes (the electrodes corresponding to PE in Fig. 6 and Fig. 1) respectively disposed in the plurality of pixel areas (Fig. 1 and Fig. 6);
a plurality of common electrodes (the electrodes corresponding to COM in Fig. 7A-7B) overlapping the plurality of pixel electrodes (Fig. 7A-7B), the plurality of common electrodes located on a different layer than the plurality of pixel electrodes (Fig. 7A-7B);
a plurality of touch lines (the lines corresponding to 432/S1-S4 in Fig. 6 and Fig. 1) connected respectively to (Fig. 7A-7B) the plurality of common electrodes (the electrodes corresponding to COM in Fig. 7A-7B);
a plurality of data pad electrodes (the pad corresponding to 121/122/123/124 in Fig. 1, Fig. 6, [0058, 0098]) in the non-display area (the area corresponding to 102 in Fig. 1 and Fig. 6, [0005, 0055]), the plurality of data pad electrodes (the pad corresponding to 121/122/123/124 in Fig. 1, Fig. 6, [0058, 0098]) being electrically connected to (Fig. 1, Fig. 6, [0098, 0058,]) the plurality of data lines (the lines corresponding to 431/D1-D4 in Fig. 6 and Fig. 1); and
a plurality of touch pad electrodes (the pad corresponding to 131/132/133/134 in Fig. 1, Fig. 6 and Fig. 9A-9G, [0058, 0091-0096]) in the non-display area (the area corresponding to 102 in Fig. 1 and Fig. 6, [0005, 0055]), the plurality of touch pad electrodes (the pad corresponding to 131/132/133/134 in Fig. 1, Fig. 6 and Fig. 9A-9G, [0058, 0091-0096]) being electrically connected to (Fig. 1, Fig. 6 and Fig. 9A-9G, [0058, 0091-0096]) the plurality of touch lines (the lines corresponding to 432/S1-S4 in Fig. 6 and Fig. 1),
Yeh teaches that each of the plurality of data pad electrodes (the pad corresponding to 121/122/123/124 in Fig. 1, Fig. 6, [0058, 0098]) and the plurality of touch pad electrodes (the pad corresponding to 131/132/133/134 in Fig. 1, Fig. 6 and Fig. 9A-9G, [0058, 0091-0096]) comprises a lower first wiring layer ([0068, 0095], Fig. 9A-9G), and each of the plurality of data pad electrodes (the pad corresponding to 121/122/123/124 in Fig. 1, Fig. 6, [0058, 0098]) and the plurality of touch pad electrodes (the pad corresponding to 131/132/133/134 in Fig. 1, Fig. 6 and Fig. 9A-9G, [0058, 0091-0096]) is located below and electrically connected to a driving chip or a circuit board (110 in Fig. 1, [0058]). Yeh does not teach that each of the plurality of data pad electrodes and the plurality of touch pad electrodes comprises a first wiring layer, a second wiring layer, and a third wiring layer that overlap each other, and each of the plurality of data pad electrodes and the plurality of touch pad electrodes has a first connection hole that connects the first wiring layer and the second wiring layer and a second connection hole that connects the second wiring layer and the third wiring layer, and the first connection hole and the second connection hole are at different planar positions.
Kim teaches that (Fig. 6-13, [0110-0156]) each of a plurality of pad electrodes (DP-PD/PD1/PD2/PD3 in Fig. 10-13 and Fig. 6, [0125, 0114]) located below and electrically connected to a driving chip or a circuit board (Fig. 6, Fig. 10-13, [0114, 0125]) comprises a first wiring layer (the Layer corresponding to DL-E in Fig. 10-13, [0115]), a second wiring layer (the Layer corresponding to CL1 in Fig. 10-13, [0121-0124]), and a third wiring layer (the Layer corresponding to CL2 in Fig. 10-13, [0117-0119, 0121-0122]) that overlap each other (Fig. 10-13), and each of the plurality of pad electrodes (DP-PD/PD1/PD2/PD3 in Fig. 10-13 and Fig. 6, [0125, 0114]) has a first connection hole (the hole corresponding to S-H in Fig. 10-13, [0127]) that connects the first wiring layer (the Layer corresponding to DL-E in Fig. 10-13, [0115]) and the second wiring layer (the Layer corresponding to CL1 in Fig. 10-13, [0121-0124]) and a second connection hole (the hole of 70 and IS-IL2 corresponding to CB1 in Fig. 10-13) that connects the second wiring layer (the Layer corresponding to CL1 in Fig. 10-13, [0121-0124]) and the third wiring layer (the Layer corresponding to CL2 in Fig. 10-13, [0117-0119, 0121-0122]), and the first connection hole (the hole corresponding to S-H in Fig. 10-13, [0127]) and the second connection hole (the hole of 70 and IS-IL2 corresponding to CB1 in Fig. 10-13) are at different planar positions (Fig. 10-13).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Kim for each of the plurality of data pad electrodes and the plurality of touch pad electrodes in the system of Yeh such that in the system of Yeh, each of the plurality of data pad electrodes and the plurality of touch pad electrodes comprises a first wiring layer, a second wiring layer, and a third wiring layer that overlap each other, and each of the plurality of data pad electrodes and the plurality of touch pad electrodes has a first connection hole that connects the first wiring layer and the second wiring layer and a second connection hole that connects the second wiring layer and the third wiring layer, and the first connection hole and the second connection hole are at different planar positions. The motivation is to prevent or reduce the breakage of the conductive pattern, and signal pads have relatively reduced defects (Kim, [0157-0159, 0007]).
Regarding claim 12, Yeh teaches a display device (Fig. 1, Fig. 6-7B, Fig. 9A-9G, [0054-0101]) comprising:
a first substrate and a second substrate that are opposite each other ([0005]), each of the first substrate and the second substrate ([0005]) having a display area (the area corresponding to 101 in Fig. 1 and Fig. 6) and a non-display area (the area corresponding to 102 in Fig. 1 and Fig. 6, [0005, 0055]) that surrounds the display area (Fig. 1 and Fig. 6, [0005, 0055]);
a plurality of gate lines (the lines corresponding to 430/G1-G4 in Fig. 6 and Fig. 1) and a plurality of data lines (the lines corresponding to 431/D1-D4 in Fig. 6 and Fig. 1) on the first substrate (Fig. 1 and 6), the plurality of gate lines and the plurality of data lines intersecting each other and define a plurality of pixel areas (the pixels corresponding to P11-P44 in Fig. 1, Fig. 6);
a plurality of pixel electrodes (the electrodes corresponding to PE in Fig. 6 and Fig. 1) respectively disposed in the plurality of pixel areas (Fig. 1 and Fig. 6);
a plurality of common electrodes (the electrodes corresponding to COM in Fig. 7A-7B) overlapping the plurality of pixel electrodes (Fig. 7A-7B), the plurality of common electrodes located on a different layer than the plurality of pixel electrodes (Fig. 7A-7B);
a plurality of touch lines (the lines corresponding to 432/S1-S4 in Fig. 6 and Fig. 1) connected respectively to (Fig. 7A-7B) the plurality of common electrodes (the electrodes corresponding to COM in Fig. 7A-7B);
a plurality of data pad electrodes (the pad corresponding to 121/122/123/124 in Fig. 1, Fig. 6, [0058, 0098]) in the non-display area (the area corresponding to 102 in Fig. 1 and Fig. 6, [0005, 0055]), the plurality of data pad electrodes (the pad corresponding to 121/122/123/124 in Fig. 1, Fig. 6, [0058, 0098]) electrically connected to (Fig. 1, Fig. 6, [0098, 0058,]) the plurality of data lines (the lines corresponding to 431/D1-D4 in Fig. 6 and Fig. 1);
a plurality of touch pad electrodes (the pad corresponding to 131/132/133/134 in Fig. 1, Fig. 6 and Fig. 9A-9G, [0058, 0091-0096]) in the non-display area (the area corresponding to 102 in Fig. 1 and Fig. 6, [0005, 0055]), the plurality of touch pad electrodes (the pad corresponding to 131/132/133/134 in Fig. 1, Fig. 6 and Fig. 9A-9G, [0058, 0091-0096]) electrically connected to (Fig. 1, Fig. 6 and Fig. 9A-9G, [0058, 0091-0096]) the plurality of touch lines (the lines corresponding to 432/S1-S4 in Fig. 6 and Fig. 1); and
a liquid crystal layer between the first substrate and the second substrate ([0005, 0069]).
Yeh teaches that each of the plurality of data pad electrodes (the pad corresponding to 121/122/123/124 in Fig. 1, Fig. 6, [0058, 0098]) and the plurality of touch pad electrodes (the pad corresponding to 131/132/133/134 in Fig. 1, Fig. 6 and Fig. 9A-9G, [0058, 0091-0096]) comprises a lower first wiring layer ([0068, 0095], Fig. 9A-9G), and each of the plurality of data pad electrodes (the pad corresponding to 121/122/123/124 in Fig. 1, Fig. 6, [0058, 0098]) and the plurality of touch pad electrodes (the pad corresponding to 131/132/133/134 in Fig. 1, Fig. 6 and Fig. 9A-9G, [0058, 0091-0096]) is located below and electrically connected to a driving chip or a circuit board (110 in Fig. 1, [0058]). Yeh does not teach that each of the plurality of data pad electrodes and the plurality of touch pad electrodes comprises a first wiring layer, a second wiring layer, and a third wiring layer overlapping each other, and each of the plurality of data pad electrodes and the plurality of touch pad electrodes has a first connection hole that connects the first wiring layer and the second wiring layer and a second connection hole that connects the second wiring layer and the third wiring layer, and the first connection hole and the second connection hole are at different planar positions.
Kim teaches that (Fig. 6-13, [0110-0156]) each of a plurality of pad electrodes (DP-PD/PD1/PD2/PD3 in Fig. 10-13 and Fig. 6, [0125, 0114]) located below and electrically connected to a driving chip or a circuit board (Fig. 6, Fig. 10-13, [0114, 0125]) comprises a first wiring layer (the Layer corresponding to DL-E in Fig. 10-13, [0115]), a second wiring layer (the Layer corresponding to CL1 in Fig. 10-13, [0121-0124]), and a third wiring layer (the Layer corresponding to CL2 in Fig. 10-13, [0117-0119, 0121-0122]) overlapping each other (Fig. 10-13), and each of the plurality of pad electrodes (DP-PD/PD1/PD2/PD3 in Fig. 10-13 and Fig. 6, [0125, 0114]) has a first connection hole (the hole corresponding to S-H in Fig. 10-13, [0127]) that connects the first wiring layer (the Layer corresponding to DL-E in Fig. 10-13, [0115]) and the second wiring layer (the Layer corresponding to CL1 in Fig. 10-13, [0121-0124]) and a second connection hole (the hole of 70 and IS-IL2 corresponding to CB1 in Fig. 10-13) that connects the second wiring layer (the Layer corresponding to CL1 in Fig. 10-13, [0121-0124]) and the third wiring layer (the Layer corresponding to CL2 in Fig. 10-13, [0117-0119, 0121-0122]), and the first connection hole (the hole corresponding to S-H in Fig. 10-13, [0127]) and the second connection hole (the hole of 70 and IS-IL2 corresponding to CB1 in Fig. 10-13) are at different planar positions (Fig. 10-13).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Kim for each of the plurality of data pad electrodes and the plurality of touch pad electrodes in the system of Yeh such that in the system of Yeh, each of the plurality of data pad electrodes and the plurality of touch pad electrodes comprises a first wiring layer, a second wiring layer, and a third wiring layer overlapping each other, and each of the plurality of data pad electrodes and the plurality of touch pad electrodes has a first connection hole that connects the first wiring layer and the second wiring layer and a second connection hole that connects the second wiring layer and the third wiring layer, and the first connection hole and the second connection hole are at different planar positions. The motivation is to prevent or reduce the breakage of the conductive pattern, and signal pads have relatively reduced defects (Kim, [0157-0159, 0007]).
Regarding claims 2 and 13, Yeh does not teach the following elements.
Kim teaches the following elements:
(Claims 2 and 13) the first connection hole (the hole corresponding to S-H in Fig. 10-13, [0127]) and the second connection hole (the hole of 70 and IS-IL2 corresponding to CB1 in Fig. 10-13) overlap at least one insulating film (the insulation layer 10/20/30/40 in Fig. 10-13).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Kim for the system of Yeh in view of Kim such that in the system of Yeh in view of Kim,
(Claims 2 and 13) the first connection hole and the second connection hole overlap at least one insulating film.
The motivation is to prevent or reduce the breakage of the conductive pattern, and signal pads have relatively reduced defects (Kim, [0157-0159, 0007]).
Regarding claims 10-11, Yeh also teaches the following elements:
(Claim 10) the plurality of pixel electrodes (the electrodes corresponding to PE/512 in Fig. 6, Fig. 7B) and the plurality of common electrodes (the electrodes corresponding to COM/511 in Fig. 7B) are transparent ([0069]).
(Claim 11) a drive chip or a flexible film (110 in Fig. 1, [0058]) having a plurality of lead electrodes that are connected to the plurality of data pad electrodes and the plurality of touch pad electrodes (Fig. 1, [0058]).
Claims 3-4 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh in view of Kim as applied to claims 1 and 12 above, and further in view of Dong (CN 109962077A).
Regarding claim 3, Yeh teaches that a first insulating film (INS1 in Fig. 7B) between the first wiring layer (M1 in Fig. 7B) and the second wiring layer (M2 in Fig. 7B); and a second insulating film (INS2 in Fig. 7B) between the second wiring layer (M2 in Fig. 7B) and the third wiring layer (511, M3 and/or 512 in Fig. 7B), wherein the first wiring layer (M1 in Fig. 7B) is on a same layer as the plurality of gate lines (420G in Fig. 6 and 7B), the second wiring layer (M2 in Fig. 7B) is on a same layer as the plurality of data lines (431 in Fig. 7B), and the third wiring layer (511, M3 and/or 512 in Fig. 7B) is on a same layer as the plurality of pixel electrodes (PE/512 in Fig. 7B) or the plurality of common electrodes (511/COM in Fig. 7B). Yeh does not teach the following elements.
Dong teaches the following elements (Fig. 13, Pages 5-7 of English translation of CN 109962077A):
(Claim 3) a second insulating film (12 in Fig. 13, Page 5, Paragraph 7), a third insulating film (13 in Fig. 13, Page 5, Paragraph 7) and a fourth insulating film (25 in Fig. 13, Page 5, Paragraph 7) between the second wiring layer (the layer corresponding to 8, 9 and 11 in Fig. 3 and 13) and the third wiring layer (the layer corresponding to 17, 18, 16 and/or 20 in Fig. 13).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Dong for the system of Yeh in view of Kim such that in the system of Yeh in view of Kim,
(Claim 3) a second insulating film, a third insulating film, and a fourth insulating film between the second wiring layer and the third wiring layer.
The motivation is to improve the quality of the product and improve the product reliability (Dong, Page 3, Paragraph 3).
Regarding claim 18, Yeh teaches that a first insulating film (INS1 in Fig. 7B) between the first wiring layer (M1 in Fig. 7B) and the second wiring layer (M2 in Fig. 7B); and a second insulating film (INS2 in Fig. 7B) between the second wiring layer (M2 in Fig. 7B) and the third wiring layer (511, M3 and/or 512 in Fig. 7B), wherein the first wiring layer (M1 in Fig. 7B) is on a same layer as the plurality of gate lines (420G in Fig. 6 and 7B), the second wiring layer (M2 in Fig. 7B) is on a same layer as the plurality of data lines (431 in Fig. 7B), and the third wiring layer (511, M3 and/or 512 in Fig. 7B) is on a same layer as a pixel electrode (PE/512 in Fig. 7B) from the plurality of pixel electrodes (PE/512 in Fig. 7B) or a common electrode (511/COM in Fig. 7B) from the plurality of common electrodes (511/COM in Fig. 7B). Yeh does not teach the following elements.
Dong teaches the following elements (Fig. 13, Pages 5-7 of English translation of CN 109962077A):
(Claim 18) a second insulating film (12 in Fig. 13, Page 5, Paragraph 7), a third insulating film (13 in Fig. 13, Page 5, Paragraph 7) and a fourth insulating film (25 in Fig. 13, Page 5, Paragraph 7) between the second wiring layer (the layer corresponding to 8, 9 and 11 in Fig. 3 and 13) and the third wiring layer (the layer corresponding to 17, 18, 16 and/or 20 in Fig. 13).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Dong for the system of Yeh in view of Kim such that in the system of Yeh in view of Kim,
(Claim 18) a second insulating film, a third insulating film, and a fourth insulating film between the second wiring layer and the third wiring layer.
The motivation is to improve the quality of the product and improve the product reliability (Dong, Page 3, Paragraph 3).
Regarding claims 4 and 19, Yeh does not teach the following elements.
Kim teaches the following elements (Fig. 12):
(Claims 4 and 19) the first connection hole (the hole corresponding to S-H4 in Fig. 12) is in a first insulating film (30 in Fig. 13) and overlaps at least a part of a second insulating film (70 in Fig. 12), and the second connection hole (the hole of 70 and IS-IL2 corresponding to CB1 in Fig. 10-13) is in the second insulating film (70 in Fig. 12) and overlaps the first insulating film (30 in Fig. 13).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Kim for the system of Yeh in view of Kim such that in the system of Yeh in view of Kim,
(Claims 4 and 19) the first connection hole is in the first insulating film and overlaps at least a part of the second insulating film, and the second connection hole is in the second insulating film and overlaps the first insulating film.
The motivation is to prevent or reduce the breakage of the conductive pattern, and signal pads have relatively reduced defects (Kim, [0157-0159, 0007]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh in view of Kim as applied to claim 1 above, and further in view of Han (US 2022/0164065).
Regarding claim 9, Yeh teaches that the plurality of touch pad electrodes (the pad corresponding to 131/132/133/134 in Fig. 1, Fig. 6 and Fig. 9A-9G, [0058, 0091-0096]) and the plurality of data pad electrodes (the pad corresponding to 121/122/123/124 in Fig. 1, Fig. 6, [0058, 0098]) are alternately disposed in parallel (Fig. 1).
Yeh does not teach the following elements.
Han teaches the following elements (Fig. 15-17, [0265-0316]):
(Claim 9) a first pad electrode (the electrode corresponding to TP1 in Fig. 15-16) and a second pad electrode (the electrode corresponding to TP2 in Fig. 15-16) that are adjacent to each other (Fig. 15-16) have convex portions at different locations (Fig. 15-16), a first connection hole (CH3a/CH4 in Fig. 15-16) and the second connection hole (CH2a/CH2b in Fig. 15-16) being in the convex portions (Fig. 15-16).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Han for the system of Yeh in view of Kim such that in the system of Yeh in view of Kim,
(Claim 9) a touch pad electrode and a data pad electrode that are adjacent to each other have convex portions at different locations, the first connection hole and the second connection hole being in the convex portions.
The motivation is that a bonding process electrically connecting the touch driving circuit to the touch/data pad electrode can be performed more easily, the number of pad electrodes being capable of disposing increases while maintaining a reliability (Han, [0278, 0317]).
Allowable Subject Matter
Claims 5-8 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art of record discloses or suggests all the combination of a display panel or a display device as set forth in claims 5-8 and 14-17.
Regarding claims 5-8, none of the prior art discloses or suggests a display panel recited in claim 1, wherein “the plurality of touch lines are between the plurality of pixel electrodes and the plurality of common electrodes, each of the plurality of touch pad electrodes further comprises a fourth wiring layer extending from one of the plurality of touch lines and the fourth wiring layer is between the second wiring layer and the third wiring layer” in combination with the other required elements of the claim.
Regarding claims 14-17, none of the prior art discloses or suggests a display device recited in claim 12, wherein “the plurality of touch lines are between a pixel electrode from the plurality of pixel electrodes and a common electrode from the plurality of common electrodes, each of the plurality of touch pad electrodes further comprises a fourth wiring layer extending from a touch line from the plurality of touch lines, and the fourth wiring layer is between the second wiring layer and the third wiring layer” in combination with the other required elements of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAN LIU whose telephone number is (571)270-0383. The examiner can normally be reached on 9am-5pm EST M-F.
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/Shan Liu/
Primary Examiner, Art Unit 2871
Prosecution Insights