Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in the file.
2. Claims 9-28 are presented for examination.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
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4. Claims 9-28 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 12198753. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 9-16 of the examined application are anticipated and the same scope of invention by claims 1-8 of the reference such as a memory device comprising: a first chip including a memory cell area and a first metal pad, wherein the memory cell area includes: a plurality of word lines extending in a first horizontal direction; and a plurality of memory blocks separated from each other by a plurality of word line cut areas extending long in the first horizontal direction, and wherein the memory cell area is divided into a normal cell area in which a plurality of normal memory blocks among the plurality of memory blocks are disposed and a dummy cell area in which a plurality of dummy memory blocks among the plurality of memory blocks are disposed; and a second chip including a second metal pad and a peripheral circuit area, wherein the peripheral circuit area is connected to the memory cell area in a vertical direction by the first metal pad and the second metal pad connected with each other, wherein the peripheral circuit area includes a row decoder area in which a row decoder circuit for controlling a plurality of word lines of each memory block of the plurality of memory blocks of the normal cell area is disposed, wherein, when viewed in a plan view, the row decoder area is adjacent to the plurality of memory blocks, and where in the row decoder circuit includes: a first unit row decoder circuit connected to n normal memory blocks of the plurality of normal memory blocks, and a second unit row decoder circuit connected to m normal memory blocks of the plurality of normal memory blocks, the m and the n being positive integers and the m being smaller than the n.
The claim 9 of examined application are obvious over the claims 1 and 5 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a second chip while in the reference claimed a cell array structure vertically overlapping the peripheral circuit structure in a claim 1 and the memory cell area is divided into a plurality of tiles (i.e., a plurality of planes) in a claim 5. Therefore, one of ordinary skill in the art would have recognized that the tiles or the planes would be a plurality of chips.
A metal pad in a claim 9 is obvious in the reference claimed the cell array structure vertically overlapping the peripheral circuit structure
Claims 17-22 of the examined application are anticipated and the same scope of invention by claims 1-8 of the reference such as a memory device comprising: a first chip including: a memory cell area; a pair of dummy step areas disposed on opposite sides of the memory cell area; and a first metal pad, wherein the memory cell area includes: a plurality of word lines extending in a first horizontal direction, and a plurality of memory blocks separated from each other by a plurality of word line cut areas extending long in the first horizontal direction, wherein the memory cell area is divided into a normal cell area in which a plurality of normal memory blocks are disposed and a dummy cell area in which a plurality of dummy memory blocks are disposed, and wherein, in each dummy step area of the pair of dummy step areas, the plurality of word lines extend parallel to each other in the first horizontal direction and a second horizontal direction crossing the first horizontal direction and vertically overlap each other; and a second chip including a second metal pad and a peripheral circuit area, wherein the peripheral circuit area is connected in a vertical direction to the memory cell area by the first metal pad and the second metal pad connected with each other, wherein the peripheral circuit area includes a row decoder area in which a row decoder circuit for controlling a plurality of word lines of each memory block of the plurality of memory blocks of the normal cell area is disposed, wherein, when viewed in a plan view, the row decoder area is adjacent to the plurality of memory blocks, wherein the row decoder circuit includes: a first unit row decoder circuit connected to n normal memory blocks of the plurality of normal memory blocks, and a second unit row decoder circuit connected to m first normal memory blocks of the plurality of normal memory blocks, the m and the n being positive integers and the m being smaller than the n, wherein the second unit row decoder circuit is adjacent to an area where a first dummy step area among the pair of dummy step areas and the m first normal memory blocks are disposed, and wherein a height, in the second horizontal direction, of the second unit row decoder circuit corresponds to a sum of block heights of the m first normal memory blocks and a height, in the second horizontal direction, of the first dummy step area.
The claim 17 of examined application are obvious over the claims 1 and 5 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a second chip while in the reference claimed a cell array structure vertically overlapping the peripheral circuit structure in a claim 1 and the memory cell area is divided into a plurality of tiles (i.e., a plurality of planes) in a claim 5. Therefore, one of ordinary skill in the art would have recognized that the tiles or the planes would be a plurality of chips.
A metal pad in a claim 17 is obvious in the reference claimed the cell array structure vertically overlapping the peripheral circuit structure.
Claims 23-28 of the examined application are anticipated and the same scope of invention by claims 1-8 of the reference such as a memory device comprising: a first chip including a first memory cell area and a plurality of first metal pads, wherein the first memory cell area includes: a plurality of first word lines extending in a first horizontal direction; a plurality of first bit lines extending in a second horizontal direction crossing the first horizontal direction; and a plurality of first memory blocks separated from each other by a plurality of first word line cut areas extending long in the first horizontal direction, and wherein the first memory cell area is divided into a first normal cell area in which a plurality of first normal memory blocks among the plurality of first memory blocks are disposed and a first dummy cell area in which a plurality of first dummy memory blocks among the plurality of first memory blocks are disposed; a second chip including a second memory cell area and a plurality of second metal pads, wherein the second memory cell area includes: a plurality of second word lines extending in the first horizontal direction; a plurality of second bit lines extending in the second horizontal direction; and a plurality of second memory blocks separated from each other by a plurality of second word line cut areas extending long in the first horizontal direction, and where in the second memory cell area is divided into a second normal cell area in which a plurality of second normal memory blocks among the plurality of second memory blocks are disposed and a second dummy cell area in which a plurality of second dummy memory blocks among the plurality of second memory blocks are disposed; and a third chip including a plurality of third metal pads and a peripheral circuit area, wherein the peripheral circuit area is connected in a vertical direction to the first memory cell area and the second memory cell area by the plurality of first metal pads, the plurality of second metal pads and the plurality of third metal pads connected with each other, wherein the peripheral circuit area includes a row decoder area in which a row decoder circuit for controlling the plurality of first word lines of each memory block of the plurality of first memory blocks of the first normal cell area and the plurality of second word lines of each memory block of the plurality of second memory blocks of the second normal cell area is disposed, wherein, when viewed in a plan view, the row decoder area is adjacent to the plurality of first memory blocks and the plurality of second memory blocks, and wherein the row decoder circuit includes: a first unit row decoder circuit connected to n first normal memory blocks of the plurality of first normal memory blocks and n second normal memory blocks of the plurality of second normal memory blocks, and a second unit row decoder circuit connected to m first normal memory blocks of the plurality of first normal memory blocks and m second normal memory blocks of the plurality of second normal memory blocks, the m and the n being positive integers and the m being smaller than the n.
The claim 23 of examined application are obvious over the claims 1 and 5 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites second and third chips while in the reference claimed a cell array structure vertically overlapping the peripheral circuit structure in a claim 1 and the memory cell area is divided into a plurality of tiles (i.e., a plurality of planes) in a claim 5. Therefore, one of ordinary skill in the art would have recognized that the tiles or the planes would be a plurality of chips.
A metal pad in a claim 23 is obvious in the reference claimed the cell array structure vertically overlapping the peripheral circuit structure.
6. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
7. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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