DETAILED ACTION
Claims 1-20 are currently pending in the application and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 02/20/2025 and 04/21/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 5 is objected to because of the following informalities: The acronym “the MEC setting” should be expanded to read “the module error correction (MEC) setting”. Appropriate correction is required. A better way would be to add “(MEC)” to claim 1, line 4 to read “a module error correction (MEC) setting”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 8-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6:
This claim recites the limitation "the change syndrome" in line 3. There is insufficient antecedent basis for this limitation in the claim. It appears that this should read “the changed state of the syndrome”. Correction is required.
Claim 8:
claim recites the limitation "the changed plurality of syndrome bits " in lines 6 and 9. There is insufficient antecedent basis for this limitation in the claim. It appears that this should read “the changed state of the plurality of syndrome bits”. Correction is required.
Claim 10:
This claim recites the limitation "the corrected plurality of parity bits" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 11:
This claim recites the limitation “the behavior of a module error correction circuit” in line 3. There is insufficient antecedent basis for the limitation “the behavior” in the claim.
Claims 9 and 12:
These claims are also rejected because they depend on a base rejected claim and have the same problems of insufficient antecedent basis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 13-17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Geiger et al. (US-20220399902), hereinafter Geiger, in view of HALBERT et al. (US-20180203761), hereinafter HALBERT.
Claim 1:
Geiger teaches an apparatus comprising:
a memory array configured to store a plurality of data bits and a plurality of parity bits (¶¶ [0013], [0051]; Figs 1-3);
a mode register configured to store a module error correction setting (¶¶ [0013], [0026], [0036]-[0038]; responsive to the multi-bit error (MBE) signal being active, an MBE flag in a mode register 132 may be set);
an error correction code (ECC) circuit (Fig. 2 ECC circuit 208) configured to determine if there is a correctable error in the plurality of data bits and parity bits (The mapped states are those the ECC circuit 120 is capable of interpreting as single bit error locations (or no errors) and correcting (if needed); Abstract, ¶¶ [0012], [0025], [0027]. The ECC circuit 208 may use the read parity bits and the read data bits to generate syndrome bits. The syndrome bits may in turn be used to locate and correct a single bit error in the read data, ¶ [0035]).
Geiger does not explicitly teach “configured to alias one of a subset of the plurality of data bits if the module error correction setting is enabled”. However, HALBERT teaches in an analogous art Single error correction (SEC) codes can detect and correct single bit errors but will not correct double bit errors. Aliasing a bit error can refer to the ECC process of selecting a correct bit to invert in an ECC operation based on ECC computations. (¶¶ [0023]-[0025], [0042], [0045], [0063]). It would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to add HALBERT’s aliasing capabilities to Geiger’s ECC circuit and multibit error (MBE) detection logic 210. The artisan would be motivated to do so because it would enable Geiger to expand the types of errors that can be corrected.
Claim 3:
Geiger teaches the subset of the plurality of data bits is a specified range of burst bits, a specified data terminal, or combinations thereof (¶ [0060]: data may be organized into bursts).
Claim 4:
Geiger teaches the ECC circuit is further configured to generate a plurality of syndrome bits based on the plurality of data bits and the plurality of parity bits, wherein a state of the plurality of syndrome bits determines if there is a correctable error (¶¶ [0027], [0072]; claim 8: the ECC circuit is configured to generate the syndrome bits based on the data bits and the parity bits; the mapped state is the ECC circuit capable of correcting the bit error).
Claim 5:
Geiger teaches the ECC circuit comprises an alias logic circuit which, when enabled by the MEC setting, is configured to determine if the state of the plurality of syndrome bits indicates no error, an error in one of the plurality of data bits, or an error in one of the plurality of parity bits and if it does not, change the state of the syndrome. (¶¶ [0013], [0026], [0036]-[0038]; responsive to the multi-bit error (MBE) signal being active, an MBE flag in a mode register 132 may be set. The mapped states are those the ECC circuit 120 is capable of interpreting as single bit error locations (or no errors) and correcting (if needed); Abstract, ¶¶ [0012], [0025], [0027]. The ECC circuit 208 may use the read parity bits and the read data bits to generate syndrome bits. The syndrome bits may in turn be used to locate and correct a single bit error in the read data, ¶ [0035]).
Claim 6:
Geiger teaches the ECC circuit comprises an error locator circuit configured to change a state of one of the subset of the plurality of data bits based on the changed syndrome. (¶¶ [0012], [0024], [0035], [0042], [0046], claim 20; locate errors).
Claim 7:
Geiger teaches the subset of the plurality of data bits is in a portion of the plurality of data bits which is selected by a column plane select bit of a column address. (¶ [0021]: read data is read from memory cells in the memory array corresponding to a row address and a column address).
Claim 13:
Geiger teaches a method comprising:
reading a plurality of data bits and a plurality of parity bits from a memory device on a module (see claim 24);
generating a plurality of syndrome bits based on the plurality of data bits and the plurality of parity bits (see claim 24);
determining if the plurality of syndrome bits indicates an uncorrectable error (multi-bit errors, 2 or more bits are in error, MBE) (¶ [0027]).
Geiger does not explicitly teach “aliasing one of a subset of the plurality of data bits if the plurality of syndrome bits indicate an uncorrectable error”. However, HALBERT teaches in an analogous art Single error correction (SEC) codes can detect and correct single bit errors but will not correct double bit errors. Aliasing a bit error can refer to the ECC process of selecting a correct bit to invert in an ECC operation based on ECC computations. (¶¶ [0023]-[0025], [0042], [0045], [0063]). It would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to add HALBERT’s aliasing capabilities to Geiger’s ECC circuit and multibit error (MBE) detection logic 210. The artisan would be motivated to do so because it would enable Geiger to expand the types of errors that can be corrected.
Claim 14:
Geiger teaches determining if the plurality of syndrome bits indicates a correctable error; and correcting the error in the plurality of data bits. (¶¶ [0012], [0027], [0035], [0044], mapped states of the syndrome bits may be used to detect and correct the bit error in the data; the mapped state of the syndrome bits is the ECC circuit capable of correcting the bit error).
Claim 15:
Geiger teaches determining the uncorrectable error based on a non-zero syndrome state which is not associated with one of the plurality of data bits or one of the plurality of parity bits. (¶ [0027], the unmapped states of the syndrome bits represent uncorrectable errors).
Claim 16:
Geiger in view of HALBERT teaches aliasing a bit in a specified range of burst bits, a specified data terminal, or combinations thereof. (HALBERT: Single error correction (SEC) codes can detect and correct single bit errors but will not correct double bit errors. Aliasing a bit error can refer to the ECC process of selecting a correct bit to invert in an ECC operation based on ECC computations. (¶¶ [0023]-[0025], [0042], [0045], [0063]).
Claim 17:
Geiger in view of HALBERT teaches enabling the aliasing of the one of the subset of the plurality of data bits based on a module error correction setting. (Geiger, ¶ [0036]: responsive to the MBE, the logic may set an MBE flag in the mode register; if the MBE flag is high, a controller takes various corrective actions to mitigate data corruption) and HALBERT, (¶¶ [0023]-[0025], [0042], [0045], [0063]: the SEC codes can detect and correct the single bit errors but will not correct the double bit (two bits) errors; the two bit errors may be aliased; the aliased bit will not cause errors).
Claim 19:
Geiger teaches the plurality of syndrome bits if the plurality of syndrome bits indicates an uncorrectable error. (A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated, Abstract. The unmapped states represent errors (such as MBEs) which are uncorrectable by the ECC circuit 120, ¶ [0027]).
Geiger does not explicitly teach “aliasing the one of the subset of the plurality of data bits with an error correction circuit based on the changed plurality of syndrome bits”. However, HALBERT teaches in an analogous art Single error correction (SEC) codes can detect and correct single bit errors but will not correct double bit errors. Aliasing a bit error can refer to the ECC process of selecting a correct bit to invert in an ECC operation based on ECC computations. (¶¶ [0023]-[0025], [0042], [0045], [0063]). It would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to add HALBERT’s aliasing capabilities to Geiger’s ECC circuit and multibit error (MBE) detection logic 210. The artisan would be motivated to do so because it would enable Geiger to expand the types of errors that can be corrected.
Claim 20:
Geiger teaches changing a portion of the plurality of syndrome bits which indicates a burst bit location (¶ [0060]: data may be organized into bursts).
Claims 2 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Geiger et al. (US-20220399902), hereinafter Geiger, in view of HALBERT et al. (US-20180203761), hereinafter HALBERT, in further view of Schaefer et al. (US-20220066867), hereinafter Schaefer.
Claim 2:
Geiger in view of HALBERT does not explicitly teach “the module error correction setting is set based on a type of a controller coupled to the apparatus”. However, Schaefer teaches in an analogous art [t]he memory controller 340 may determine which type of error correction procedure is enabled (e.g., SEC or SECDED), if programmable. In some cases, the memory controller 340 may identify the type of error correction procedure based on an indication received from the host device 305. For example, the host device 305 may cause a value in a register 370 (e.g., a mode register) to be set to indicate the type of error correction procedure (e.g., the host device 305 may set the register 370 to a logic value ‘0’ to indicate SEC and a logic value ‘1’ to indicate SECDED). (¶ [0076]). It would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the controller of Geiger in view of HALBERT to utilize Schaefer’s memory controller 340. The artisan would be motivated to do so because it would further enhance the controller of Geiger in view of HALBERT to identify the type of error correction procedure based on set in the mode register.
Claim 18:
Geiger in view of HALBERT does not explicitly teach “setting the module error correction setting based on an error correction scheme of a controller coupled to the module”. However, Schaefer teaches in an analogous art [t]he memory controller 340 may determine which type of error correction procedure is enabled (e.g., SEC or SECDED), if programmable. In some cases, the memory controller 340 may identify the type of error correction procedure based on an indication received from the host device 305. For example, the host device 305 may cause a value in a register 370 (e.g., a mode register) to be set to indicate the type of error correction procedure (e.g., the host device 305 may set the register 370 to a logic value ‘0’ to indicate SEC and a logic value ‘1’ to indicate SECDED). (¶ [0076]). It would have been obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to modify the controller of Geiger in view of HALBERT to utilize Schaefer’s memory controller 340. The artisan would be motivated to do so because it would further enhance the controller of Geiger in view of HALBERT to identify the type of error correction procedure based on set in the mode register.
Allowable Subject Matter
Claims 8-12 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. PAE et al. (Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement, February 25, 2021, IEEE, pp. 29862- 29869.) teaches We discuss the problem of finding a minimal aliasing code among a class of systematic single-error-correction codes that are suitable to be implemented within DRAM die, as opposed to external ECC used in memory controller outside of DRAM chip. We prove a sharp lower bound of aliasing probability propose a simple method to come up with a code that meets the bound. By an experiment, we also demonstrate that a randomly chosen code is likely to have much more aliasings with overwhelmingly high probability.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN J TABONE JR whose telephone number is (571)272-3827. The examiner can normally be reached M-F 9 AM to 7 PM EST.
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/JOHN J TABONE JR/Primary Examiner, Art Unit 2111 04/30/2026
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