DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3, 4, 7, 11, 12, 13, 16, 23, and 25 have been amended as per Applicant’s amendment filed on January 9, 2026. No claims have been canceled. Claims 1-28 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11, 12 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Shin (US 2022/0399529 A1, Published December 15, 2022).
As to claim 1, Shin discloses a pixel circuit, comprising:
a first light-emitting element (Shin at Fig. 12, OLED1);
a second light-emitting element (Shin at Fig. 12, OLED2);
a driving element configured to drive the first and second light-emitting elements (Shin at Fig. 12, transistor Tdr);
a first switch element connected between the driving element and the first light-emitting element (Shin at Fig. 12, transistor T4);
a second switch element connected between the driving element and the second light-emitting element (Shin at Fig. 12, transistor T6); and
a compensation circuit, including: a capacitor connected to a gate electrode of the driving element (Shin at Fig. 12, storage capacitor Cst);
a third switch element directly connected between a voltage line to which a reference voltage is for being applied and one electrode of the capacitor (Shin at Fig. 12, transistor T3 is connected between Vref (analogous to a reference voltage) and node P1 (an electrode of capacitor Cst));
a fourth switch element directly connected between a first node to which an anode electrode of the first light-emitting element is connected and an initialization voltage line to which an initialization voltage is for being applied (Shin at Fig. 12, transistor T5 is connected between anode of OLED1 and Vref. Examiner regards the line that connects Vref to transistor T5 as analogous to an initialization voltage line); and
a fifth switch directly connected element connected between a second node to which an anode electrode of the second light-emitting element is connected and the initialization voltage line (Shin at Fig. 12, transistor T7 is connected between anode of OLED2 and Vref (Examiner regards Vref as analogous to an initialization voltage)).
In the alternative, and in the event that it is found that the voltage line for the reference voltage is different from the voltage line for the initialization voltage, then Examiner submits that MPEP 2144.04(V) establishes that making separable is obvious. Thus, it would be obvious to a person ordinary skill to separate Vref of Shin at Fig. 12 into two separate voltage lines.
As to claim 11, Shin discloses a display device, comprising:
a pixel array in which a plurality of data lines, a plurality of gate lines, and… a plurality of pixel circuits are disposed (Shin at Fig. 1);
a data driver configured to output data voltages to the plurality of data lines (Shin at Fig. 1, data driver 30); and
a gate driver configured to output gate signals to the plurality of gate lines (Shin at Fig. 1, gate driver 20),
wherein each of the plurality of pixel circuits includes: a first light-emitting element (Shin at Fig. 12, OLED1);
a second light-emitting element (Shin at Fig. 12, OLED2);
a driving element configured to drive the first and second light-emitting elements (Shin at Fig. 12, transistor Tdr);
a first switch element connected between the driving element and the first light-emitting element (Shin at Fig. 12, transistor T4);
a second switch element connected between the driving element and the second light-emitting element (Shin at Fig. 12, transistor T6); and
a compensation circuit, including: a capacitor connected to a gate electrode of the driving element (Shin at Fig. 12, storage capacitor Cst);
a third switch element directly connected between a voltage line to which a reference voltage is for being applied and one electrode of the capacitor (Shin at Fig. 12, transistor T3 is connected between Vref (analogous to a reference voltage) and node P1 (an electrode of capacitor Cst));
a fourth switch element directly connected between a first node to which an anode electrode of the first light-emitting element is connected and an initialization voltage line to which an initialization voltage is for being applied (Shin at Fig. 12, transistor T5 is connected between anode of OLED1 and Vref. Examiner regards the line that connects the Vref to transistor T5 as analogous to an initialization voltage line); and
a fifth switch element directly connected between a second node to which an anode electrode of the second light-emitting element is connected and the initialization voltage line Shin at Fig. 12, transistor T7 is connected between anode of OLED2 and Vref (Examiner regards Vref as analogous to the initialization voltage)).
In the alternative, and in the event that it is found that the voltage line for the reference voltage is different from the voltage line for the initialization voltage, then Examiner submits that MPEP 2144.04(V) establishes that making separable is obvious. Additionally, in the event that it is found that Shin does not contemplate a plurality of voltage lines, then Examiner submits that MPEP 2144.04(VI) establishes that duplication of parts is obvious.1 Thus, it would be obvious to a person ordinary skill to separate Vref of Shin at Fig. 12 into two separate voltage lines.
As to claim 22, Shin discloses the display device of claim 11, wherein: the first light-emitting element is configured to emit light with a first viewing angle; the second light-emitting element is configured to emit light with a second viewing angle; and the second viewing angle is wider than the first viewing angle (Shin at Fig. 11).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Shin (US 2022/0399529 A1, Published December 15, 2022) in view of Cha (US 2021/0066430 A1, Published March 4, 2021).
As to claim 25, Shin discloses the display device of claim 11.
Shin does not expressly disclose that the plurality of voltage lines include an initialization voltage line to which an initialization voltage is for being applied; wherein the initialization voltage line includes: a first voltage line which is disposed in a non-display area surrounding a display area for displaying an image and which is configured to receive the initialization voltage from a power supply; and a plurality of second voltage lines which are disposed in the display area, which are branched from the first voltage line, and which are configured to supply the initialization voltage to the plurality of sub-pixels.
However, Cha does disclose that the plurality of voltage lines include an initialization voltage line to which an initialization voltage is for being applied (Cha at Figs. 4-5, first and second initialization power supply lines 181, 182; MPEP 2144.04(V, IV)), and
wherein the initialization voltage line includes: a first voltage line which is disposed in a non-display area surrounding a display area for displaying an image and which is configured to receive the initialization voltage from a power supply (Cha at Figs. 4-5, first and second initialization voltage power supply lines 181, 182 are in non-display area NDA2; ¶ [0109]); and
a plurality of second voltage lines which are disposed in the display area, which are branched from the first voltage line, and which are configured to supply the initialization voltage to the plurality of sub-pixels (Cha at Figs. 4-5, initialization voltage lines VL; ¶ [0097]).
Shin discloses a base display device upon which the claimed invention is an improvement. Cha discloses a comparable display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Shin the teachings of Cha for the predictable result of increasing functions that may be combined or associated with a display device (Cha at ¶ [0006]).
Claims 2 are rejected under 35 U.S.C. 103 as being unpatentable over Shin (US 2022/0399529 A1, Published December 15, 2022) in view of Kim (US 2013/0162620 A1, Published June 27, 2013).
As to claim 2, Shin discloses the pixel circuit of claim 1.
Shin does not disclose that the initialization voltage is set to be lower than the reference voltage.
However, Kim does disclose that the initialization voltage is set to be lower than the reference voltage (Kim at Fig. 2, in particular; ¶ [0011], [0036] discloses “The voltages are set such that the initialization voltage Vinit is lower than the reference voltage Vref”).
Shin discloses a base OLED display device upon which the claimed invention is an improvement. Kim discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Shin the teachings of Kim for the predictable result of minimizing a current driving capability deviation to thereby achieve enhancement in picture quality (Kim at ¶ [0008]).
Claims 20, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Shin (US 2022/0399529 A1, Published December 15, 2022) in view of Kim2 (US 2024/0107812 A1, Filed July 25, 2023).
As to claim 20, Shin discloses the display device of claim 11, wherein the initialization voltage line includes: a first-first initialization voltage line; a first-second initialization voltage line; a second-first initialization voltage line; and a second-second initialization voltage line (Shin at Figs. 2A, 11, 12, in particular), and
wherein: the first-first initialization voltage line is configured to apply a first-first initialization voltage to an anode electrode of a first light-emitting element included in a pixel circuit of a red sub-pixel (Shin at Fig. 2A, 11, 12, application of Vref applied to OLED1 of red subpixel 1SP1-1. An initialization voltage line from Vref to the red sub-pixel 1SP1-1 anode is necessarily present);
the first-second initialization voltage line is configured to apply a first-second initialization voltage to anode electrodes of first light-emitting elements included in pixel circuits of green and blue sub-pixels (Shin at Figs. 2A, 11, 12, application of Vref applied to OLED1 of green subpixel 1SP2-1 and to OLED1 of blue subpixel 1SP3-1. Respective initialization voltage lines from Vref to the green sub-pixel 1SP2-1 anode and to the blue sub-pixel 1SP3-1 anode is necessarily present);
the second-first initialization voltage line is configured to apply a second-first initialization voltage to an anode electrode of a second light-emitting element included in the pixel circuit of the red sub-pixel (Shin at Fig. 2A, 11, 12, application of Vref applied to OLED2 of red subpixel 2SP1-1. An initialization voltage line from Vref to the red sub-pixel 2SP1-1 anode is necessarily present); and
the second-second initialization voltage line is configured to apply a second-second initialization voltage to anode electrodes of second light-emitting elements included in the pixel circuits of the green and blue sub-pixels (Shin at Figs. 2A, 11, 12, application of Vref applied to OLED2 of green subpixel 2SP2-1 and to OLED1 of blue subpixel 2SP3-1. Respective initialization voltage lines from Vref to the green sub-pixel 2SP2-1 anode and to the blue sub-pixel 2SP3-1 anode is necessarily present).
Shin does not disclose a single initialization voltage line for one green sub-pixel and one blue sub-pixel.
However, Kim2 does teach a single initialization voltage line for one green sub-pixel and one blue sub-pixel (Kim2 at Fig. 3; ¶ [0095] discloses “Here, the initialization voltage lines 128g and 128rb include an initialization voltage line 128g for a green pixel and an initialization voltage line 128rb for a red or blue pixel as separate wires. The initialization voltage lines 128g and 128rb may apply different initialization voltages, and the initialization voltage for the green pixel and the initialization voltage for the red or blue pixel may have different voltage level.” Claim 7. Examiner regards the color choice of one green and one blue as a design choice).2
Shin discloses a base OLED display device upon which the claimed invention is an improvement. Kim2 discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Shin the teachings of Kim2 for the predictable result of preventing display quality deterioration (Kim at ¶ [0029]-[0030]).
As to claim 21, the combination of Shin and Kim discloses the display device of claim 20, wherein: the second-first initialization voltage is set to be higher than the first-first initialization voltage; the first-second initialization voltage is set to be higher than the second-first initialization voltage; and the second-second initialization voltage is set to be higher than the first-second initialization voltage (Kim at ¶ [0095]).
Claims 26, 27, 28 are rejected under 35 U.S.C. 103 as being unpatentable over Shin and Cha as applied to claim 25 above, and in further view of Lee (US 2014/0176399 A1, Published June 26, 2014).
As to claim 26, the combination of Shin and Cha discloses the display device of claim 25, wherein the plurality of second voltage lines include: a plurality of second-first voltage lines branched from a part of the first voltage line, wherein the plurality of second-first voltage lines are disposed in a first axial direction, and wherein each of the plurality of second-first voltage lines is configured to supply the initialization voltage to one or more corresponding sub-pixels of the plurality of sub-pixels (Cha at Fig. 4, 6, initialization voltage lines VL).
While Cha does disclose a plurality of second-second voltage lines branched from a part of the first voltage line (Cha at Fig. 4, initialization voltage lines VL), Cha does not expressly disclose that the plurality of second-second voltage lines are disposed in a second axial direction perpendicular to the first axial direction.
However, Lee does a plurality of second-second voltage lines branched from a part of the first voltage line, wherein the plurality of second-second voltage lines are disposed in a second axial direction perpendicular to the first axial direction (Lee at Fig. 3, VINI connection to auxiliary electrode PE3 and VINIVLq; ¶ [0036]).
The combination of Shin and Cha discloses a base OLED display device upon which the claimed invention is an improvement. Lee discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of Shin and Cha the teachings of Lee for the predictable result of minimizing the possibility of short-circuit of power lines (Lee at ¶ [0058]).
As to claim 27, the combination of Shin, Cha and Lee discloses the display device of claim 26, wherein each of the plurality of second-second voltage lines connects two parts of the first voltage line respectively disposed in the second axial direction (Lee at Fig. 3. MPEP 2144.04(IV) establishes that changes in shape/configuration are obvious).
Cha discloses a base OLED display device upon which the claimed invention is an improvement. Lee discloses a comparable OLED display device which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Cha the teachings of Lee for the predictable result of minimizing the possibility of short-circuit of power lines (Lee at ¶ [0058]).
As to claim 28, the combination of Shin, Cha and Lee discloses the display device of claim 25, wherein each of the plurality of second voltage lines has a width smaller than a width of the first voltage line and has a thickness smaller than a thickness of the first voltage line (Cha at Figs 4-5. Examiner takes an official notice that the electrical resistance (e.g. sheet resistivity) or current carrying capacity through a material, such as metal or alloy, is a function of the physical dimensions of the material. In view of the officially noticed facts, it would be obvious to a person of ordinary skill to adjust the width and thickness of the first and second voltage lines for the well-known purpose of minimizing the amount of material used while also minimizing the effect of current-resistance (i.e. IR) voltage drop).
Response to Arguments
Applicant's arguments filed claims 1-28 have been fully considered but they are not persuasive.
Applicant contends that the Shin reference does not disclose the features in amended claim 1 (Applicant’s Remarks (AR) at page 15). Examiner respectfully disagrees for the reasons given above in the substantive rejection of the claims.
Allowable Subject Matter
Claims 3-10, 12-19, 23, and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all elements of the objected to claim and all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 3, none of the prior art found by the Examiner discloses the claimed aspects of: wherein a first repair capacitor is formed between the initialization voltage line and the first node, and a second repair capacitor is formed between the initialization voltage line and the second node.
As to claim 12, none of the prior art found by the Examiner discloses the claimed aspects of: wherein a first repair capacitor is formed between the initialization voltage line and the first node, and a second repair capacitor is formed between the initialization voltage line and a second node.
As to claim 23, Shin discloses the display device of claim 11, wherein each of the plurality of pixel circuits further includes: a selection switch element connected to a mode line to which a mode selection signal is for being applied and respective gate electrodes of the first and second switch elements; and a second capacitor connected between the selection switch element and a power line, and wherein the selection switch element is configured to apply the mode selection signal to the respective gate electrodes of the first and second switch elements (Shin at Fig. 12-13, EM2 or EM3)
However, none of the prior art found by the Examiner discloses the bolded and italicized claim language in claim 23.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang (US 2024/0221590 A1, Filed on May 24, 2021) is a made of record for its relevance to claim 20 by its disclosures in Figs. 3-5 and ¶ [0083]:
“[0083] A gate of the second initialization transistor T7 is electrically connected to a scanning signal line GA, a first electrode of a second initialization transistor T7 in a driving circuit corresponding to the first subpixel (green subpixel G) is electrically connected to the first initialization voltage line VIN1, first electrodes of second initialization transistors in driving circuits corresponding to the second subpixel (red subpixel R) and the third subpixel (blue subpixel B) are each electrically connected to the second initialization voltage line VIN2, and a second electrode of the second initialization transistor T7 is electrically connected to an anode of the light-emitting device L.”
Kwak (US 2009/0039355 A1, Published February 12, 2009) in view of Kwak2 (US 2006/0125737 A1, Published June 15, 2006) are made of record for their relevance to claim 1 by their disclosure of the following:
As to claim 1, Kwak discloses a pixel circuit, comprising:
a first light-emitting element (Kwak at Fig. 3, OLEDr);
a second light-emitting element (Kwak at Fig. 3, OLEDg);
a driving element configured to drive the first and second light-emitting elements (Kwak at Fig. 3, transistor M1);
a first switch element connected between the driving element and the first light-emitting element (Kwak at Fig. 3, transistor M2r);
a second switch element connected between the driving element and the second light-emitting element (Kwak at Fig. 3, transistor M2g); and
a compensation circuit, including: a capacitor connected to a gate electrode of the driving element (Kwak at Fig. 3, capacitor Cvth);
a third switch element configured to apply a reference voltage to one electrode of the capacitor (Kwak at Fig. 3, transistor M4).
Kwak does not disclose a fourth switch element connected between the first light-emitting element and an initialization voltage line to which an initialization voltage is for being applied; and a fifth switch element connected to the second light-emitting element and the initialization voltage line.
However, Kwak2 does disclose a fourth switch element connected between the first light-emitting element and an initialization voltage line to which an initialization voltage is for being applied (Kwak2 at Fig. 5, transistor Maa1. Examiner regards reverse bias line NB as analogous to an initialization voltage line); and
a fifth switch element connected to the second light-emitting element and the initialization voltage line (Kwak2 at Fig. 5, transistor Mba1. Examiner regards reverse bias line NB as analogous to an initialization voltage line).
Kwak discloses a base display OLED pixel upon which the claimed invention is an improvement. Kwak2 discloses a comparable display OLED pixel which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kwak the teachings of Kwak2 for the predictable result of to improving the characteristics of the OLED, and/or in which a plurality of OLEDs are connected to one pixel circuit to reduce the number of pixel circuits of a light emitting display, or alternatively, improving the aperture ratio of the light emitting display (Kwak2 at ¶ [0022]).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sanjiv D Patel whose telephone number is (571)270-5731. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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/Sanjiv D. Patel/Primary Examiner, Art Unit 2625
01/18/2026
1 See also Cha at Figs 1, 4; ¶ [0109].
2 See also Wang in Conclusion Section below.