DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 6 and 20 are objected to because of the following informalities:
For claim 6, Examiner believes this claim should be amended in the following manner:
The apparatus of claim 5, wherein to mark [[of]] each of the set of registers at the GPU based on the uniformity of each of the set of registers at the GPU, the at least one processor is configured to:
provide an indication of the uniformity of each of the set of registers at the GPU; or
store the indication of the uniformity of each of the set of registers at the GPU.
For claim 20, Examiner believes this claim should be amended in the following manner:
A computer-readable medium storing computer executable code for graphics processing, the computer executable code when executed by at least one processor causes the at least one processor to:
obtain an indication of a set of registers at a graphics processing unit (GPU);
identify a classification of each of the set of registers at the GPU, wherein the classification of each of the set of registers at the GPU is associated with an accessibility of each of the set of registers at the GPU; and
output an indication of the classification of each of the set of registers at the GPU.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 20 rejected under 35 U.S.C. 101 because it encompasses nonstatutory subject matter.
Claim 20 is directed to a “computer-readable medium”. Applicants Specification defines “computer-readable media” to include communication media such as signals and carrier waves. Therefore, the claimed “computer-readable medium” encompasses ineligible subject matter of transitory media such as signals and carrier waves. Therefore, claim 20 is rejected under 35 U.S.C. 101 for encompassing nonstatutory subject matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5-7, 9 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feiste et al. (U.S. Patent Application Publication 2023/0068637 A1, hereinafter “Feiste”) (made of record of the IDS submitted 4/16/2026) in view of Du et al. (U.S. Patent 9,633,411 B2, hereinafter “Du”).
For claim 1, Feiste discloses an apparatus for graphics processing (disclosing an apparatus with a graphics processing unit (GPU) to perform graphics processing (par. 78-82)), comprising: at least one memory (disclosing memory (Fig. 1; par. 25)); and at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory (disclosing a processor coupled to the memory and executed instructions stored in memory to perform the functions of the apparatus (Fig. 1; par. 25)), the at least one processor is configured to: obtain an indication of a set of registers at a graphics processing unit (GPU) (disclosing determination of indications for registers at a processor (par. 43) where the processor may be a GPU (par. 82)); identify a classification of each of the set of registers at the GPU, wherein the classification of each of the set of registers at the GPU is associated with an accessibility of each of the set of registers at the GPU (disclosing the identification of availability with a valid bit field as classification of each register to associate each register as to availability for allocation/use or access at the GPU (par. 43 and 82)); and output an indication of the classification of each of the set of registers at the GPU (disclosing output of information to indicate each register at the GPU as available for use (par. 43)).
Examiner finds Feiste discloses a classification of each register is associated with an accessibility of each register.
In any case, these limitations are well-known in the art as disclosed in Du.
Du similarly discloses a system and method for graphics processing (col. 1/lines 11-24). Du likewise discloses a graphics processing unit comprising a set of registers (col. 2/lines 4-23). Du explains each register is classified as either a general purpose register or a shared general purpose register where a shared general purpose register is accessed differently than a general purpose register so that uniform data is read from the shared general purpose register rather than repeatedly accessing a general purpose register (col. 4/lines 44-57). It follows Feiste may be accordingly modified with the teachings of Du to implement a classification of each of its set of registers to be associated with an accessibility of each of its set of registers.
A person having ordinary skill in the art (PHOSITA) before the effective filing date of the claimed invention would find it obvious to modify Feiste with the teachings of Du. Du is analogous art in dealing with a system and method for graphics processing (col. 1/lines 11-24). Du discloses its classification of registers is advantageous in appropriately reducing the number of times registers need to be accessed to improve power consumption of a GPU (col. 5/lines 22-35). Consequently, a PHOSITA would incorporate the teachings of Du into Feiste for appropriately reducing the number of times registers need to be accessed to improve power consumption of a GPU. Therefore, claim 1 is rendered obvious to a PHOSITA before the effective filing date of the claimed invention.
For claim 2, depending on claim 1, Feiste as modified by Du discloses wherein the at least one processor is further configured to: identify a uniformity of each of the set of registers at the GPU based on the classification of each of the set of registers at the GPU (Du similarly discloses a system and method for graphics processing (col. 1/lines 11-24); Du likewise discloses a graphics processing unit comprising a set of registers (col. 2/lines 4-23); Du explains each register is classified as either a general purpose register or a shared general purpose register where a shared general purpose register is accessed differently than a general purpose register so that uniform data is read from the shared general purpose register rather than repeatedly accessing a general purpose register to identify a uniformity of the registers (col. 4/lines 44-57); and it follows Feiste may be accordingly modified with the teachings of Du to implement a classification of each of its set of registers to be associated with an accessibility of each of its set of registers).
For claim 3, depending on claim 2, Feiste as modified by Du discloses wherein to identify the uniformity of each of the set of registers at the GPU based on the classification of each of the set of registers at the GPU, the at least one processor is configured to: determine whether one of the set of registers at the GPU is replaceable by another of the set of registers at the GPU (Feiste discloses determination of whether an unavailable register at the GPU is replaceable by another register that is available (par. 43 and 82) ; Feiste further discloses a register may be replaced by another register through swapping (par. 69)).
For claim 5, depending on claim 2, Feiste as modified by Du discloses wherein the at least one processor is further configured to: mark each of the set of registers at the GPU based on the uniformity of each of the set of registers at the GPU (Du similarly discloses a system and method for graphics processing (col. 1/lines 11-24); Du likewise discloses a graphics processing unit comprising a set of registers (col. 2/lines 4-23); Du explains each register is classified as either a general purpose register or a shared general purpose register where a shared general purpose register is accessed differently than a general purpose register so that uniform data is read from the shared general purpose register rather than repeatedly accessing a general purpose register to identify a uniformity of the registers (col. 4/lines 44-57); Du further explains a uniform valid flag may be used to mark the uniformity of the shared general purpose register (col. 18/lines 41-53); and it follows Feiste may be accordingly modified with the teachings of Du to implement a classification of each of its set of registers to be associated with an accessibility of each of its set of registers).
For claim 6, depending on claim 5, Feiste as modified by Du discloses wherein to mark of each of the set of registers at the GPU based on the uniformity of each of the set of registers at the GPU, the at least one processor is configured to: provide an indication of the uniformity of each of the set of registers at the GPU; or store the indication of the uniformity of each of the set of registers at the GPU (Du similarly discloses a system and method for graphics processing (col. 1/lines 11-24); Du likewise discloses a graphics processing unit comprising a set of registers (col. 2/lines 4-23); Du explains each register is classified as either a general purpose register or a shared general purpose register where a shared general purpose register is accessed differently than a general purpose register so that uniform data is read from the shared general purpose register rather than repeatedly accessing a general purpose register to identify a uniformity of the registers (col. 4/lines 44-57); Du further explains a uniform valid flag may be used to provide an indication of the uniformity of the shared general purpose register where the flag is stored in memory (col. 18/lines 41-53); and it follows Feiste may be accordingly modified with the teachings of Du to implement a classification of each of its set of registers to be associated with an accessibility of each of its set of registers).
For claim 7, depending on claim 5, Feiste as modified by Du discloses wherein the at least one processor is further configured to: refrain from executing a set of instructions associated with at least one register of the set of registers at the GPU based on the marking (Du similarly discloses a system and method for graphics processing (col. 1/lines 11-24); Du likewise discloses a graphics processing unit comprising a set of registers (col. 2/lines 4-23); Du explains each register is classified as either a general purpose register or a shared general purpose register where a shared general purpose register is accessed differently than a general purpose register so that uniform data is read from the shared general purpose register rather than repeatedly accessing a general purpose register to identify a uniformity of the registers (col. 4/lines 44-57); Du further explains a uniform valid flag may be used to provide an indication of the uniformity of the shared general purpose register where the flag is stored in memory (col. 18/lines 41-53); Du explains instructions for reading uniform data are refrained from execution on the general purpose register and are performed instead for the shared general purpose register to read the uniform data based on the uniform valid flag (col. 4/lines 44-57 and col. 18/lines 41-53); and it follows Feiste may be accordingly modified with the teachings of Du to implement a classification of each of its set of registers to be associated with an accessibility of each of its set of registers).
For claim 9, depending on claim 1, Feiste as modified by Du discloses wherein to identify the classification of each of the set of registers at the GPU, the at least one processor is configured to: determine, during a shader compilation at the GPU, the classification of each of the set of registers at the GPU (Du similarly discloses a system and method for graphics processing (col. 1/lines 11-24); Du likewise discloses a graphics processing unit comprising a set of registers (col. 2/lines 4-23); Du explains each register is classified as either a general purpose register or a shared general purpose register where a shared general purpose register is accessed differently than a general purpose register so that uniform data is read from the shared general purpose register rather than repeatedly accessing a general purpose register to identify a uniformity of the registers (col. 4/lines 44-57); Du further explains the classification of the registers is determined during an execution of a compiler of a shader program as a shader compilation at the graphics processing unit (col. 4/lines 63-67 and col. 5/lines 1-6); and it follows Feiste may be accordingly modified with the teachings of Du to implement a classification of each of its set of registers to be associated with an accessibility of each of its set of registers).
For claim 15, depending on claim 1, Feiste as modified by Du discloses wherein to identify the classification of each of the set of registers at the GPU, the at least one processor is configured to: determine, at a compiler of a central processing unit (CPU) or a processor of the CPU, the classification of each of the set of registers at the GPU (Du similarly discloses a system and method for graphics processing (col. 1/lines 11-24); Du likewise discloses a graphics processing unit comprising a set of registers (col. 2/lines 4-23); Du explains each register is classified as either a general purpose register or a shared general purpose register where a shared general purpose register is accessed differently than a general purpose register so that uniform data is read from the shared general purpose register rather than repeatedly accessing a general purpose register to identify a uniformity of the registers (col. 4/lines 44-57); Du discloses the classification is determined at a compiler of a central processing unit (col. 4/lines 63-67 and col. 5/lines 1-6; and col. 6/lines 4-18); and it follows Feiste may be accordingly modified with the teachings of Du to implement a classification of each of its set of registers to be associated with an accessibility of each of its set of registers).
For claim 16, depending on claim 1, Feiste as modified by Du discloses wherein the set of registers is a set of general purpose registers (GPRs) at the GPU, a set of graphics memories at the GPU, or a set of memories at the GPU (Du similarly discloses a system and method for graphics processing (col. 1/lines 11-24); Du likewise discloses a graphics processing unit comprising a set of registers (col. 2/lines 4-23); Du explains each register is classified as either a general purpose register or a shared general purpose register where a shared general purpose register is accessed differently than a general purpose register so that uniform data is read from the shared general purpose register rather than repeatedly accessing a general purpose register to identify a uniformity of the registers (col. 4/lines 44-57); and it follows Feiste may be accordingly modified with the teachings of Du to implement a classification of each of its set of registers to be associated with an accessibility of each of its set of registers).
For claim 17, depending on claim 1, Feiste as modified by Du discloses wherein the set of registers at the GPU is associated with at least one of: a shader compilation at the GPU, shader processing at the GPU, or post-processing at the GPU (Du similarly discloses a system and method for graphics processing (col. 1/lines 11-24); Du likewise discloses a graphics processing unit comprising a set of registers (col. 2/lines 4-23); Du explains each register is classified as either a general purpose register or a shared general purpose register where a shared general purpose register is accessed differently than a general purpose register so that uniform data is read from the shared general purpose register rather than repeatedly accessing a general purpose register to identify a uniformity of the registers (col. 4/lines 44-57); Du further explains the classification of the registers is determined during an execution of a compiler of a shader program as a shader compilation at the graphics processing unit (col. 4/lines 63-67 and col. 5/lines 1-6); and it follows Feiste may be accordingly modified with the teachings of Du to implement a classification of each of its set of registers to be associated with an accessibility of each of its set of registers).
For claim 18, depending on claim 1, Feiste as modified by Du discloses wherein to obtain the indication of the set of registers at the GPU, the at least one processor is configured to: receive, from the GPU, the indication of the set of registers at the GPU (Du similarly discloses a system and method for graphics processing (col. 1/lines 11-24); Du likewise discloses a graphics processing unit comprising a set of registers (col. 2/lines 4-23); Du explains each register is classified as either a general purpose register or a shared general purpose register where a shared general purpose register is accessed differently than a general purpose register so that uniform data is read from the shared general purpose register rather than repeatedly accessing a general purpose register to identify a uniformity of the registers (col. 4/lines 44-57); Du further explains a uniform valid flag may be used to provide an indication of the uniformity of the shared general purpose register from the GPU to the processor (col. 4/lines 63-67 and col. 5/lines 1-6; col. 6/lines 4-18; and col. 18/lines 41-53); and it follows Feiste may be accordingly modified with the teachings of Du to implement a classification of each of its set of registers to be associated with an accessibility of each of its set of registers and so that its processor is configured to receive the indication of its set of registers from its GPU).
For claim 19, Feiste as modified by Du discloses a method comprising steps corresponding to the functions performed by the apparatus of claim 1 (see above as to claim 1).
For claim 20, Feiste as modified by Du discloses computer-readable medium storing computer executable code, the code when executed by at least one processor (Feiste discloses a memory for storing instructions as computer executable code for execution by a processor to perform the functions of the apparatus (Fig. 1; par. 25)) causes the at least one processor to perform the functions performed by the apparatus of claim 1 (see above as to claim 1).
Claim(s) 4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feiste in view of Du further in view of Ray et al. (U.S. Patent Application Publication 2023/0102538 A1, hereinafter “Ray”).
For claim 4, depending on claim 3, Feiste as modified by Du does not disclose a register including a vector classification and a register including a scalar classification.
However, these limitations are well-known in the art as disclosed in Ray.
Ray similarly discloses a system and method for managing registers in a graphics processing unit (par. 75). Ray explains the registers may include vector registers as registers including a vector classification and scalar registers as registers including a scalar classification (par. 253). Ray further explains a register may be replaced with another register (par. 385). It follows Feiste and Du may be accordingly modified with the teachings of Ray to implement registers including a vector classification and a scalar classification where such registers are replaceable with one another.
A PHOSITA before the effective filing date of the claimed invention would find it obvious to modify Feiste and Du with the teachings of Ray. Ray is analogous art in dealing with a system and method for managing registers in a graphics processing unit (par. 75). Ray discloses its use of vector registers and scalar registers is advantageous in processing vector data and scalar data to appropriate carry out functions of a graphics processing unit (par. 253). Consequently, a PHOSITA would incorporate the teachings of Ray into Feiste and Du for processing vector data and scalar data to appropriate carry out functions of a graphics processing unit. Therefore, claim 4 is rendered obvious to a PHOSITA before the effective filing date of the claimed invention.
For claim 13, depending on claim 1, Feiste as modified by Du and Ray discloses wherein to identify the classification of each of the set of registers at the GPU, the at least one processor is configured to: determine whether the classification of each of the set of registers is one of: a scalar classification, a vector classification, an unknown classification, or a conditional classification (Ray similarly discloses a system and method for managing registers in a graphics processing unit (par. 75); Ray explains the registers may include vector registers as registers including a vector classification and scalar registers as registers including a scalar classification (par. 253); Ray further explains a register may be replaced with another register (par. 385); and it follows Feiste and Du may be accordingly modified with the teachings of Ray to implement registers including a vector classification and a scalar classification where such registers are replaceable with one another).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feiste in view of Du further in view of Vishwesh et al, Greeener: A Tool for Improving Energy Efficiency of Register Files, arXiv, September 2017 (hereinafter “Vishwesh”) (made of record of the IDS submitted 4/16/2026).
For claim 8, depending on claim 1, Feiste as modified by Du does not disclose performing an analysis of paths for a register.
However, these limitations are well-known in the art as disclosed in Vishwesh.
Vishwesh similarly discloses a system and method for managing registers in a graphics processing unit (page 1). Vishwesh explains its system performs an analysis of paths for a register to determine a state for classifying a register (pages 5-6). It follows Feiste and Du may be accordingly modified with the teachings of Vishwesh to adjust classification of at least on register of its set of registers based on a set of paths.
A PHOSITA before the effective filing date of the claimed invention would find it obvious to modify Feiste and Du with the teachings of Vishwesh. Vishwesh is analogous art in dealing with a system and method for managing registers in a graphics processing unit (page 1). Vishwesh discloses its use of path analysis is advantageous in managing states of registers to reduce power consumption in a graphics processing unit (pages 1 and 5-6). Consequently, a PHOSITA would incorporate the teachings of Vishwesh into Feiste and Du for managing states of registers to reduce power consumption in a graphics processing unit. Therefore, claim 8 is rendered obvious to a PHOSITA before the effective filing date of the claimed invention.
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feiste in view of Du further in view of Surti et al. (U.S. Patent Application Publication 2016/0284119 A1, hereinafter “Surti”).
For claim 10, depending on claim 9, Feiste as modified by Du does not disclose a later stage of a plurality of stages in a shader compilation.
However, these limitations are well-known in the art as disclosed in Surti.
Surti similarly discloses a system and method for managing registers in a graphics processing unit (par. 5 and 112). Surti likewise discloses its system performs a shader compilation for the graphics processing unit (par. 56 and 186). Surti explains the shader compilation determines a plurality of stages including a last shading stage as a later stage of the plurality of shading stages (par. 56-58). It follows Feiste and Du may be accordingly modified with the teachings of Surti to determine a later stage of a plurality of stages in its shader compilation for determining its classification of its set of registers .
A PHOSITA before the effective filing date of the claimed invention would find it obvious to modify Feiste and Du with the teachings of Surti. Surti is analogous art in dealing with a system and method for managing registers in a graphics processing unit (par. 5 and 112). Surti discloses its determination of shader stages is advantageous in managing a graphics processing unit to appropriately process graphics data (par. 98). Consequently, a PHOSITA would incorporate the teachings of Surti into Feiste and Du for managing a graphics processing unit to appropriately process graphics data. Therefore, claim 10 is rendered obvious to a PHOSITA before the effective filing date of the claimed invention.
For claim 11, depending on claim 10, Feiste as modified by Du discloses wherein to determine, during the later stage of the plurality of stages in the shader compilation at the GPU, the classification of each of the set of registers at the GPU, the at least one processor is configured to: determine, during a last stage of the plurality of stages in the shader compilation at the GPU, the classification of each of the set of registers at the GPU (Surti similarly discloses a system and method for managing registers in a graphics processing unit (par. 5 and 112); Surti likewise discloses its system performs a shader compilation for the graphics processing unit (par. 56 and 186); Surti explains the shader compilation determines a plurality of stages including a last shading stage as a later stage of the plurality of shading stages (par. 56-58); and it follows Feiste and Du may be accordingly modified with the teachings of Surti to determine a last stage of a plurality of stages in its shader compilation for determining its classification of its set of registers).
For claim 12, depending on claim 10, Feiste as modified by Du discloses wherein to determine, during the later stage of the plurality of stages in the shader compilation at the GPU, the classification of each of the set of registers at the GPU, the at least one processor is configured to: refrain from determining, during an early stage of the plurality of stages in the shader compilation at the GPU, the classification of each of the set of registers at the GPU; and determine, during the later stage of the shader compilation at the GPU, the classification of each of the set of registers at the GPU, wherein the early stage is prior to the later stage in the plurality of stages in the shader compilation (Surti similarly discloses a system and method for managing registers in a graphics processing unit (par. 5 and 112); Surti likewise discloses its system performs a shader compilation for the graphics processing unit (par. 56 and 186); Surti explains the shader compilation determines a plurality of stages including a last shading stage as a later stage of the plurality of shading stages where certain processing is only performed at the last shading stage (par. 56-58); and it follows Feiste and Du may be accordingly modified with the teachings of Surti to determine a last stage of a plurality of stages in its shader compilation for determining its classification of its set of registers where the classification is refrained from being performed at an earlier stage prior to the last stage of its shader compilation).
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES TSENG whose telephone number is (571)270-3857. The examiner can normally be reached 8-5.
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/CHARLES TSENG/Primary Examiner, Art Unit 2613
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