Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 - 4, 12, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Molina et al. (EP 3716486) in view of Speir et al. (US Patent Number 9,503,116).
Regarding claims 1, 12, Molina et al. disclose a circuit and method comprising:; a multiplexer (120, fig. 1) configured to receive the calibration signal and an input voltage; an analog-to-digital converter (ADC) (130) coupled to the multiplexer (120) and configured to generate an output code (132) in response to the calibration signal but do not disclose a circuit that comprises a digital-to-analog converter (DAC) configured to generate a calibration signal in response to an input code of a plurality of input codes and a storage circuit coupled to the ADC and configured to store the output code as address and the input code as data. However, Speir et al., in a related field, disclose a circuit (figs. 9, 10, 11, 12); a digital-to-analog converter (DAC) (1206, fig. 12) configured to generate a calibration signal in response to an input code of a plurality of input codes (figs. 10, 12) and a storage circuit (908, fig. 9) coupled to the ADC (904, fig. 9) and configured to store the output code as address and the input code as data (col. 7, lines 25 – 35). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective fining of the invention to modify Molina et al.’s circuit with that of Speir et al. in order to improve the performance of the circuit.
Regarding claim 3, the combination of Molina et al. and Speir et al. would achieve the same end result as the claimed invention since Speir disclose a circuit further comprising a calibration engine coupled to the storage circuit and the ADC, the calibration engine configured to generate the plurality of input codes (figs. 9, 10, 11, 12; column. 7, lines 25 – 35). Therefore, it would have been obvious to one of ordinary skill in the art at the of the effective filing of the invention to modify Molina et al.’s circuit with that of Speir et al. in order to improve the performance of the circuit.
Regarding claim 2, Molina et al. and Speir et al. combine would achieve the same end result as the claimed invention since Molina et al. disclose in fig. 1 a circuit, wherein the ADC (130) generates a raw code (132) in response to receiving the input voltage (140) from the multiplexer (120), and Speir et al. disclose a circuit (fig. 9) that comprise a storage circuit (908) generates an input code stored at an address corresponding to the raw code as a final output. (fig. 9).
Regarding claims 4 and 13, both Molina et al. and Speir et al. would achieve the same end result; index and course value are well known in the art. As coarse value refers to “rough or large-scale adjustment setting used to quickly move a variable – such as voltage, current or frequency” and index value is known as “parameter lookup”. Molina et al. receives input signal which can be index and coarse value as seen in fig. 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 10, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Molina et al. (EP 3716486) in view of Speir et al. (US Patent Number 9,503,116) as applied to claim 1 above, and further in view of Rajagopal et al. (US Patent Number 11,316,526).
Regarding claims 9, 10, Molinat et al. and Speir et al. disclose all the limitations discussed above except the circuit wherein the ADC further comprises: a plurality of preamplifiers, each preamplifier configured to compare one of an input voltage and the calibration signal to a threshold voltage; a delay multiplexer coupled to the plurality of preamplifiers and configured to generate a delay signal based on an output of one of the preamplifiers; and a backend ADC configured to generate the output code in response to the delay signal (claim 9); the circuit wherein each preamplifier has a different threshold voltage (claim 10). However, Rajagopal et al., in a related field, disclose a circuit the ADC further comprises: a plurality of preamplifiers (20, fig. 1), each preamplifier configured to compare one of an input voltage and the calibration signal to a threshold voltage; a delay multiplexer (34, fig. 1) coupled to the plurality of preamplifiers and configured to generate a delay signal based on an output of one of the preamplifiers; and a backend ADC configured to generate the output code in response to the delay signal (fig. 1); the circuit wherein each preamplifier has a different threshold voltage (fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to incorporate the circuit of Rajagopal et al. in Molinat et al. and Speir et al. in order to improve the performance of the circuit.
Regarding claim 11, the combination of Molina et al., Speir et al. and Rajagopal et al. would achieve the same end result as the claimed invention since Molina et al. disclose a circuit that comprises a multiplexer (120, fig. 1) is configured to provide the input voltage to the ADC (130, fig. 1); and the ADC is configured to generate the raw code in response to the input voltage (fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to combine Rajagopal et al., Molinat et al. and Speir et al. in order to improve the performance of the circuit.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Speir et al. (US Patent Number 9,503,116) in view of Molina et al. (EP 3716486) .
Regarding claim 18, Speir et al. disclose a device (fig. 9) comprising: a processor (910); a memory (908) coupled to the processor (910); and a circuit coupled to the processor and the memory, the circuit comprising: a digital-to-analog converter (DAC) (1206, fig. 12) configured to generate a calibration signal in response to an input code of a plurality of input codes; a storage circuit (908, fig. 9) coupled to the ADC and configured to store the output code as address and the input code as data but do not disclose a circuit comprising a multiplexer configured to receive the calibration signal and an input voltage; an analog-to-digital converter (ADC) coupled to the multiplexer and configured to generate an output code in response to the calibration signal. However, Molina et al., in a related field, disclose a circuit (fig. 9) comprising a multiplexer (120, fig. 1) configured to receive the calibration signal (111, fig. 1) and an input voltage (140, fig. 1); an analog-to-digital converter (ADC) (130) coupled to the multiplexer (120) and configured to generate an output code in response to the calibration signal. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to modify Speir et al.’s circuit with that of Molina et al. in order to improve the performance of the circuit.
Regarding claims 19 and 20, the combination of Speir et al. and Molina et al. would achieve the same end result as the claimed invention since Speir et al’s circuit comprises a storage and calibration engine (see fig. 9 of Speir et al. ) as discussed above and Molina et al’s circuit comprise a multiplexer coupled to an ADC (see fig. 1 of Molina et al.).
Allowable Subject Matter
Claims 5 – 8, 14 – 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845
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