DETAILED ACTION
Status of Application
Claims 1-20 are pending in the present application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/09/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eickemever et al (hereinafter Eickemever), US 20060149934 A1, in view of Colavin et al (hereinafter Colavin), US 20040088526 A1.
Referring to claims 1 and 11, taking claim 1 as exemplary, Eickemever discloses a device comprising:
a memory configured to store a set of instructions that includes a branch instruction [fig. 2, instruction cache 114; paragraph 15, “branch instructions”]; and
a processor coupled to the memory and configured to execute the set of instructions [fig. 2, CPU 10; CPU 10 including BPU 118; “Branch unit 118 executes branch instructions”] to:
receive a set of data elements and a set of validity indicators [fig. 3, paragraph 66, 41, At dispatch time, every instruction will lookup all its source registers in dirty vector 119 to determine if any of these are to be considered invalid; “The bits in dirty bit vector 119 will indicate which results in the GPRs have valid, or invalid results”; hence data elements in the GPRs have validity indicators (bits in dirty bit vector 119)];
determine whether to perform an operation on at least a subset of the set of data elements based on the set of validity indicators [paragraphs 66, 70, At dispatch time, every instruction will lookup all its source registers (RA and RB) in dirty vector 119 to determine if any of these are to be considered invalid; “The dirty bit is forwarded along with results to any dependent instruction. If an instruction uses multiple sources, the dirty bits can simply be logically ORed together. That is, if an instruction is using RA and RB, then the dirty bits for these two (2) registers are ORed together and if one bit is set then the data resulting for the execution of the instruction is considered invalid”; paragraph 17, “Similarly, it is desirable to limit the execution of branches based on ‘dirty’ source operands to avoid unnecessary redirection of the instruction stream, and possible pollution of the instruction cache hierarchy with unneeded data”; Abstract, “Dependency and dirty (i.e. invalid result) bits are tracked and used to determine which speculative instructions are valid for execution”].
Eickemever does not explicitly disclose in response to the branch instruction, determine whether to perform a branch operation based on whether the set of validity indicators specifies that all of the set of data elements is invalid.
However, Colavin discloses in response to the branch instruction, determine whether to perform a branch operation based on whether the set of validity indicators specifies that all of the set of data elements is invalid [paragraphs 15, 38, “In a programmable processor supporting operand predication, an instruction will execute only if the predicate bit of every register containing a source operand is true”; “Memory and branch instructions are similarly predicated”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Colavin in the device of Eickemever to implement, in response to the branch instruction, determine whether to perform a branch operation based on whether the set of validity indicators specifies that all of the set of data elements is invalid, in order to reduce the number of data dependencies introduced in the program data flow graph by predication so as to enable the compiler to generate more efficient code, or more efficient hardware [Colavin, paragraph 14].
Referring to claims 2 and 12, taking claim 2 as exemplary, the modified Eickemever discloses the device of claim 1, wherein:
the processor includes a predicate register [Colavin, paragraph 24, “predicate registers 108 containing operand predicates”]; and
the processor is configured to store the set of validity indicators in the predicate register [Colavin, paragraph 15, “where each operand has an associated predicate bit intuitively indicating the validity of the operand value”].
Claim(s) 10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eickemever, in view of Colavin, as applied to claims 1 and 11 above, and further in view of Wagh et al (hereinafter Wagh), US 20160283429 A1.
Referring to claims 10 and 17, taking claim 10 as exemplary, the modified Eickemever does not explicitly disclose the device of claim 1, wherein the set of data elements is associated with a set of lanes; and
the set of validity indicators includes a respective validity indicator for each lane of the set of lanes that specifies whether the respective lane is associated with valid data or invalid data.
However, Wagh discloses wherein the set of data elements is associated with a set of lanes [paragraph 83]; and
the set of validity indicators includes a respective validity indicator for each lane of the set of lanes that specifies whether the respective lane is associated with valid data or invalid data [paragraph 83, “Accordingly, when the sink logical PHY detects that the valid signal is not asserted (e.g., on lanes VALID0 and VALID1), the sink can disregard any data that is detected on the data lanes (e.g., DATA[0-49])”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Wagh in the device of the modified Eickemever to implement, wherein the set of data elements is associated with a set of lanes; and the set of validity indicators includes a respective validity indicator for each lane of the set of lanes that specifies whether the respective lane is associated with valid data or invalid data, in order to more eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations, one data element at a time [Wagh, paragraph 151].
Allowable Subject Matter
Claims 3-9 and 13-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein: the processor includes a second register; the set of instructions includes an instruction that specifies to transfer the set of validity indicators from the predicate register to the second register; and the branch instruction specifies the set of validity indicators by specifying the second register, in combination with other recited limitations in claim 3.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest the device of claim 1 further comprising a memory circuit coupled to the processor, wherein: the set of instructions includes a stream open instruction; and the processor is configured to, in response to the stream open instruction, cause the memory circuit to retrieve at least a portion of the set of data elements and generate the set of validity indicators, in combination with other recited limitations in claim 4.
Claims 5-9 are objected to based on their dependency.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein: the instructions, when executed, cause the at least one processor core to transfer the set of validity indicators from the predicate register to a second register; and the branch instruction specifies the second register, in combination with other recited limitations in claim 13.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein: the instructions include a stream open instruction that, when executed, causes the at least one processor core to cause a memory circuit to retrieve at least a portion of the set of data elements and generate the set of validity indicators, in combination with other recited limitations in claim 14.
Claims 15-16 are objected to based on their dependency.
Claims 18-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest during a first iteration, based on a branch instruction, determining not to perform a branch operation based on the first set of validity indicators specifying that at least a portion of the first set of data elements is valid; and during a second iteration, based on the branch instruction, determining to perform the branch operation based on the second set of validity indicators specifying that each of the second set of data elements is invalid, in combination with other recited limitations in claim 18.
Claims 19-20 are allowed based on their dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Sprangle, US 20040078558 A1, discloses the data validity circuit determines the validity of the data in the source, e.g., in source registers and indicates the validity of the data in a destination (e.g., a destination register) as follows: If any source register has invalid data (e.g., the validity bit is a logic `0`) then the output of the data validity circuit is logic `0`, i.e., the data validity circuit 335 sets the validity bit of the destination (e.g., a destination register) to a logic `0`. Thus, if a branch instruction is dependent on the data from a previous instruction, the early checker and the late checker may inspect the validity bit of the data from the previous instruction (i.e., the validity bit associated with the destination register) to determine whether the checker sources are correct [paragraph 31].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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/Farley Abad/ Primary Examiner, Art Unit 2181
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