Prosecution Insights
Last updated: October 02, 2026
Application No. 18/973,263

DC-DC CONVERTER WITH HYBRID CURRENT SENSING

Non-Final OA §102§103
Filed
Dec 09, 2024
Priority
Jul 27, 2022 — continuation of 12/206,331
Examiner
GBLENDE, JEFFREY A
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
698 granted / 814 resolved
+17.7% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
25 currently pending
Career history
827
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
54.9%
+14.9% vs TC avg
§102
18.6%
-21.4% vs TC avg
§112
23.0%
-17.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 814 resolved cases

Office Action

§102 §103
DETAILED ACTION This action is in response to the application filed on 12/9/2024. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2014/0001980). Regarding claim 9, Park et al. discloses (see fig. 1) a circuit comprising: a first sample and hold circuit having an output (31 and output from 31); a second sample and hold circuit having an output (15 and output from 15); and an error amplifier (33) having a first input, a second input, and an output (2 inputs and output from 33), the first input coupled to the output of the first sample and hold circuit (31 connection to input of 33) and the second input coupled to the output of the second sample and hold circuit (15 connection to input of 33). Claim(s) 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US Patent 9853548). Regarding claim 17, Park et al. discloses (see fig. 3 and 4) a method comprising: receiving a current sense signal (peak value from 412); sampling and holding, by a first sample and hold circuit (414), the current sense signal, to produce a first hold signal (output from 414); receiving a current emulation signal (valley value from 412); sampling and holding, by a second sample and hold circuit (416), the current emulation signal, to produce a second hold signal (output from 416); and producing an updated emulation signal based on the first hold signal and the second hold signal (operation of 415/418/420/404/206/208 to controlling the operation of SW1 and SW2 which changes valley value from 412). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2014/0001980) in view of Sheehan (US Patent 7936160) and Kobayashi (US Patent 9471077). Regarding claim 10, Park et al. discloses (see fig. 1) a current measurement circuit (circuit used in producing CS) having an output coupled to an input of the first sample and hold circuit (CS connection to input of 31). Park et al. does not disclose a switch network coupled to the current measurement circuit and to the output of the error amplifier. Sheehan discloses (see fig. 1) a switch network (S1) coupled to a current measurement circuit (S1 connection to 120). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the circuit of Park et al. to include the features of Sheehan because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Kobayashi discloses (see fig. 4) a switch network (S1/S2) coupled to an output of an error amplifier (S1/S2 connection to the output of the error amplifier). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the circuit of Park et al. to include the features of Kobayashi because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Claim(s) 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2014/0001980) in view of Ouyang (US Patent 9716432). Regarding claim 12, Park et al. does not disclose that a capacitor coupled to the output of the error amplifier; a current source circuit coupled to the capacitor; and a current sink circuit coupled to the capacitor. Ouyang discloses (see fig. 2) a capacitor (CSLOPE) coupled to an output of an error amplifier (connection to output from AMP); a current source circuit coupled to the capacitor (U11 connection to CSLOPE); and a current sink circuit coupled to the capacitor (U12 connection to CSLOPE). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the circuit of Park et al. to include the features of Ouyang because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 13, Park et al. does not disclose a switch coupled between the current source circuit and the capacitor. Ouyang discloses (see fig. 2) a switch (S1) coupled between the current source circuit and the capacitor (connection to U11, U12 and CSLOPE). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the circuit of Park et al. to include the features of Ouyang because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Claim(s) 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US Patent 9853548 in view of Ouyang (US Patent 9716432). Regarding claim 18, Zhang does not disclose charging, by a ramp-up circuit, a capacitor; and discharging, by a ramp-down circuit, the capacitor. Ouyang discloses (see fig. 2) charging, by a ramp-up circuit (operation of U11), a capacitor (CSLOPE); and discharging, by a ramp-down circuit (operation of U12), the capacitor (CSLOPE). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Zhang to include the method of Ouyang because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US Patent 9853548 in view of Nguyen et al. (US Patent 9184651). Regarding claim 20, Zhang does not disclose producing the current sense signal by measuring an inductor current; and producing a sense current output by selecting either the current sense signal or the current emulation signal. Nguyen et al. discloses (see fig. 3 and 4) producing a current sense signal (CS) by measuring an inductor current (operation of 35, wherein 33 is on CS is equal to the inductor current); and producing a sense current output (output to 46) by selecting (operation of switch 41) either the current sense signal (CS) or a current emulation signal (CE). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the method of Zhang to include the method of Nguyen et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Allowable Subject Matter Claims 1-8 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claim 1, the prior art fails to teach or disclose a circuit comprising: a second switch having a first terminal and a second terminal, the first terminal coupled to the output of the current emulation circuit and the second terminal coupled to the second terminal of the first switch; and a third switch having a first terminal and a second terminal, the first terminal coupled to the first terminal of the first switch and the second terminal coupled to the first terminal of the second switch, in combination with all the limitations set forth in claim 1. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Claims 11, 14-16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A GBLENDE whose telephone number is (571)270-5472. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Dec 09, 2024
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.7%)
2y 4m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 814 resolved cases by this examiner. Grant probability derived from career allowance rate.

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