DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Information Disclosure Statement
The references listed in the information disclosure statement (IDS) submitted have been considered. The submission complies with the provisions of 37 CFR 1.9 /. Form PTO-1449 is signed and attached hereto.
Specification
The specification is accepted.
Drawings
The formal drawings are accepted.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 line 7, recites “the number of first bits” and it should recite “the number of first bits that are invalid”.
Claim 7 lines 10 and 13, recites “the number of second bits” and it should recite “the number of second bits that are invalid”.
Claim 16, line 13 recited “error detection information” and it should recite “the first error detection information”.
Claim 16, line 19, ended with period instead of semicolon.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites, “receiving a write command to write user data to one or more memory units of a number of memory units” which renders the claim indefinite since it is unclear how to distinguish between “one or more memory units” and “a number of memory units” that make up the memory units.
Claim 7 recites “write the number of second bits to a second portion of the plurality of memory units instead of a number of third bits corresponding to the error correction information or the first error detection information” is unclear and vague, it is unknown the connection between the second bits and the third bits. Interconnections between the number of second bits and a number of third bits are confusing and for the most part not detailed or mentioned in the claim. It is difficult to translate the claim and follow what processes are taking place. Further, the claims recite the negative limitation “instead of a number of third bits corresponding to the error correction information or the first error detection information”. The introduction of negative limitation does not narrow the claim limitation and lack/silence of explicitly teaching that limitation by the prior art does not exclude the prior art from the teaching of that particular limitation. Thus, negative limitation does not narrow the limitation.
Claim 9 recite the limitation wherein the controller is further configured to: in response to the user data being determined to be not corrupted, generate the number of third bits; and write, instead of the number of second bits, the number of third bits to the second portion of the plurality of memory units. The introduction of negative limitation does not narrow the claim limitation and lack/silence of explicitly teaching that limitation by the prior art does not exclude the prior art from the teaching of that particular limitation. Thus, negative limitation does not narrow the limitation.
Claim 10 recites the limitation wherein the controller is further configured to write, instead of the number of first bits of the user data, the number of second bits to the first portion of the plurality of memory units. The introduction of negative limitation does not narrow the claim limitation and lack/silence of explicitly teaching that limitation by the prior art does not exclude the prior art from the teaching of that particular limitation. Thus, negative limitation does not narrow the limitation.
Dependent claims depend from the base claims and inherently include limitations therein and therefore are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as well.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 1, 2, 7, 9, 10, and 12 are rejected under 35 U.S.C. 103(a) as being unpatentable over Shim (U.S. PN: 9,164,677) in view of Sharon et al. “herein as Sharon” (US-20130024748).
As per claim 1:
Shim substantially teaches or discloses a method, comprising receiving a write command to write user data to one or more memory units of a number of memory units (see figure 9, col. 2, lines 12-35 and col. 5, lines 66-67 to col. 6, lines 1-24) responsive to the user data being determined to be corrupted, generating a number of first bits that are invalid as error correction information or error detection information for the user data (see col. 1, lines 54-65, col. 2, lines 4-11, col. 2, lines 54-67 to col. 3, lines 1-7, col. 6, lines 25-33, and col. 11, lines 19-29)
Shim substantially teaches the claimed invention described in claim 1 (as indicated above). However, Shim does not explicitly teach writing data to a first portion of the number of memory units and writing, along with the user data, the number of first bits to a second portion of the number of memory units.
Sharon, in an analogous art, teaches writing data to a first portion of the number of memory units and writing, along with the user data, the number of first bits to a second portion of the number of memory units (see par. [0153-0154], In Sharon)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Shim with the teachings of Sharon by writing data to a first portion of the number of memory units and writing, along with the user data, the number of first bits to a second portion of the number of memory units.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that writing data to a first portion of the number of memory units and writing, along with the user data, the number of first bits to a second portion of the number of memory units would have provided to enhance the accuracy of the error detecting process and the overall system performance.
As per claim 2:
The combination of Shim and Sharon substantially teaches responsive to receiving the write command including the user data, generating first error detection information based on the user data; and performing an error detection operation on the user data using the first error detection information prior to writing the user data to the first portion of the number of memory units and to indicate whether the user data is corrupted or not (see col. 2, lines 57-62, In Shim).
As per claim 7:
Shim substantially describes or teaches apparatus comprising a plurality of memory units; and a controller communicatively coupled to the plurality of memory units (see figures 1, 2 and col. 5, lines 5, lines 66-67 to col. 6, lines 1-15) the controller configured to receive a write command to write user data comprising a number of first bits to a first portion of the plurality of memory units responsive to the user data being determined to be corrupted, generate a number of second bits that are invalid as error correction information or first error detection information for the user data (see col. 2, lines 25-67 to col. 3, lines 1-7 and col. 6, lines 25-33, col. 11, lines 19-29) such that an error correction operation or an error detection operation performed using the number of second bits on the user data is designed to result in one or more uncorrectable bit errors on the user data or indication of one or more bit errors on the user data (see col. 6, lines 25-33 and col. 10, lines 27-46).
Shim substantially teaches the claimed invention described in claim 7 (as indicated above).
However, Shim does not explicitly teach write the number of second bits to a second portion of the plurality of memory units instead of a number of third bits corresponding to the error correction information or the first error detection information.
Sharon, in an analogous art, teaches write the number of second bits to a second portion of the plurality of memory units instead of a number of third bits corresponding to the error correction information or the first error detection information (see par. [0153-0154], In Sharon)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Shim with the teachings of Sharon by writing the number of second bits to a second portion of the plurality of memory units instead of a number of third bits corresponding to the error correction information or the first error detection information.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that writing the number of second bits to a second portion of the plurality of memory units instead of a number of third bits corresponding to the error correction information or the first error detection information would have provided to enhance the accuracy of the error detecting process and the overall system performance
As per claim 9:
The combination of Shim and Sharon substantially teaches wherein the controller is further configured to: in response to the user data being determined to be not corrupted, generate the number of third bits; and write, instead of the number of second bits, the number of third bits to the second portion of the plurality of memory units (see col. 2, lines 54-67 to col. 3, lines 1-7, col. 6, lines 25-33, col. 11, lines 19-29, in Shim).
As per claim 10:
The combination of Shim and Sharon substantially teaches wherein the controller is further configured to write, instead of the number of first bits of the user data, the number of second bits to the first portion of the plurality of memory units (see col. 2, lines 54-67 to col. 3, lines 1-7, col. 6, lines 25-33, col. 11, lines 19-29).
As per claim 12:
The combination of Shim and Sharon substantially teaches wherein the first error detection information corresponds to cyclic redundancy check (CRC) data (see col. 6, lines 25-33 and col. 10, lines 33-37, In Shim).
Claims 8 and 11 are rejected under 35 U.S.C. 103(a) as being unpatentable over Shim (U.S. PN: 9,164,677) in view of Sharon et al. “herein as Sharon” (US-20130024748) further in view of Kim et al. “herein as Kim” (11,681,579).
Regarding claim 8, most of the limitations of this claim has been noted in the rejection of Claim 7. However, the combination of teachings above does not explicitly teach the wherein the controller is configured to write the number of second bits to the second portion of the plurality of memory units via one or more data mask inversion (DMI) pins.
Kim, in an analogous art, teaches wherein the controller is configured to write the number of second bits to the second portion of the plurality of memory units via one or more data mask inversion (DMI) pins “the parity generator 515 may be disabled in response to an enable signal EN3. In this case, the channel interface circuit 500a may transmit once the decoding status flag DSF to the memory controller 100 through the data mask and inversion pin DMIP, repeatedly transmit the decoding status flag DSF to the memory controller 100 through the data mask and inversion pin DMIP, or transmit the pre-defined pattern PDP to the memory controller 100 through the data mask and inversion pin DMIP (View Kim col. 11, lines 59-67 to col. 16, lines 1-7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the combination of Shim and Sharon with the teachings Kim to write the number of second bits to the second portion of the plurality of memory units via one or more data mask inversion (DMI) pins.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that write the number of second bits to the second portion of the plurality of memory units via one or more data mask inversion (DMI) pins would have provided to improved security and increased capacity.
Regarding claim 11, most of the limitations of this claim has been noted in the rejection of Claim 7. However, the combination of teachings above does not explicitly teach the wherein the number of second bits corresponds to a number of predefined bit patterns.
Kim, in an analogous art, teaches wherein the controller is configured to write the number of second bits to the second portion of the plurality of memory units via one or more data mask inversion (DMI) pins “the parity generator 515 may be disabled in response to an enable signal EN3. In this case, the channel interface circuit 500a may transmit once the decoding status flag DSF to the memory controller 100 through the data mask and inversion pin DMIP, repeatedly transmit the decoding status flag DSF to the memory controller 100 through the data mask and inversion pin DMIP, or transmit the pre-defined pattern PDP to the memory controller 100 through the data mask and inversion pin DMIP (View Kim col. 11, lines 59-67 to col. 16, lines 1-7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the combination of Shim and Sharon with the teachings Kim that the number of second bits corresponds to a number of predefined bit patterns.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that the number of second bits corresponds to a number of predefined bit patterns would have provided to improved security and increased capacity.
Allowable Subject Matter
Claims 3-6, and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. However, such an allowance is conditioned on the resolution of all of the identified claim objections and rejections based upon 35 U.S.C. 112, of independent claims 1 and 7.
Claim 16 would be allowable if rewritten or amended to overcome the claim objection, set forth in this Office action. Dependent claims 17-20 would be allowable, however, such an allowance is conditioned on the resolution of the identified claim objections to claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sridharan et al. (U.S. PN: 11,573,853) teach performing 904 an error check on the data block read from host memory using host-generated error checking information stored in the data block prior to copying the data block to the remote execution device includes marking 802 the data block with an error indicator when an unrecoverable error is detected. In some examples, marking 802 the data block with an error indicator when an unrecoverable error is detected is carried out by the host 302 indicating within the data block that the data or a portion thereof is corrupted.
Vrabel et al. (U.S. PN: 11,210,186) teach if an ECC error is detected, then an unlocked error bank register is updated with information about that error: the valid bit is set; the address gives the address of the error; if the error is correctable, the data is set the corrected data at that location; and if the error is uncorrectable, the poison bit is set (to indicate that the data at this address has been corrupted)
Coquerrel et al. (U.S. PN: 10,936,404) describe the error detector 214 may be configured to compute a checksum (e.g., cyclic redundancy check (CRC)) of the respective data and then check to see that the checksums are the same. For example, the error detector 214 may be configured to apply additional and/or alternative comparisons, such as a length/size of the decompressed data relative to a length/size of the uncompressed data, to detect a corrupted bit in the data stream. The error indicator 216 is configured to indicate whether an error was detected (e.g., updating a flag, generating a fault, generating an exception, etc.) to the error recovery manager 218 based on a result of the comparison performed by the error detector 214.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112
Prosecution Insights