Prosecution Insights
Last updated: October 01, 2026
Application No. 18/973,471

MULTILAYER ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §103
Filed
Dec 09, 2024
Priority
Jan 23, 2024 — RE 10-2024-0009846
Examiner
TORRES, TIMOTHY JOSEPH
Art Unit
Tech Center
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
1 granted / 1 resolved
+40.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
21 currently pending
Career history
9
Total Applications
across all art units

Statute-Specific Performance

§103
64.9%
+24.9% vs TC avg
§102
25.7%
-14.3% vs TC avg
§112
8.1%
-31.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Election/Restrictions Claim(s) 8 and 14-15 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 2, 2026. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-3, 7, 9-11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakano et al. JP 2022085688 A in view of Sawada et al. US 20180182552 A1 and further in view of Kim et al. US 2013/0258546 A1. PNG media_image1.png 933 1654 media_image1.png Greyscale Figure 1: Examiner annotated fig. 16a of Nakano ‘688 pointing out a connection portion, a band portion, and a corner portion. Regarding claim 1, Nakano ‘688 discloses A multilayer electronic component comprising: a body (12 – fig. 16a; para. [0094]) including a dielectric layer (14 – fig. 16a; para. [0095]) and first and second internal electrodes alternately disposed with the dielectric layer therebetween (16 – fig. 16a; para. [0095]), and including a first surface and a second surface opposing each other in a first direction (12a, 12b, X – fig. 16a), a third surface and a fourth surface, connected to the first and second surfaces and opposing each other in a second direction (12e, 12f, Z – fig. 16a), and a fifth surface and a sixth surface, connected to the first to fourth surfaces and opposing each other in a third direction (12c, 12d, Y, fig. 17); and an external electrode (30 – fig. 16a; para. [0096]) including: a connection portion disposed on the third surface and/or the fourth surface (connection portion – present office action figure 1, hereafter called POA1), and a band portion extending from the connection portion to a portion of the first surface and a portion of the second surface (band portion – POA1), wherein the external electrode includes: a plating layer disposed in the connection portion and contacting the first and/or second internal electrode and including Cu (42 – fig. 16a; para. [0171]), an oxide layer disposed on the plating layer and including a Cu oxide, and a conductive polymer layer disposed in the band portion and including a polymer material (32 – fig. 16a; paras. [0100-0101] and [0105] or 32 – fig. 16b; paras. [0093] and [0103]). Nakano ‘688 fails to disclose wherein the external electrode includes: a sputtered layer and an oxide layer is disposed on the sputtered layer and including a Cu oxide. Sawada ‘552 discloses wherein a sputtering layer is an alternative to a plating layer for a thin electrode layer (para. [0084]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the plating layer of Nakano ’688 as a sputtered layer, as sputtering is an alternative to plating for forming an external electrode layer (para. [0084] of Sawada ‘552). Sawada ‘552 fails to disclose wherein the external electrode includes an oxide layer disposed on the sputtered layer and including a Cu oxide. Kim ‘546 discloses wherein the external electrode includes an oxide layer disposed on the sputtered layer and including a Cu oxide (para. [0076]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a copper oxide layer on the sputtered layer of Nakano ‘688 as modified by Sawada ‘552 in order to prevent a plating solution and hydrogen gas from entering the body, improving reliability (para. [0076] of Kim ‘546). Regarding claim 2, modified Nakano ‘688 discloses The multilayer electronic component of claim 1, wherein the conductive polymer layer (32 – fig. 16a of Nakano ‘688) includes a first layer disposed on the first surface (32a – fig. 17; paras. [0102] and [0166] of Nakano ‘688), and a second layer spaced apart from the first layer and disposed on the second surface (32c – fig. 17; paras. [0102] and [0166] of Nakano ‘688). Regarding claim 3, modified Nakano ‘688 discloses The multilayer electronic component of claim 1, wherein the conductive polymer layer (32 – fig. 16a of Nakano ‘688) is not disposed in the connection portion (see POA1 and para. [0093] of Nakano ‘688). Regarding claim 7, modified Nakano ‘688 discloses The multilayer electronic component of claim 1, wherein one end of the conductive polymer layer (32 – fig. 16b of Nakano ‘688) is disposed in the connection portion (see fig. 16b and paras. [0093] and [0103] of Nakano ‘688). Regarding claim 9, modified Nakano ‘688 discloses The multilayer electronic component of claim 1, wherein one end of the sputtered layer is disposed in the band portion, and in the band portion, the conductive polymer layer (32 – fig. 16a of Nakano ‘688) is disposed between the body and the sputtered layer (see POA1). Regarding claim 10, modified Nakano ‘688 discloses The multilayer electronic component of claim 1, wherein an amount (at%) of Cu among a total amount (at%) of elements constituting the sputtered layer is 99 at% or more (para. [0118] only mentions Cu when disclosing what is preferably used for suppressing penetration of a plating solution and would therefore be at least 99 at% as Cu is the only component mentioned in layer 42). Regarding claim 11, modified Nakano ‘688 discloses The multilayer electronic component of claim 1, wherein the external electrode further includes: a Ni plated layer disposed on the oxide layer in the connection portion and disposed on the conductive polymer layer in the band portion (44 – fig. 16a and para. [0122] of Nakano ‘688; after the modification with Kim ‘546, the Ni plated layer will be disposed on the oxide layer), and a Sn plated layer disposed on the Ni plated layer (46 – fig. 16a and para. [0126] of Nakano ‘688). Regarding claim 13, modified Nakano ‘688 discloses The multilayer electronic component of claim 1, wherein the polymer material includes at least one of polypyrrole, polyaniline, polythiophene, or PEDOT:PSS (para. [0105] of Nakano ‘688). Claim(s) 1, 4-6, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 2022/0392707 A1 in view of Sawada et al. US 2018/0182552 A1 and further in view of Kim et al. US 2013/0258546 A1. PNG media_image2.png 463 1016 media_image2.png Greyscale Figure 2: Examiner annotated fig. 3 of Lee ‘707 pointing out a connection portion, a band portion, and a corner portion. Regarding claim 1, Lee ‘707 discloses A multilayer electronic component comprising: a body (110 – fig. 1; para. [0040]) including a dielectric layer (111 – fig. 3; para. [0041]) and first and second internal electrodes alternately disposed with the dielectric layer therebetween (121, 122 – fig. 3; para. [0048]), and including a first surface and a second surface opposing each other in a first direction (1, 2, Z – fig. 1), a third surface and a fourth surface, connected to the first and second surfaces and opposing each other in a second direction (3, 4, X – fig. 1), and a fifth surface and a sixth surface, connected to the first to fourth surfaces and opposing each other in a third direction (5, 6, Y – fig. 1); and an external electrode (130 – fig. 1; para. [0040]) including: a connection portion disposed on the third surface and/or the fourth surface (connection portion – present office action figure 2, hereafter called POA2), and a band portion extending from the connection portion to a portion of the first surface and a portion of the second surface (band portion – POA2), wherein the external electrode includes: a layer (131 – fig. 3; paras. [0058-0059]) disposed in the connection portion and contacting the first and/or second internal electrode and including Cu (POA2; paras. [0053] and [0061]), and a conductive polymer layer disposed in the band portion and including a polymer material (133 – fig. 3; paras. [0058] and [0071] disclose a conductive polymer resin). Lee ‘707 fails to disclose wherein the external electrode includes: a sputtered layer and an oxide layer disposed on the sputtered layer and including a Cu oxide. Sawada ‘552 discloses wherein a sputtering layer may be used for a thin electrode layer as well as other alternative methods (para. [0084]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the layer of Lee ‘707 as a sputtered layer as taught by Sawada ‘552 to obtain a thin film electrode of a desired thickness with reduced thickness variation therein (para. [0084 or Sawada ‘552). Furthermore, Sawada ‘552 discloses various methods of forming the underlying electrode of a MLCC and it would have been obvious to one of ordinary skill in the art prior to the effective filing date to choose a well-known method based on the manufacturing equipment available to one. Sawada ‘552 fails to disclose wherein the external electrode includes an oxide layer disposed on the sputtered layer and including a Cu oxide. Kim ‘546 discloses wherein the external electrode includes an oxide layer disposed on the sputtered layer and including a Cu oxide (para. [0076]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a copper oxide layer on the sputtered layer of Lee ‘707 as modified by Sawada ‘552 in order to prevent a plating solution and hydrogen gas from entering the body, improving reliability (para. [0076] of Kim ‘546). Regarding claim 4, modified Lee ‘707 discloses The multilayer electronic component of claim 1, wherein the external electrode includes a corner portion disposed between the connection portion and the band portion (corner portion – POA2), one end of the sputtered layer is disposed in the corner portion (PAO2 and para. [0059] of Lee ‘707 shows an end of the sputtered layer is disposed in the corner portion in the same way as depicted figs. 2 and 10 of the applicant’s present disclosure). Regarding claim 5, modified Lee ‘707 discloses The multilayer electronic component of claim 4, wherein, in the corner portion, the conductive polymer layer covers the one end of the sputtered layer (fig. 4A of Lee ‘707 clearly shows an end of 131 covered by 133b included in 133 in the same way as depicted fig. 2 of the applicant’s present disclosure). Regarding claim 6, modified Lee ‘707 discloses The multilayer electronic component of claim 4, wherein, in the corner portion, the sputtered layer covers one end of the conductive polymer layer (POA2 and fig. 4A of Lee ‘707 clearly shows that an end of 133b included in 133 is covered by 131 from above as the end of 133b disposed on 131. As seen in figs. 2 and 10 of applicant’s present disclosure, this is what constitutes covered). Regarding claim 12, modified Lee ‘707 discloses The multilayer electronic component of claim 1, wherein the polymer material includes an insulating resin (para. [0071] discloses insulative resins which are also polymers), and the conductive polymer layer further includes a metal particle (para. [0068]; metal particles are included to make the polymer (resin) layer conductive). Claim(s) 1 and 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zenzai US 2021/0057154 A1 in view of Kim et al. US 2013/0258546 A1. PNG media_image3.png 612 1223 media_image3.png Greyscale Figure 3: Examiner annotated fig. 2 of Zenzai ‘154 pointing out a connection portion, a band portion, and a corner portion. Regarding claim 1, Zenzai ‘154 discloses A multilayer electronic component comprising: a body (12 – fig. 1; para. [0035]) including a dielectric layer (14b – fig. 2; para. [0037]) and first and second internal electrodes alternately disposed with the dielectric layer therebetween (16 – fig. 2; para. [0037]), and including a first surface and a second surface opposing each other in a first direction (12a, 12b, X – fig. 1), a third surface and a fourth surface, connected to the first and second surfaces and opposing each other in a second direction (12e, 12f, Z – fig. 1), and a fifth surface and a sixth surface, connected to the first to fourth surfaces and opposing each other in a third direction (12c, 12d, Y – fig. 1); and an external electrode (24a – fig. 1; para. [0053]) including: a connection portion disposed on the third surface and/or the fourth surface (connection portion – present office action figure 3, hereafter called POA3. Note that as claimed, the connection portion may only be a portion of the third surface. As seen in POA3, the connection portion consists of a portion of the third and fourth surface slightly before a rounded portion), and a band portion extending from the connection portion to a portion of the first surface and a portion of the second surface (band portion – POA3), wherein the external electrode includes: a sputtered layer (26a – fig. 2; paras. [0054] and [0058]) disposed in the connection portion and contacting the first and/or second internal electrode and including Cu (POA3; para. [0057]), and a conductive polymer layer (28a – fig. 2; a resin is a polymer and specifically, epoxy is a polymer, see para. [0073]) disposed in the band portion and including a polymer material (POA3; para. [0073]). Zenzai ‘154 fails to disclose wherein the external electrode includes an oxide layer disposed on the sputtered layer and including a Cu oxide. Kim ‘546 discloses wherein the external electrode includes an oxide layer disposed on the sputtered layer and including a Cu oxide (para. [0076]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form a copper oxide layer on the sputtered layer of Zenzai ‘154 in order to prevent a plating solution and hydrogen gas from entering the body, improving reliability (para. [0076] of Kim ‘546). Regarding claim 4, modified Zenzai ‘154 discloses The multilayer electronic component of claim 1, wherein the external electrode includes a corner portion disposed between the connection portion and the band portion (corner portion – POA3; Note that a corner portion is defined in para. [0054] of applicant’s present disclosure. However, this definition does not further define a first edge EG1 or a second edge EG2. An edge may extend onto another surface as an edge is not defined as ending where a curvature ends. Therefore, the corner portion may extend onto another surface as shown in POA3), one end of the sputtered layer is disposed in the corner portion (POA3 clearly shows an end of the sputtered layer in the corner portion). Regarding claim 5, modified Zenzai ‘154 discloses The multilayer electronic component of claim 4, wherein, in the corner portion, the conductive polymer layer covers the one end of the sputtered layer (POA3 and para. [0059] of Zenzai ‘154 clearly shows the conductive polymer layer covering a portion of one end of the sputtered layer in the corner portion). Regarding claim 6, modified Zenzai ‘154 discloses The multilayer electronic component of claim 4, wherein, in the corner portion, the sputtered layer covers one end of the conductive polymer layer (POA3 and para. [0059] of Zenzai ‘154 clearly shows the conductive polymer layer covering one end of the sputtered layer in the corner portion). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20180268998 A1: fig. 2 US 20210065984 A1: fig. 3 US 20200251283 A1: fig. 3 US 20140029157 A1: para. [0064] CuO layer US 20160086733 A1: 20 – fig. 1; para. [0028] Cu2O layer and rational US 20210217561 A1: para. [0057] teach conductive polymers from claim 13 and metal particles US 20220208474 A1: fig. 2 US 20200273621 A1: 132 – fig. 2; paras. [0013-0015], [0088], and [0094] US 20130299215 A1: paras. [0047-0050]; includes copper oxide protective layer US 6381117 B1: fig. 7 Communication Any inquiry concerning this communication or earlier communications from the examiner should be directed to Timothy Torres whose telephone number is (571)272-9896. The examiner can normally be reached Mon-Fri 7:30-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /T.J.T./Examiner, Art Unit 2847 /Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
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Prosecution Timeline

Dec 09, 2024
Application Filed
Sep 21, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 0m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1 resolved cases by this examiner. Grant probability derived from career allowance rate.

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