DETAILED ACTION
This office action is in response to the applicant's amendment submitted on 07/20/2026. In virtue of this amendment:
Claim 9 is canceled;
Claims 1, 6-8 and 10 currently amended; and thus,
Claims 1-8 and 10 are pending;
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The rejection to claims 1-10 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph is withdrawn in view of the amendment made to the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over NPL “Transistor drive LEDs to light the path” hereinafter “EDN” in view of US2011/0248632A1 hereinafter “Williams” in view of US2013/0249422A1 hereinafter “Kerstens” further in view of US2003/0202851A1 hereinafter “Kovarik”
Regarding claim 1, EDN disclose in Fig.1 (recreated by examiner below) a light-emission circuit for a handheld tool, the circuit comprising:
PNG
media_image1.png
525
608
media_image1.png
Greyscale
a first node (as annotated above, connect to one end capacitor [C1]) providing a first input voltage reference (output voltage of rectifier);
a second node (as annotated above, connect to other end of capacitor [C1]) providing a second input voltage reference (ground reference), the second node separated from the first node by a first capacitor (as shown above, capacitor [C1]),
a third node (as annotated above, connect to one end resistor [R1]) separated from the second node by a second capacitor (as shown above, capacitor [C2]) in parallel with a light emission branch (as annotated above); and wherein
the light emission branch comprises a first sub-branch having a light emitting diode (LED) having a first high pin and a first low pin (as annotated above),
a second sub-branch having a transistor array (transistor [Q1] and [Q2]) with two second high pins and a second low pin (as annotated above), the transistor array configured to regulate the current draw of the light emission branch (Page.1: the two transistor act as a simple current source), wherein
the first high pin and one of the two second high pins are connected to the third node (as shown above, third node is connect to 1st high pin and 1st 2nd high pin via resistor [R1]), and the second low pin is connected to the second node (as shown above, the 2nd low pins are connected together to ground)
EDN does not explicitly disclose:
the third node separated from the first node by a diode restricting current flow between the first node and the third node
Williams discloses in Fig.4 for example an LED circuity, with a rectifier, a capacitor and a LED wherein
the third node (as shown in Fig.4, one end of LED [4]) separated from the first node (as shown in Fig.4, output end of rectifier) by a diode (¶29L8-11: a Zener diode (not shown) may be provided between the bridge rectifier and the charge storage element) restricting current flow between the first node and the third node (inherent property of a diode is to allow current to flow only one way)
It would have been obvious to one ordinarily skilled in the art prior to the effective filing date of the application to include the Zener diode disclosed by Williams to the circuitry disclosed by EDN.
One of ordinary skill in the art would’ve been motivated because this prevents over-charging of the storage element. (¶29L8-11)
EDN in view of Williams hereinafter “EDN/Williams” does not explicitly disclose:
the LED array comprises a plurality of sub-path in parallel, each of the sub-paths comprising an identical number of LEDs
Kerstens discloses a current mirror circuit for driving LED (as shown in Fig.8 for example) wherein, the LED array comprises
a plurality of sub-path in parallel (¶38L1-21: a first LED string [110] and a second LED string [111]), each of the sub-paths comprising an identical number of LEDs (¶38L1-21: a first LED string [110] includes LEDs [110A-110E], the second LED string [111] includes LEDS [111A-111E])
It would have been obvious to one ordinarily skilled in the art prior to the effective filing date of the application to modify the LED string shown with 4 total LED connected in series disclosed by EDN to be connected in a parallel configuration with 2 LED string including 2 LEDs in each string as disclosed by Kerstens.
One of ordinary skill in the art would’ve been motivated because parallel LED configuration have the advantage of requiring a lower line voltage than a series configuration (US2014/0015424A1 - ¶6L1-6) and prior art recognizes such configuration is common in the art. (Kerstens ¶3L1-6)
EDN/Williams in view of Kerstens hereinafter “EDN/Williams/Kerstens” does not explicitly disclose:
the light-emission circuit is disposed within a nosecap of the handheld tool.
Kovarik discloses a handheld power tool with a LED light disposed within the housing (¶25L6-7: the drill includes a hosing and a light [116])
It would have been obvious to one ordinarily skilled in the art prior to the effective filing date of the application to utilize the LED circuitry disclosed by EDN/Williams/Kerstens to be the light disclosed by Kovarik.
One of ordinary skill in the art would’ve been motivated because LEDs consumes less power than other form of lighting device, and the LED can illuminate when the drill is in operation letting the user know the operating status of the drill.
Regarding claim 2, EDN/Williams/Kerstens in view of Kovarik hereinafter “EDN/Williams/Kerstens/Kovarik” discloses in EDN the light-emission circuit of claim 1, wherein the transistor array comprises
a plurality of bipolar junction transistors (BJT) (as shown above; transistor [Q2] and [Q1]), wherein
the base of a first BJT is electrically connected to the collector of a second BJT (base of [Q2] is connected to collector of [Q1]), and wherein
the base of the second BJT is electrically connected to the emitter of the first BJT.(base of [Q1] is connected to emitter of [Q2])
Regarding claim 3, EDN/Williams/Kerstens/Kovarik discloses in EDN the light-emission circuit of claim 2, wherein
the collector of the second BJT is electrically separate from the third node by a first impedance load (collector of [Q1] is separated from third node by resistor [R1]) and
the emitter of the first BJT is electrically separated from the second node by a second impedance load (emitter of [Q2] is separate from second node by resistor [R2]).
Regarding claim 4, EDN/Williams/Kerstens/Kovarik discloses in EDN the light-emission circuit of claim 3, wherein
the first impedance load and the second impedance load are resistors. (Page.1 two-transistor, two resistor circuit)
Regarding claim 5, EDN/Williams/Kerstens/Kovarik discloses in EDN the light-emission circuit of claim 2, further comprising
a fourth node where the first low pin is electrically connected to the collector of the first BJT. (as shown above, the 1st low pin is connected to collector of [Q2] through [R5])
Regarding claim 6, EDN/Williams/Kerstens/Kovarik discloses the light-emission circuit of claim 1, wherein
each sub-path comprises a plurality of LEDs in series between the first high pin and the first low pin along the sub-path. (as shown in Fig.8 of Kerstens)
Regarding claim 7, EDN/Williams discloses in EDN the light-emission circuit of claim 6, wherein
each sub-path comprises 2 LEDs in series between the first high pin and the first low pin along the sub-path. (Note: since EDN shows 4 total LED in series in one branch, the combination of EDN/Williams/Kerstens/Kovarik would split the 4 LED into 2 branch of 2 LED each.)
Regarding claim 8, EDN/Williams discloses in EDN the light-emission circuit of claim 6, wherein
the LED array comprises a pair of sub-paths. (as shown in Fig.8 of Kerstens)
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over EDN in view of William.
Regarding claim 10, EDN disclose in Fig.1 (recreated by examiner above) a light-emission circuit for a handheld tool, the circuit having 4 nodes,
a first input voltage reference (output voltage of rectifier),
a second input voltage reference (ground reference)),
a light emitting diode (LED) array (annotated as first sub-branch), and
a transistor array (annotated as second sub-branch), the circuit further comprising:
a first node (as annotated above, connect to one end capacitor [C1]) connected to the first input voltage reference (output voltage of rectifier);
a second node (as annotated above, connect to other end of capacitor [C1] and grounded) connected to the second input voltage reference and separated from the first node by a first capacitor (as shown above, capacitor [C1]),
a third node (as annotated above, connect to one end resistor [R1]) separated from the second node by a second capacitor (as shown above, capacitor [C2])
a light emission branch comprising the LED array and the transistor array, wherein the capacitor and the light emission branch are in parallel (as annotated above, capacitor [C2] is in parallel with first/second sub-branch); and
a fourth node (as shown above, the 1st low pin is connected to collector of [Q2] through [R5]) within the light emission branch, the fourth node separated from the third node by the LED array, and separated from the second node by a sub-path of the transistor array, wherein the transistor array (as shown above) comprises
a pair of bipolar junction transistors (BJTs) (as shown above; transistor [Q2] and [Q1]),
the collector of a first BJT connected to the fourth node (as shown above, the 1st low pin is connected to collector of [Q2] through [R5]), the base of the first BJT connected to the collector of a second BJT (base of [Q2] is connected to collector of [Q1]), the emitter of the first BJT connected to the base of the second BJT and separated from the second node by a first resistor (emitter of [Q2] is separate from second node by resistor [R2]), the collector of the second BJT separated from the third node by a second resistor (collector of [Q1] is separated from third node by resistor [R1]), and the emitter of the second BJT connected to the second node (emitter of [Q1] is grounded).
EDN does not explicitly disclose:
the third node separated from the first node by a diode restricting current flow between the first node and the third node
Williams discloses in Fig.4 for example an LED circuity, with a rectifier, a capacitor and a LED wherein
the third node (as shown in Fig.4, one end of LED [4]) separated from the first node (as shown in Fig.4, output end of rectifier) by a diode (¶29L8-11: a Zener diode (not shown) may be provided between the bridge rectifier and the charge storage element) restricting current flow between the first node and the third node (inherent property of a diode is to allow current to flow only one way)
It would have been obvious to one ordinarily skilled in the art prior to the effective filing date of the application to include the Zener diode disclosed by Williams to the circuitry disclosed by EDN.
One of ordinary skill in the art would’ve been motivated because this prevents over-charging of the storage element. (¶29L8-11)
Response to Arguments
Applicant's arguments filed 07/20/2026 have been fully considered but they are not persuasive.
Regarding claim 1, the applicant argued prior art US2014/0015424A1 hereinafter “Kraft” does not disclose the narrower version of the amendment claim 1, which is moot argument, as the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding claim 1, the applicant argued none of the prior art disclose the circuit disposed in the nosecap of the handheld tool, which is moot argument, as the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding claim 1, the applicant argued that “no storage element is claimed” and unclear why one ordinarily skilled in the art would see to prevent over-charging of an untaught element.
The examiner disagree, it is clear that EDN discloses capacitors C1 and C2, which both are energy storage element and can have potential to be over-charged, furthermore, a Zener diode also can provide overvoltage protection by absorbing extra voltage, which is another benefit/reason to include said element in the circuitry.
Regarding claim 10, the applicant argued that the prior art does not disclose “fourth node and collector of first BJT” are connected explicitly that the nodes in the prior art are connected through resistor R5; and that one ordinarily skilled in the art would understand a direct connection is implied.
The examiner disagree, the mere fact that applicant has to point out there is a distinction between “connected” and “directly connected” shows that by simply claiming “connected” does not mean “directly connected” thus the feature “directly connected” is not recited in the rejected claim(s).
Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Furthermore, the LEDs and Resistor R5 of EDN is clearly connected in series, meaning the arrangement of the elements can be rearranged without affecting the operation of the circuit, therefore, one ordinarily skilled in the art could re-arrange the resistor R5 to be connected between the 1st high pin and anode of the LED, thus making the cathode of the LED and the collector of Q2 directly connected without any other circuit element.
For the at least foregoing reason, all rejections are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAYMOND R CHAI whose telephone number is (571)270-0576. The examiner can normally be reached M-F 9:30AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 571-242-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Raymond R Chai/Primary Examiner, Art Unit 2845
Prosecution Insights