Prosecution Insights
Last updated: May 29, 2026
Application No. 18/973,869

CIRCUIT BOARD AND IMAGE FORMING APPARATUS

Non-Final OA §103
Filed
Dec 09, 2024
Priority
Dec 11, 2023 — JP 2023-208451
Examiner
GRAINGER, QUANA MASHELLE
Art Unit
2852
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Canon Kabushiki Kaisha
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
1024 granted / 1154 resolved
+20.7% vs TC avg
Minimal -4% lift
Without
With
+-3.9%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
18 currently pending
Career history
1178
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
60.4%
+20.4% vs TC avg
§102
32.6%
-7.4% vs TC avg
§112
4.9%
-35.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1154 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/9/2024 was considered by the examiner. Drawings The drawings filed on 12/9/2024 are acceptable for examination by the examiner. Title The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Objections Claims objected to because of the following informalities. Claims 1-11 recite in claim 1 that “a circuit board comprising: a first surface S1 configured so that a first electronic part 2 is mountable; a second surface different from the first surface, the second surface being configured so that a second electronic part is mountable; …” Thus, the electronic parts are not mounted in claim 1 and it is unclear if all the processes claimed in the claims, which do not recite that the electronic part is mounted, is actionable. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 5-6, and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over LAI et al. (US 2018/0343739 A1) in view of HATANO (US 2022/0151059 A1) in view of KOSAKA (US 2015/0055972 A1). LAI teaches regarding claims 1 and 13, a circuit board comprising: a first surface S1 configured so that a first electronic part 2 is mountable; a second surface S2 different from the first surface S1, the second surface S2 being configured so that a second electronic part 1 is mountable; a controller configured to generate: a first control signal to be input to the first electronic part to control a logical value of an output signal output by the first electronic part [0021-0022]; and a second control signal to be input to the second electronic part to control a logical value of an output signal output by the second electronic part [0030-0031]; and a first via [0027] configured to connect a wiring to which the output signal from the first electronic part is output and a wiring to which the output signal from the second electronic part is output. Regarding claim 11, a mounting region of the first electronic part and a mounting region of the second electronic part overlap at least partially when viewed from a normal direction of the first surface [0147]. Regarding claim 12, the first electronic part and the second electronic part are mounted exclusively (figure 1-2, [0021-0022]). Regarding claim 13, LIA teaches an image forming apparatus (an image forming apparatus; shown in figures 1-2) comprising: a load configured to perform at least part of image forming; and a circuit board 1, 2, wherein the circuit board includes a first surface S1 configured so that a first electronic part is mountable, a second surface S2 different from the first surface, the second surface S2 being configured so that a second electronic part is mountable, a controller [configured to generate a first control signal to be input to the first electronic part to control a logical value of an output signal output by the first electronic part and a second control signal to be input to the second electronic part to control a logical value of an output signal output by the second electronic part, and a first via configured to connect a wiring to which the output signal from the first electronic part is output and a wiring to which the output signal from the second electronic part is output]. LAI does not teach wherein a logical value of the first control signal and a logical value of the second control signal has an inverse relationship with each other. HATANO teaches different phases for input signals for electric parts on the first and second surfaces of the circuit board (figure 3, [0055]). KOSAKA teach a logical value of a first control signal and a logical value of a second control signal have an inverse relationship with each other (figures 3-4, 18, [0147]; KOSAKA uses a logical value, which is a method of communicating the value of signal phases). Regarding claim 5, the controller has a logical inversion unit, to which a control signal is input, configured to generate the second control signal by inverting the logical value of the first control signal input to the controller (inverting a signal to form a second inverted signal is commonly used; [0078]). Regarding claim 6, the output signal output from the first electronic part and the output signal output from the second electronic part are signals that control rotation of a motor (60, figure 3, the controller 60 controls motors 13, 21, 32; [0061]). Further regarding claim 13, discussed above, Kosaka teaches an image forming apparatus comprising: a controller configured to generate a first control signal to be input to the first electronic part to control a logical value of an output signal output by the first electronic part and a second control signal to be input to the second electronic part to control a logical value of an output signal output by the second electronic part (figures 3-4, 18, [0147]; KOSAKA used the logical value of the signal phases), wherein the logical value of the first control signal and the logical value of the second control signal have inverse relationship with each other (figures 3-4, 18, [0147]; KOSAKA used the logical value of the signal phases), and wherein the first electronic part is mounted on the circuit and the second electronic part is not mounted on the circuit (The mounted parts are a matter of design choice; figures 3-4, 18, [0147]; KOSAKA used the logical value of the signal phases). Regarding claim 14, the load is a motor, and wherein the output signal output from the first electronic part and the output signal output from the second electronic part are signals that control rotation of the motor (60, figure 3, the controller 60 controls motors 13, 21, 32; [0061]). LAI, HATANO, and KOSAKA are concerned with circuit boards for an image forming apparatus. LAI teaches a method of simplifying the circuit board layout. HATANO teaches a signal transmission device and method. KOSAKA teach a power supply device with load protection. The rationale for combining the teachings of HATANO and KOSAKA with the teachings of LAI relates to the rationale of combining prior art elements according to known methods to yield predictable results. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use the teaching of HATANO with the teaching of LAI to obtain a conventional method of managing signal for electronic part on a two-surface circuit board. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use the teaching of KOSAKA with the teaching of LAI to obtain power supply management for an image forming device. Allowable Subject Matter Claims 2-4, 7-10, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 2 recites the circuit board according to claim 1, wherein the first electronic part comprises a first terminal from which a positive phase signal of a first complementary signal is output as the output signal, and wherein the second electronic part comprises a second terminal from which a positive phase signal of a second complementary signal is output as the output signal. Claim 3 recites the circuit board according to claim 2, further comprising a second via, wherein the first electronic part comprises a third terminal from which a negative phase signal of the first complementary signal is output as the output signal, wherein the second electronic part comprises a fourth terminal from which a negative phase signal of second complementary signal is output as the output signal, and wherein the second via is connected to the third terminal and the fourth terminal. Claim 4 recites the circuit board according to claim 3, wherein an arrangement of the first and third terminals in the first electronic part and an arrangement of the second and fourth terminals in the second electronic part are designed to be reversed by mounting the first and second electronic parts on different surfaces. Claim 7 recites the circuit board according to claim 6, wherein the controller is configured to: output the first control signal to the first electronic part to control a direction of the rotation of the motor in a first direction in a case where the first electronic part is mounted; and output the second control signal to the second electronic part to control a direction of the rotation of the motor in a second direction opposite to the first direction in a case where the second electronic part is mounted. Claim 8 recites the circuit board according to claim 1, further comprising: a judgment unit configured to output a judgment signal indicating which of the first and second electronic parts is mounted. Claim 9 recites the circuit board according to claim 8, wherein the controller is configured to transmit one of the first control signal and the second control signal based on the judgment signal acquired from the judgment unit. Claim 10 recites the circuit board according to claim 8, wherein the judgment unit is configured to: output the judgment signal with a first voltage value in a case where the first electronic part is mounted; and output the judgment signal with a second voltage value different from the first voltage value in a case where the second electronic part is mounted. Claim 15 recites the image forming apparatus according to claim 14, wherein the controller is configured to: output the first control signal to the first electronic part to control a direction of the rotation of the motor in a first direction in a case where the first electronic part is mounted; and output the second control signal to the second electronic part to control a direction of the rotation of the motor in a second direction opposite to the first direction in a case where the second electronic part is mounted. Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. INOUE et al. (US 2004/0126124 A1) teaches digital motor driver. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUANA GRAINGER whose telephone number is (571)272-2135. The examiner can normally be reached on Monday - Friday, 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Walter Lindsay can be reached on 571-272-1674. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /QUANA GRAINGER/Primary Examiner, Art Unit 2852 QG
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Prosecution Timeline

Dec 09, 2024
Application Filed
Apr 29, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
85%
With Interview (-3.9%)
2y 0m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1154 resolved cases by this examiner. Grant probability derived from career allowance rate.

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