Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant application having Application No. 18/973,875 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
INFORMATION CONCERNING DRAWINGS
The applicant’s drawings submitted are acceptable for examination purposes.
STATUS OF CLAIM FOR PRIORITY IN THE APPLICATION
Application No. 18973875 filed 12/09/2024 claims foreign priority to 10-2024-0053898, filed 04/23/2024.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement(s) dated 12/9/2024 is/are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy (copies) of the PTOL-1449(s) initialed and dated by the examiner is/are attached to the instant office action.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 8, 11-12, 15-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Confalonieri et al. (US 2022/0261363) in view of Von Bokern et al. (US 2014/0181894).
1. A storage system comprising: a host device; and [host 103 (fig. 1 and related text)]
a storage device connected to the host device through both a main link and a sub link, wherein the storage device includes: [Confalonieri teaches “Confalonieri teaches “[0034] As shown in FIG. 2, a front end portion 204 can include an interface 206 that includes multiple I/O lanes 202-1, 202-2, . . . , 202-N (individually or collectively referred to as I/O lanes 202), as well as circuitry 208 to manage the interface 206…The interface 206 can receive data from a host (e.g., the host 103 shown in FIG. 1) through the of I/O lanes 202.” Where I/O lanes 202 are interpreted to correspond to the claimed main link. “[0045] The memory controller 200 can include a management unit 234 configured to initialize, configure, and/or monitor characteristics of the memory controller 200. In some embodiments, the management unit 234 includes an I/O bus 238 (interpreted to correspond to the claimed sub link) to manage out-of-band data and/or commands… An endpoint of the management unit 234 can be exposed to the host system (e.g., the host 103 shown in FIG. 1) to manage data.”]
a nonvolatile memory device configured to store data; and [Confalonieri teaches memory devices 126, 128 (fig. 1 and related text) 226, 228 (fig. 2 and related text) where memory devices 128, 228 may be configured as FeRAM nonvolatile memory devices (pars. 0003, 0031, 0033)]
a storage controller package configured to control the nonvolatile memory device based on information from the host device, and wherein the storage controller package includes: [Confalonieri teaches controller 200 (fig. 2 and related text)]
an on-chip bus; a host interface connected to the on-chip bus and the main link; [Confalonieri teaches I/O bus (fig. 5 and related text) connected to interface 206 (508 in fig. 5) and I/O lanes 202 (figs. 1 and 2 and related text) where “The bandwidths 556-1, 556-2, 556-3, 556-4, 556-5, 556-6, 556-7, 556-8, 556-9, 556-10, 556-11, 556-12 (individually or collectively referred to as bandwidth 556) of the I/O bus between components in the front end portion 504, the central controller portion 510, and the back end portion 519 of a memory controller are shown.” (fig. 5 and related text)]
a memory interface connected to the on-chip bus and the nonvolatile memory device; [Confalonieri teaches back end interface 119 (fig. 1 and related text) connect to nonvolatile memory 128 and I/O bus depicted in fig. 5 and related text]
a storage processor connected to the on-chip bus, and configured to perform an in-band communication with the host device through the on-chip bus, the host interface and the main link; and [Confalonieri teaches “[0034] As shown in FIG. 2, a front end portion 204 can include an interface 206 that includes multiple I/O lanes 202-1, 202-2, . . . , 202-N (individually or collectively referred to as I/O lanes 202), as well as circuitry 208 to manage the interface 206. The interface 206 can be a peripheral component interconnect express (PCIe) 5.0 interface coupled to the I/O lanes 202. In some embodiments, the memory controller 200 can receive access requests involving at least one of the cache memory 212, the first type of memory device 226, and/or the second type of memory device 228 via the PCIe 5.0 interface 206 according to a CXL protocol. The interface 206 can receive data from a host (e.g., the host 103 shown in FIG. 1) through the of I/O lanes 202. The interface management circuitry 208 may use CXL protocols to manage the interface 206.” Where the communication via I/O lanes 202 is interpreted as in-band and I/O lanes 202 are interpreted to correspond to the claimed main link where all items are connected via I/O bus depicted in fig. 5 and related text]; however, Confalonieri does not expressly refer to the interface management circuit as a storage processor for in-band communication
a microcontroller connected to the on-chip bus and the sub link, and configured to perform an out-of-band communication with the host device through the sub link [Confalonieri teaches “[0045] The memory controller 200 can include a management unit 234 configured to initialize, configure, and/or monitor characteristics of the memory controller 200. In some embodiments, the management unit 234 includes an I/O bus 238 (interpreted to correspond to the claimed sub link) to manage out-of-band data and/or commands, a management unit controller 240 to execute instructions associated with initializing, configuring, and/or monitoring the characteristics of the memory controller 200, and a management unit memory 242 to store codes and/or data associated with managing and/or monitoring the characteristics of the memory controller 200. An endpoint of the management unit 234 can be exposed to the host system (e.g., the host 103 shown in FIG. 1) to manage data.” Where all items are connected via I/O bus depicted in fig. 5 and related text]; however, Confalonieri does not expressly refer to the management unit controller 240 which manages out of band communication as a microcontroller.
Regarding the limitations of the interface management circuit which is connected to host via I/O lanes 202 being implemented as a processor for in band communication and the management unit controller 240 which manages out of band communication being implemented as a microcontroller; Von Bokern teaches [“Accordingly, management microcontroller 235 can have direct access to network interfaces of the system device. In some implementations, management microcontroller can run a fully independent, out-of-band communication channel (such as through a dedicated TCP/IP stack) allowing the microcontroller to inspect and receive packets not processed by the CPU, as well as inspect inbound and/or outbound traffic before the CPU has access to it. Effectively, two logical network connections can be maintained on a single physical networking connector of the device 205, one in-band through the CPU (e.g., 232) and the other out-of-band through the management microcontroller 235.” (par. 0026) thus teaching in-band communication via CPU 232 (see fig. 2 and related text) and “[0025] In one example implementation, a system device 205 can include a chipset 230 that includes a processor 232, such as a central processing unit (CPU), and memory 234, such as memory including system memory utilized by the CPU and accessible to an operating system (e.g., 250) of the system device 205, among other examples. The chipset 230, in some examples, can additionally include a management microcontroller 235 that can provide secured processing functionality to perform management tasks outside of (or below) the control and instructions of the operating system. An example management microcontroller 235, in some implementations, can run a lightweight microkernel operating system that provides a low-power, out-of-band management controller.” Where management microcontroller is interpreted as Corresponding to the claimed out-band microcontroller].
Confalonieri and Vo Bokern are analogous art because they are from the same field of endeavor of memory access and control as well as data communication/transfer.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Confalonieri to have the interface management circuit which is connected to host via I/O lanes 202 being implemented as a processor for in band communication and the management unit controller 240 which manages out of band communication being implemented as a microcontroller as taught by Von Bokern since doing so would provide the benefits of [“Network filters in communication manager 248 can be utilized to programmatically redirect traffic to either a host operating system interface or the interface of the management controller at micromanagement controller 235, for instance, based on port numbers, among other implementations. An independent network communication channel can allow the management microcontroller 235 (and management controller implemented using the management microcontroller) to perform a variety of communications and remote management functions that can take place effectively potentially at all times without regard to the state of the operating system, for example.” (par. 0026)]
Therefore, it would have been obvious to combine Confalonieri with Von Bokern for the benefit of creating a storage system/method to obtain the invention as specified in claim 1.
4. The storage system of claim 1, wherein the microcontroller is included in the storage controller package as a core-in-package structure such that the microcontroller is integrated in a single semiconductor chip with other components of the storage controller package [Confalonieri teaches “[0045] The memory controller 200 can include a management unit 234 configured to initialize, configure, and/or monitor characteristics of the memory controller 200. In some embodiments, the management unit 234 includes an I/O bus 238 (interpreted to correspond to the claimed sub link) to manage out-of-band data and/or commands, a management unit controller 240 to execute instructions associated with initializing, configuring, and/or monitoring the characteristics of the memory controller 200, and a management unit memory 242 to store codes and/or data associated with managing and/or monitoring the characteristics of the memory controller 200.” Thus, controller 240, part of management unit 234 is included in controller package 200]. Von Bokern teaches [“The chipset 230, in some examples, can additionally include a management microcontroller 235 that can provide secured processing functionality to perform management tasks outside of (or below) the control and instructions of the operating system. An example management microcontroller 235, in some implementations, can run a lightweight microkernel operating system that provides a low-power, out-of-band management controller.” Where management microcontroller is interpreted as Corresponding to the claimed out-band microcontroller” (par. 0025) thus the microcontroller included in the chipset package 230]
8. The storage system of claim 1, wherein the microcontroller is configured to access the nonvolatile memory device through the on-chip bus and the memory interface regardless of an operation of the storage processor [Confalonieri teaches “[0034] As shown in FIG. 2, a front end portion 204 can include an interface 206 that includes multiple I/O lanes 202-1, 202-2, . . . , 202-N (individually or collectively referred to as I/O lanes 202), as well as circuitry 208 to manage the interface 206. The interface 206 can be a peripheral component interconnect express (PCIe) 5.0 interface coupled to the I/O lanes 202. In some embodiments, the memory controller 200 can receive access requests involving at least one of the cache memory 212, the first type of memory device 226, and/or the second type of memory device 228 via the PCIe 5.0 interface 206 according to a CXL protocol. The interface 206 can receive data from a host (e.g., the host 103 shown in FIG. 1) through the of I/O lanes 202. The interface management circuitry 208 may use CXL protocols to manage the interface 206.” Where the communication via I/O lanes 202 is interpreted as in-band and I/O lanes 202 are interpreted to correspond to the claimed main link where all items are connected via I/O bus depicted in fig. 5 and related text. “[0045] The memory controller 200 can include a management unit 234 configured to initialize, configure, and/or monitor characteristics of the memory controller 200. In some embodiments, the management unit 234 includes an I/O bus 238 (interpreted to correspond to the claimed sub link) to manage out-of-band data and/or commands, a management unit controller 240 to execute instructions associated with initializing, configuring, and/or monitoring the characteristics of the memory controller 200, and a management unit memory 242 to store codes and/or data associated with managing and/or monitoring the characteristics of the memory controller 200.” ]. Von Bokern teaches [“Accordingly, management microcontroller 235 can have direct access to network interfaces of the system device. In some implementations, management microcontroller can run a fully independent, out-of-band communication channel (such as through a dedicated TCP/IP stack) allowing the microcontroller to inspect and receive packets not processed by the CPU, as well as inspect inbound and/or outbound traffic before the CPU has access to it. Effectively, two logical network connections can be maintained on a single physical networking connector of the device 205, one in-band through the CPU (e.g., 232) and the other out-of-band through the management microcontroller 235.” (par. 0026) thus teaching in-band communication via CPU 232 “The chipset 230, in some examples, can additionally include a management microcontroller 235 that can provide secured processing functionality to perform management tasks outside of (or below) the control and instructions of the operating system. An example management microcontroller 235, in some implementations, can run a lightweight microkernel operating system that provides a low-power, out-of-band management controller.” Where management microcontroller is interpreted as Corresponding to the claimed out-band microcontroller” (par. 0025)].
11. The storage system of claim 1, wherein the storage device further includes: a dynamic random access memory (DRAM) configured to store data, and wherein the storage controller package further includes; a DRAM interface connected to the DRAM and the on-chip bus [Confalonieri teaches memory devices 126 may include DRAM which are connected to controller via interface (par. 0026) connected to back end interface including media controller (see figs. 1-2 and related text), all connected via I/O bus shown in fig. 5 and related text].
12. The storage system of claim 11, wherein the microcontroller is configured to access the DRAM through the on-chip bus and the DRAM interface regardless of an operation of the storage processor [Confalonieri teaches memory devices 126 may include DRAM which are connected to controller via interface (par. 0026) connected to back end interface including media controller (see figs. 1-2 and related text), all connected via I/O bus shown in fig. 5 and related text where “[0012] Systems, apparatuses, and methods related to a controller for managing multiple types of memory are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit that can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics.” Thus, in order to manage the memory devices, the management unit must access the memory devices. “[0045] The memory controller 200 can include a management unit 234 configured to initialize, configure, and/or monitor characteristics of the memory controller 200. In some embodiments, the management unit 234 includes an I/O bus 238 (interpreted to correspond to the claimed sub link) to manage out-of-band data and/or commands, a management unit controller 240 to execute instructions associated with initializing, configuring, and/or monitoring the characteristics of the memory controller 200, and a management unit memory 242 to store codes and/or data associated with managing and/or monitoring the characteristics of the memory controller 200. An endpoint of the management unit 234 can be exposed to the host system (e.g., the host 103 shown in FIG. 1) to manage data” ].
15. The storage system of claim 1, wherein the main link includes a peripheral component interconnect express (PCIe) bus, and the sub link includes a system management bus (SMBUS) [Confalonieri teaches “[0034] As shown in FIG. 2, a front end portion 204 can include an interface 206 that includes multiple I/O lanes 202-1, 202-2, . . . , 202-N (individually or collectively referred to as I/O lanes 202), as well as circuitry 208 to manage the interface 206. The interface 206 can be a peripheral component interconnect express (PCIe) 5.0 interface coupled to the I/O lanes 202. In some embodiments, the memory controller 200 can receive access requests involving at least one of the cache memory 212, the first type of memory device 226, and/or the second type of memory device 228 via the PCIe 5.0 interface 206 according to a CXL protocol. The interface 206 can receive data from a host (e.g., the host 103 shown in FIG. 1) through the of I/O lanes 202. The interface management circuitry 208 may use CXL protocols to manage the interface 206.” Where I/O lanes 202 correspond to the main link management unit 234 including I/O bus 238 for out of band communication (par. 0045) “[0046] As stated above, the I/O bus 238 can be configured to transfer out-of-band data and/or commands. In some embodiments, the I/O bus 238 can be a System Management Bus (SMBus).” Where I/O bus 238 corresponds to the claimed sub link].
16. A storage device comprising: a nonvolatile memory device configured to store data; and a storage controller package configured to control the nonvolatile memory device based on information from a host device, wherein the storage controller package includes: an on-chip bus; a host interface connected to the on-chip bus and a main link; a memory interface connected to the on-chip bus and the nonvolatile memory device; a storage processor connected to the on-chip bus, and configured to perform an in-band communication with the host device through the on-chip bus, the host interface and the main link; and a microcontroller connected to the on-chip bus and a sub link, and configured to perform an out-of-band communication with the host device through the sub link [The rationale in the rejection of claim 1 is herein incorporated].
18. The storage device of claim 16, wherein the storage processor and the microcontroller are configured to operate independently based on respective firmware [The rationale in the rejection of claim 7 is herein incorporated].
19. The storage device of claim 1, wherein the microcontroller is configured to access the nonvolatile memory device through the on-chip bus and the memory interface regardless of an operation of the storage processor [Confalonieri teaches memory devices 128 may include FeRAM which are connected to controller via interface (par. 0026) connected to back end interface including media controller (see figs. 1-2 and related text), all connected via I/O bus shown in fig. 5 and related text where “[0012] Systems, apparatuses, and methods related to a controller for managing multiple types of memory are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit that can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics.” Thus, in order to manage the memory devices, the management unit must access the memory devices. “[0045] The memory controller 200 can include a management unit 234 configured to initialize, configure, and/or monitor characteristics of the memory controller 200. In some embodiments, the management unit 234 includes an I/O bus 238 (interpreted to correspond to the claimed sub link) to manage out-of-band data and/or commands, a management unit controller 240 to execute instructions associated with initializing, configuring, and/or monitoring the characteristics of the memory controller 200, and a management unit memory 242 to store codes and/or data associated with managing and/or monitoring the characteristics of the memory controller 200. An endpoint of the management unit 234 can be exposed to the host system (e.g., the host 103 shown in FIG. 1) to manage data”].
20. A storage device comprising: a nonvolatile memory device configured to store data; and [Confalonieri teaches memory devices 126, 128 (fig. 1 and related text) 226, 228 (fig. 2 and related text) where memory devices 128, 228 may be configured as FeRAM nonvolatile memory devices (pars. 0003, 0031, 0033)]
a storage controller package configured to control the nonvolatile memory device based on information from a host device, wherein the storage controller package includes: [Confalonieri teaches storage controller 200 (fig. 2 and related text)]
a storage processor configured to perform an in-band communication with the host device through a main link connected to the host device; and [Confalonieri teaches “[0034] As shown in FIG. 2, a front end portion 204 can include an interface 206 that includes multiple I/O lanes 202-1, 202-2, . . . , 202-N (individually or collectively referred to as I/O lanes 202), as well as circuitry 208 to manage the interface 206. The interface 206 can be a peripheral component interconnect express (PCIe) 5.0 interface coupled to the I/O lanes 202. In some embodiments, the memory controller 200 can receive access requests involving at least one of the cache memory 212, the first type of memory device 226, and/or the second type of memory device 228 via the PCIe 5.0 interface 206 according to a CXL protocol. The interface 206 can receive data from a host (e.g., the host 103 shown in FIG. 1) through the of I/O lanes 202. The interface management circuitry 208 may use CXL protocols to manage the interface 206.” Where the communication via I/O lanes 202 is interpreted as in-band and I/O lanes 202 are interpreted to correspond to the claimed main link]; however, Confalonieri does not expressly refer to the interface management circuit as a storage processor for in-band communication
a microcontroller configured to perform an out-of-band communication with the host device through a sub link connected to the host device [Confalonieri teaches [0045] The memory controller 200 can include a management unit 234 configured to initialize, configure, and/or monitor characteristics of the memory controller 200. In some embodiments, the management unit 234 includes an I/O bus 238 (interpreted to correspond to the claimed sub link) to manage out-of-band data and/or commands, a management unit controller 240 to execute instructions associated with initializing, configuring, and/or monitoring the characteristics of the memory controller 200, and a management unit memory 242 to store codes and/or data associated with managing and/or monitoring the characteristics of the memory controller 200. An endpoint of the management unit 234 can be exposed to the host system (e.g., the host 103 shown in FIG. 1) to manage data.”]; however, Confalonieri does not expressly refer to the management unit controller 240 which manages out of band communication as a microcontroller.
Regarding the limitations of the interface management circuit which is connected to host via I/O lanes 202 being implemented as a processor for in band communication and the management unit controller 240 which manages out of band communication being implemented as a microcontroller; Von Bokern teaches [“Accordingly, management microcontroller 235 can have direct access to network interfaces of the system device. In some implementations, management microcontroller can run a fully independent, out-of-band communication channel (such as through a dedicated TCP/IP stack) allowing the microcontroller to inspect and receive packets not processed by the CPU, as well as inspect inbound and/or outbound traffic before the CPU has access to it. Effectively, two logical network connections can be maintained on a single physical networking connector of the device 205, one in-band through the CPU (e.g., 232) and the other out-of-band through the management microcontroller 235.” (par. 0026) thus teaching in-band communication via CPU 232 (see fig. 2 and related text) and “[0025] In one example implementation, a system device 205 can include a chipset 230 that includes a processor 232, such as a central processing unit (CPU), and memory 234, such as memory including system memory utilized by the CPU and accessible to an operating system (e.g., 250) of the system device 205, among other examples. The chipset 230, in some examples, can additionally include a management microcontroller 235 that can provide secured processing functionality to perform management tasks outside of (or below) the control and instructions of the operating system. An example management microcontroller 235, in some implementations, can run a lightweight microkernel operating system that provides a low-power, out-of-band management controller.” Where management microcontroller is interpreted as Corresponding to the claimed out-band microcontroller].
Confalonieri and Vo Bokern are analogous art because they are from the same field of endeavor of memory access and control as well as data communication/transfer.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Confalonieri to have the interface management circuit which is connected to host via I/O lanes 202 being implemented as a processor for in band communication and the management unit controller 240 which manages out of band communication being implemented as a microcontroller as taught by Von Bokern since doing so would provide the benefits of [“Network filters in communication manager 248 can be utilized to programmatically redirect traffic to either a host operating system interface or the interface of the management controller at micromanagement controller 235, for instance, based on port numbers, among other implementations. An independent network communication channel can allow the management microcontroller 235 (and management controller implemented using the management microcontroller) to perform a variety of communications and remote management functions that can take place effectively potentially at all times without regard to the state of the operating system, for example.” (par. 0026)].
Therefore, it would have been obvious to combine Confalonieri with Von Bokern for the benefit of creating a storage system/method to obtain the invention as specified in claim 20.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Confalonieri et al. (US 2022/0261363) in view of Von Bokern et al. (US 2014/0181894) as applied in the rejection of claim 1 above, and further in view of Ha et al. (US 2009/0057862).
2. The storage system of claim 1, wherein the microcontroller is included in the storage controller package as a package-in-package structure such that the microcontroller is included in a first package, other components of the storage controller package are included in a second package, and the first package and the second package are mounted on an interposer [Confalonieri teaches “[0045] The memory controller 200 can include a management unit 234 configured to initialize, configure, and/or monitor characteristics of the memory controller 200. In some embodiments, the management unit 234 includes an I/O bus 238 (interpreted to correspond to the claimed sub link) to manage out-of-band data and/or commands, a management unit controller 240 to execute instructions associated with initializing, configuring, and/or monitoring the characteristics of the memory controller 200, and a management unit memory 242 to store codes and/or data associated with managing and/or monitoring the characteristics of the memory controller 200.” Thus, controller 240, part of management unit 234 is included in controller package 200]. Von Bokern teaches [“The chipset 230, in some examples, can additionally include a management microcontroller 235 that can provide secured processing functionality to perform management tasks outside of (or below) the control and instructions of the operating system. An example management microcontroller 235, in some implementations, can run a lightweight microkernel operating system that provides a low-power, out-of-band management controller.” Where management microcontroller is interpreted as Corresponding to the claimed out-band microcontroller” (par. 0025) thus the microcontroller included in the chipset package 230] thus, teaching structures corresponding to the claimed microcontroller in controller but the combination does not expressly disclose a package-in-package structure mounted on an interposer; however, regarding these limitation Ha teaches [“[0026] Referring now to FIG. 2, therein is shown a cross-sectional view of the integrated circuit package-in-package system 100 along line 2-2 of FIG. 1. The cross-sectional view depicts an integrated circuit package system 206 having a carrier interposer 208. The carrier interposer 208 may serve a number of functions. For example, the carrier interposer 208 may function as the carrier for the integrated circuit package system 206. Another example, the carrier interposer 208 may function as an interposer for the integrated circuit package-in-package system 100.”].
Confalonieri, Vo Bokern and Ha are analogous art because they are from the same field of endeavor of memory access and control as well as data communication/transfer and integrated circuit design.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Confalonieri and Von Bokern to implement the controller and microcontroller as package-in-package system on a interposer such as those as taught by Ha since doing so would provide the benefits of [“[0033] It has been discovered that the present invention provides an integrated circuit package-in-package system having improved component integration while also reducing the form factor of the resultant package.”].
Therefore, it would have been obvious to combine Confalonieri with Von Bokern and Ha for the benefit of creating a storage system/method to obtain the invention as specified in claim 2.
3. The storage system of claim 2, wherein an input-output terminal of the second package is electrically connected to an input-output terminal of the first package through a conduction line that is formed in the interposer, wherein the on-chip bus is included in the second package [Confalonieri teaches “[0045] The memory controller 200 can include a management unit 234 configured to initialize, configure, and/or monitor characteristics of the memory controller 200. In some embodiments, the management unit 234 includes an I/O bus 238 (interpreted to correspond to the claimed sub link) to manage out-of-band data and/or commands, a management unit controller 240 to execute instructions associated with initializing, configuring, and/or monitoring the characteristics of the memory controller 200, and a management unit memory 242 to store codes and/or data associated with managing and/or monitoring the characteristics of the memory controller 200.” Thus, controller 240, part of management unit 234 is included in controller package 200 where all circuit items are connected via I/O bus in fig. 5 and related text, corresponding the claimed on-chip bus]. Von Bokern teaches [“The chipset 230, in some examples, can additionally include a management microcontroller 235 that can provide secured processing functionality to perform management tasks outside of (or below) the control and instructions of the operating system. An example management microcontroller 235, in some implementations, can run a lightweight microkernel operating system that provides a low-power, out-of-band management controller.” Where management microcontroller is interpreted as Corresponding to the claimed out-band microcontroller” (par. 0025) thus the microcontroller included in the chipset package 230] thus, teaching structures corresponding to the claimed microcontroller in controller. [Ha teaches “[0005] This increased integrated circuit density, has led to the development of multi-chip packages in which more than one integrated circuit can be packaged. Each package provides mechanical support for the individual integrated circuits and one or more layers of interconnect lines that enable the integrated circuits to be connected electrically to surrounding circuitry.” “[0026] Referring now to FIG. 2, therein is shown a cross-sectional view of the integrated circuit package-in-package system 100 along line 2-2 of FIG. 1. The cross-sectional view depicts an integrated circuit package system 206 having a carrier interposer 208. The carrier interposer 208 may serve a number of functions. For example, the carrier interposer 208 may function as the carrier for the integrated circuit package system 206. Another example, the carrier interposer 208 may function as an interposer for the integrated circuit package-in-package system 100.”], where it would have been obvious to have the bus connecting all devices included in the second package since doing so would allow for flexibility of design and rearrangement of items, where it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Confalonieri et al. (US 2022/0261363) in view of Von Bokern et al. (US 2014/0181894) as applied in the rejection of claim 1 above, and further in view of Montero et al. (US 2025/0004538).
7. The storage system of claim 1, wherein the storage processor and the microcontroller are configured to operate independently based on respective firmware [Confalonieri teaches interface management circuit which may use CXL protocols to manage the interface 206 (par. 0034) “ a management unit memory 242 to store codes and/or data associated with managing and/or monitoring the characteristics of the memory controller 200.” (par. 0045) “[0047] The management unit 234 can include a management unit controller 240. In some embodiments, the management unit controller 240 can be a controller that meets the Joint Test Action Group (JTAG) standard and operate according to an Inter-Integrate Circuit (I.sup.2C or I.sup.3C) protocol, and auxiliary I/O circuitry. As used herein, the term “JTAG” generally refers to an industry standard for verifying designs and testing printed circuity boards after manufacture. As used herein, the term “I.sup.2C” generally refers to a serial protocol for a two-wire interface to connect low-speed devices like microcontrollers, I/O interfaces, and other similar peripherals in embedded systems. In some embodiments, the auxiliary I/O circuitry can couple the management unit 234 to the memory controller 200. Further, firmware for operating the management unit can be stored in the management unit memory 242. In some embodiments, the management unit memory 242 can be a flash memory such as flash NOR memory or other persistent flash memory device.” Von Bokern teaches processor 232 and management controller 235 operating independently, one of ordinary skill in the art would recognize each device has its own firmware or operating software (fig.2 and related text)] but the combination of Confalonieri and Von Bokern does not expressly refer to respective firmware; however, regarding these limitations, Montero teaches [OOB boot Rom where “[0137] OOB ROM 605 includes program instructions and/or firmware that enable OOB MCU 604 to start and maintain its operations (e.g., Real-Time OS or “RTOS” code), including certain operations described in more detail below. Integrated SRAM 606 is usable by OOB MCU 604 as its working memory during such operations.” And “OEM-owned firmware may reside primary within an EC 109's domain” (par. 0199)].
Confalonieri, Vo Bokern and Montero are analogous art because they are from the same field of endeavor of memory access and control as well as data communication/transfer and integrated circuit design.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Confalonieri and Von Bokern to have respective firmware in the processor and the out of band microcontroller of the combination in the manner Montero teaches respective firmware since doing so would allow for efficient operation of each device.
Therefore, it would have been obvious to combine Confalonieri with Von Bokern and Montero for the benefit of creating a storage system/method to obtain the invention as specified in claim 7.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Confalonieri et al. (US 2022/0261363) in view of Von Bokern et al. (US 2014/0181894) as applied in the rejection of claim 1 above, and further in view of Zhang et al. (US 2013/0205063).
10. The combination of Confalonieri and Von Bokern teaches The storage system of claim 1, but does not expressly disclose wherein the microcontroller is configured to, when the storage processor does not operate, receive a recovery request from the host device through the out-of-band communication via the sub link, and generate a signal to restart firmware of the storage processor based on the recovery request; however, regarding these limitations, [Zhang teaches “Systems and methods are provided that may be implemented for out-of-band backup and/or restore of information handling system components. Such out-of-band backup and restore operations may be performed, in one embodiment, to backup and/or restore hardware profile information such as firmware images and corresponding system configuration information.” (Abstract) “[0005] The disclosed out-of-band backup and restore operations may be performed in one embodiment using one or more out-of-band processing devices that are separate and independent from any in-band host central processing unit (CPU) that runs the host OS of the information handling system, and without management of any application executing with a host OS on the host CPU. Moreover, a remote system manager may also be provided with the ability to manage and control an out-of-band processing device from across an out-of-band network to perform out-of-band firmware backup and/or restore operations. Examples of system firmware information that may be backed up and/or restored using the disclosed systems and methods include, but are not limited to, firmware and configurations therefor, e.g., such as system platform basic input/output system (BIOS) firmware, motor control (MC) firmware, redundant array of independent disks (RAID) firmware, network interface card (NIC) firmware, Remote Access Controller firmware, etc. Thus, the disclosed out-of-band backup and restore operations may be implemented, for example, to restore hardware profile information and then load an operating system (OS) such a Linux, or configure/reconfigure RAID settings (e.g., back to RAID 1 configuration) on an information handling system. It will be understood that a restore request may also include a request to initially load hardware profile information for the first time, as well as request to reload previously backed up hardware profile information.” “program and utilize an out-of-band processor to perform a full out-of-band firmware and firmware configuration backup in response to a single command, and then to restore the firmware and/or firmware configurations to its original state and/or settings as represented by the contents of the backup with a subsequent command.” (par. 0007)].
Confalonieri, Vo Bokern and Zhang are analogous art because they are from the same field of endeavor of memory access and control as well as data communication/transfer and integrated circuit design.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Confalonieri and Von Bokern to have as taught by Zhang since doing so would provide the benefits of [allowing for “program and utilize an out-of-band processor to perform a full out-of-band firmware and firmware configuration backup in response to a single command, and then to restore the firmware and/or firmware configurations to its original state and/or settings as represented by the contents of the backup with a subsequent command.” (par. 0007)].
Therefore, it would have been obvious to combine Confalonieri with Von Bokern and Zhang for the benefit of creating a storage system/method to obtain the invention as specified in claim 10.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Confalonieri et al. (US 2022/0261363) in view of Von Bokern et al. (US 2014/0181894) as applied in the rejection of claim 1 above, and further in view of Trantham et al. (US 20230305972) and Olarig et al. (US 20210382627).
13. The combination of Confalonieri and Von Bokern teaches The storage system of claim 1, but does not expressly disclose wherein the storage device further includes: an electrically erasable programmable read-only memory (EEPROM) configured to store product information including vital product data of the storage device, and wherein the microcontroller is configured to receive the product information from the EEPROM through an inter-integrated circuit (I2C) link, and transfer the product information to the host device through the out-of-band communication via the sub link; however, regarding these limitations, Trantham teaches [“[0027] The memory controller 206 can include the interface 204, memory controller logic 207, a microprocessor 210, as well as other circuits, such as shown. Further, the memory controller 206 can include a memory controller interface 212 configured to translate communications, received or sent over the interface 204, to the memory controller logic 207. Memory controller logic 207 can switch/multiplex the operation to the appropriate data channel. Further, memory controller logic 207 can split/combine the data to and from multiple channels if desired. The memory controller interface 212 may also communicate other commands to the microprocessor 210, such as CXL.io commands in a CXL device. The memory controller 206 and memory module 202 may have other communication channels with the host system 220, such as SMBus utilizing Inter-Integrated Circuit (I.sup.2C)/I.sup.3C busses for out-of-band communication of vital product data, such as performance and other characteristics of the module.”] but Trantham does not expressly disclose the vital product data for the storage device stored in an EEPROM.
Confalonieri, Vo Bokern and Trantham are analogous art because they are from the same field of endeavor of memory access and control as well as data communication/transfer and integrated circuit design.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Confalonieri and Von Bokern to have product information including vital product data of the storage device, and wherein the microcontroller is configured to receive the product information … through an inter-integrated circuit (I2C) link, and transfer the product information to the host device through the out-of-band communication via the sub link as taught by Trantham since doing so would provide the benefits of [facilitating configuring of the storage system].
The combination Confalonieri, Von Bokern and Trantham does not expressly disclose the vital product data for the storage device stored in an EEPROM; however, regarding these limitations, Olarig teaches [“For example, EEPROM 345 may store VPD 355. VPD 355 may be used by Network-Attached SSDs 320, 325, and 330, and by BMC 125, to store information pertinent to those devices. More particularly, EEPROM 345 may store separate VPD 355 for each such device.” (par. 0050)]
Confalonieri, Vo Bokern, Trantham and Olarig are analogous art because they are from the same field of endeavor of memory access and control as well as data communication/transfer and integrated circuit design.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Confalonieri, Von Bokern and Trantham to store the vital product information in an EEPROM as taught by Olarig since doing so would facilitate self configuration as [“[0051] VPD 355 has several uses. In some embodiments of the inventive concept, VPD 355 may be used to store pertinent information for each device, which may be used in self-configuration.“].
Therefore, it would have been obvious to combine Confalonieri with Von Bokern, Trantahm and Olarig for the benefit of creating a storage system/method to obtain the invention as specified in claim 13.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Confalonieri et al. (US 2022/0261363) in view of Von Bokern et al. (US 2014/0181894) as applied in the rejection of claim 1 above, and further in view of Maity et al. (US 20150149750).
14. The storage system of claim 1, wherein the storage device further includes: one or more sensors configured to provide state information including at least one of temperature information, humidity information, voltage information or current information of the storage device, and wherein the microcontroller is configured to receive the state information from the one or more sensors through an inter-integrated circuit (I2C) link, and [Confalonieri teaches “[0045] The memory controller 200 can include a management unit 234 configured to initialize, configure, and/or monitor characteristics of the memory controller 200. In some embodiments, the management unit 234 includes an I/O bus 238 to manage out-of-band data and/or commands, a management unit controller 240 to execute instructions associated with initializing, configuring, and/or monitoring the characteristics of the memory controller 200, and a management unit memory 242 to store codes and/or data associated with managing and/or monitoring the characteristics of the memory controller 200. An endpoint of the management unit 234 can be exposed to the host system (e.g., the host 103 shown in FIG. 1) to manage data. In some embodiments, the characteristics monitored by the management unit 234 can include a voltage supplied to the memory controller 200 or a temperature measured by an external sensor, or both. Further, the management unit 234 can include an advanced high-performance bus (AHB) interconnect 236 to couple different components of the management unit 234.” Where links connecting sensors to management unit are withing the integrated circuit and are interpreted as integrated circuit links] but does not expressly disclose transfer the state information to the host device through the out-of-band communication via the sub link; however, regarding these limitations [“[0005] Generally, a service processor (SP) or a baseboard management controller (BMC) refers to a specialized microcontroller that manages the interface between system management software and platform hardware.” Where “[0084] The SP 120 monitors the sensors and can send out-of-band (OOB) alerts to a system administrator of the host computer 110 if any of the parameters do not stay within preset limits, indicating a potential failure of the host computer 110. In certain embodiments, the administrator can also remotely communicate with the SP 120 from a remote management computer via a network to take remote action to the host computer. For example, the administrator may reset the host computer 110 from the remote management computer through the SP 120, and may obtain system information of the host computer 110 OOB without interrupting the operation of the host computer 110.”].
Confalonieri, Vo Bokern and Maity are analogous art because they are from the same field of endeavor of memory access and control as well as data communication/transfer and integrated circuit design.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Confalonieri and Von Bokern to transfer the state information to the host device through the out-of-band communication via the sub link as taught by Maity since doing so would provide the benefits of [allowing for failure management and reset in case the sensor values indicate a potential failure].
Therefore, it would have been obvious to combine Confalonieri with Von Bokern and Maity for the benefit of creating a storage system/method to obtain the invention as specified in claim 14.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c). Weinberg et al. (US 11,860,714) teaches “Additionally or alternatively, the memory system 310 may monitor for errors not directly related to the data storage unit. For example, the memory system 310 may monitor parameters such as a temperature (e.g., a temperature of the memory array 345, a temperature of the buffer 335, or other components of the memory system 310) or supply voltages (e.g., supply voltages received from the host system 305). In some cases, if the memory system determines that a monitored parameter is out of an acceptable range (e.g., if the temperature exceeds a threshold, if a supply voltage is not within an operating range), signaling may be generated to indicate to the host system 305 that an error was detected. For example, the error controller 365 may process error indications from the components of the memory system 310 and may, using an out of band channel 360, issue an indication of the error to host system 305.” (col. 18, lines 4-19).
CLOSING COMMENTS
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-4, 7-8, 10-16, 18-20 have received a first action on the merits and are subject of a first action non-final.
a(2) ALLOWABLE SUBJECT MATTER
Per the instant office action, claims 5, 9 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
5. The storage system of claim 1, wherein the storage device further includes: a power management integrated circuit configured to receive a main power supply voltage from the host device and provide internal power supply voltages of the storage device based on the main power supply voltage, and wherein the microcontroller is configured to receive an auxiliary power supply voltage from the host device not via the power management integrated circuit.
9. The storage system of claim 1, wherein, the microcontroller is configured to, when the storage processor does not operate, receive a data dump request from the host device through the out-of-band communication via the sub link, read log data stored in the nonvolatile memory device through the on-chip bus and the memory interface based on the data dump request, and transfer the log data to the host device through the out-of-band communication.
17. The storage device of claim 16, wherein the storage device further includes: a power management integrated circuit configured to receive a main power supply voltage from the host device and provide internal power supply voltages of the storage device based on the main power supply voltage, and wherein the microcontroller is configured to receive one of the internal power supply voltages from the power management integrated circuit or receive an auxiliary power supply voltage from the host device not via the power management integrated circuit.
Claim 6 is objected to by virtue of their dependence on objected claim 5.
6. The storage system of claim 5, wherein the storage controller package further includes: an auxiliary voltage terminal that receives the auxiliary power supply voltage from the host device; and a package voltage terminal that receives an internal power supply voltage from the power management integrated circuit, and wherein the microcontroller is configured to operate based on the auxiliary power supply voltage that is provided through the auxiliary voltage terminal.
b. DIRECTION OF FUTURE CORRESPONDENCES
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January 23, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135