Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
As per the instant application having Application No. 18/973,951, the amendment filed on 3/31/2026 is herein acknowledged. Claims 1, 10 and 11 have been amended. Claims 1-11 are pending.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claim 1, Applicant’s Specification does not provide for the limitations “prioritizes issuing the commands in an order of: a first priority for a combination of the same memory and the same command type; a second priority for a combination of a different memory and a different command type; a third priority for a combination of a different memory and the same command type; and a fourth priority for a combination of the same memory and a different command type”, without any regard for set predetermined time periods. Applicant’s Specification recites:
[0062] [Modification]
When issuing a read command or a write command, the read/write control circuit 102 may perform control so as to preferentially issue a command having a shortest predetermined period among (1) a predetermined period (a penalty period in which a command cannot be selected) set for different memory and different transfer directions, (2) a predetermined period set for different memory and the same transfer direction, (3) a predetermined period set for the same memory and different transfer directions, and (4) a predetermined period set for the same memory and the same transfer direction.
[0063] For example, the predetermined period set for different memory and different transfer directions may be nine cycles, and the predetermined period set for different memory and the same transfer direction (for example, write→write) may be 13 cycles. Also, the predetermined period set for the same memory and different transfer directions may be 23 cycles, and the predetermined period set for the same memory and the same transfer direction (for example, write→write) may be four cycles.
Thus, while applicant’s Specification refers to command types and a same memory vs different memories, the Specification does not assign priorities without any regard to the set predetermined time periods as claimed or merely based on command type and memory locations. The preference for commands according to Applicant’s Specification occurs for a command having a shortest period among predetermined time periods set for same or different memories or different or same command types. See pars. 0062 and 0063 above, which were cited by Applicant as support for the claim amendments. Note that while Applicant’s Specification uses the term “priority” in pars. (0031-0032, 0037-0038, 0058), no description for priority has been found for the subject matter as claimed.
The specification only contemplates the manner of prioritizing commands or preferentially issuing commands in the manner discussed in paragraphs 0062-0063, by taking into account the shortest time period among predetermined time periods for commands types and memory devices as discussed in paragraphs 0062-0063 and there is no evidence that the Specification ever contemplates a more generic way of assigning priorities to commands. Note that According to MPEP 2161.01(I):
The written description requirement of 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, applies to all claims including original claims that are part of the disclosure as filed. Ariad, 598 F.3d at 1349, 94 USPQ2d at 1170. As stated by the Federal Circuit, "[a]lthough many original claims will satisfy the written description requirement, certain claims may not." Id. at 1349, 94 USPQ2d at 1170-71; see also LizardTech, Inc. v. Earth Res. Mapping, Inc., 424 F.3d 1336, 1343-46, 76 USPQ2d 1724, 1730-33 (Fed. Cir. 2005); Regents of the Univ. of Cal. v. Eli Lilly & Co., 119 F.3d 1559, 1568, 43 USPQ2d 1398, 1405-06 (Fed. Cir. 1997)("The description requirement of the patent statute requires a description of an invention, not an indication of a result that one might achieve if one made that invention."). Problems satisfying the written description requirement for original claims often occur when claim language is generic or functional, or both. Ariad, 593 F.3d at 1349, 94 USPQ2d at 1171 ("The problem is especially acute with genus claims that use functional language to define the boundaries of a claimed genus. In such a case, the functional claim may simply claim a desired result, and may do so without describing species that achieve that result. But the specification must demonstrate that the applicant has made a generic invention that achieves the claimed result and do so by showing that the applicant has invented species sufficient to support a claim to the functionally-defined genus.").For instance, generic claim language in the original disclosure does not satisfy the written description requirement if it fails to support the scope of the genus claimed. Ariad, 598 F.3d at 1349-50, 94 USPQ2d at 1171 ("[A]n adequate written description of a claimed genus requires more than a generic statement of an invention’s boundaries.") (citing Eli Lilly, 119 F.3d at 1568, 43 USPQ2d at 1405-06); Enzo Biochem, Inc. v. Gen-Probe, Inc., 323 F.3d 956, 968, 63 USPQ2d 1609, 1616 (Fed. Cir. 2002) (holding that generic claim language appearing in ipsis verbis in the original specification did not satisfy the written description requirement because it failed to support the scope of the genus claimed); Fiers v. Revel, 984 F.2d 1164, 1170, 25 USPQ2d 1601, 1606 (Fed. Cir. 1993) (rejecting the argument that "only similar language in the specification or original claims is necessary to satisfy the written description requirement").The Federal Circuit has explained that a specification cannot always support expansive claim language and satisfy the requirements of 35 U.S.C. 112 "merely by clearly describing one embodiment of the thing claimed." LizardTech v. Earth Resource Mapping, Inc., 424 F.3d 1336, 1346, 76 USPQ2d 1731, 1733 (Fed. Cir. 2005). The issue is whether a person skilled in the art would understand applicant to have invented, and been in possession of, the invention as broadly claimed. In LizardTech, claims to a generic method of making a seamless discrete wavelet transformation (DWT) were held invalid under 35 U.S.C. 112, first paragraph, because the specification taught only one particular method for making a seamless DWT and there was no evidence that the specification contemplated a more generic method. "[T]he description of one method for creating a seamless DWT does not entitle the inventor . . . to claim any and all means for achieving that objective." LizardTech, 424 F.3d at 1346, 76 USPQ2d at 1733.Similarly, original claims may lack written description when the claims define the invention in functional language specifying a desired result but the specification does not sufficiently describe how the function is performed or the result is achieved. For software, this can occur when the algorithm or steps/procedure for performing the computer function are not explained at all or are not explained in sufficient detail (simply restating the function recited in the claim is not necessarily sufficient). In other words, the algorithm or steps/procedure taken to perform the function must be described with sufficient detail so that one of ordinary skill in the art would understand how the inventor intended the function to be performed. (MPEP 2161.01, I.).
Also MPEP 2163 provides a similar discussion:
While there is a presumption that an adequate written description of the claimed invention is present in the specification as filed, In re Wertheim, 541 F.2d 257, 262, 191 USPQ 90, 96 (CCPA 1976), a question as to whether a specification provides an adequate written description may arise in the context of an original claim. An original claim may lack written description support when (1) the claim defines the invention in functional language specifying a desired result but the disclosure fails to sufficiently identify how the function is performed or the result is achieved or (2) a broad genus claim is presented but the disclosure only describes a narrow species with no evidence that the genus is contemplated. See Ariad Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1349-50 (Fed. Cir. 2010) (en banc). The written description requirement is not necessarily met when the claim language appears in ipsis verbis in the specification. "Even if a claim is supported by the specification, the language of the specification, to the extent possible, must describe the claimed invention so that one skilled in the art can recognize what is claimed. The appearance of mere indistinct words in a specification or a claim, even an original claim, does not necessarily satisfy that requirement." Enzo Biochem, Inc. v. Gen-Probe, Inc., 323 F.3d 956, 968, 63 USPQ2d 1609, 1616 (Fed. Cir. 2002). (MPEP § 2163.03, V.)
Just like in LizardTech v. Earth Resource Mapping, Inc., the Specification describes one way of prioritizing commands and does not provide any suggestion or description of this priority being merely based on command type and same or different memory devices, which would be encompassed by the broader claim language of claim 1; consequently, the Specification does not entitle the inventor to claim prioritizing commands according to claim 1, which does not take into account the shortest time period among predetermined time periods for commands types and memory devices as discussed in paragraphs 0062-0063.
It is suggested claim 1 be amended in accordance with Applicant’s Specification. Appropriate correction is required.
Independent claims 10 and 11 have been rejected for the reasons indicated above with respect to claim 1.
Dependent claims 2-9 are rejected for encompassing the deficiencies found in the independent claim upon which they belong.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2024/0184487) in view of Jin (US 2019/0369917).
1. A memory controller for issuing read and write commands for accessing a plurality of memories that share a data signal, the memory controller comprising: [Choi teaches memory device group 220 comprising a first memory device 221 and a second memory device 222 (fig. 2 and related text) where “The data channel DQ may be configured to communicate data and/or control information between the memory controller 210 and the memory device group 220” (par. 0045) and is thus shared by the first memory device 221 and the second memory device 222. Where commands include read and write commands (par. 0048)]
a hold circuit configured to hold access requests for the commands; and [Choi teaches “The first command CMD1 and the second command CMD2, which are generated by the access detector 520, may be stored in a command queue” (par. 0060; fig. 2 and related text) “The first command CMD1 and the second command CMD2 may be stored in the buffer 430” (par. 0067; fig. 4 and related text))]
a control circuit configured to select an access request from access requests held in the hold circuit and issue a command, [Choi teaches “The scheduler 440 may adjust output timings of commands stored in the buffer 430, by generating the order control signal Ctrl_order.” (par. 0067)]
Choi does not expressly disclose wherein the control circuit, prioritizes issuing the commands in an order of: a first priority for a combination of the same memory and the same command type; a second priority for a combination of a different memory and a different command type; a third priority for a combination of a different memory and the same command type; and a fourth priority for a combination of the same memory and a different command type; however, regarding these limitations, Jin teaches [“[0023] FIG. 2 is a flowchart illustrating a command reordering method according to an embodiment of the invention. In step S810 (a rank level step), the controller 120 selects at least one command having a rank address of a previous scheduling command from a plurality of access commands provided by the controller 120 as at least one first candidate command. “The previous scheduling command” refers to the access command that is previous executed. While the controller 120 is providing a plurality of access commands, an access efficiency of the memory 110 would be reduced if the rank addresses are frequently changed. When a plurality of consecutive access commands all have the same rank address, the memory 110 may be accessed more efficiently. By executing step S810 (the rank level step), the command(s) having the same rank address as the previous scheduling request may be selected from the access commands stored in a queue. Accordingly, step S810 (the rank level step) may allow a plurality of access commands having the same rank address to be grouped together and executed in sequence so the memory 110 may be accessed more efficiently… [0033] FIG. 6 is a flowchart illustrating the command reordering method according to another embodiment of the invention. With reference to FIG. 3, FIG. 4 and FIG. 6, in step S510, the sorting module 240 of the controller 120 may start performing one reordering, that is, to perform one command scheduling. In step S515, the sorting module 240 may determine whether a current time is in a read scheduling window. When the current time is in the read scheduling window, the sorting module 240 executes step S520 to obtain a first checking result by checking whether a read command queue set (the read scheduling queue 230) is empty and determine whether to enter the write scheduling windows by ending the read scheduling window according to the first checking result. When the current time is not in the read scheduling window (i.e., the current time is in the write scheduling window), the sorting module 240 executes step S530 to obtain a second checking result by checking whether the write command queue set (the write scheduling queue 220) is empty and determine whether to enter the read scheduling window by ending the write scheduling window according to the second checking result… [0035] During the process of executing the access commands, if the controller 120 frequently switches between the write command and the read command, the controller 120 and the memory 110 need to spend extra time for switching so that the access efficiency of the memory 110 is reduced. When all the consecutive access commands are the write commands (or the read commands), the memory 110 may be accessed more efficiently. By executing steps S515 to S535, the read command stored by the read scheduling queue 230 (the read command queue set) may be obtained (executed) in one time window, and the write command stored by the write scheduling queue 220 (the write command queue set) may be obtained (executed) in another time window. Accordingly, step S515 to S535 allows the controller 120 to continuously perform reading (or continuously perform write) whenever possible to reduce the switching between the read command and the write command so the memory 110 may be accessed more efficiently… [0036] When the current time is in the read scheduling window, the sorting module 240 may execute step S540 to check whether an overage queue is empty queue. If the overage queue is empty, the sorting module 240 executes step S560 to reorder the read commands (the access commands) stored by the read scheduling queue 230 (the read command queue set). The implementation details of step S560 may be analogized with reference to the related description of FIG. 2, which is not repeated hereinafter. After one read command is selected from the read scheduling queue 230 (the read command queue set) in step S560, the sorting module 240 may execute step S580 to use the selected read command as the current scheduling command (the current executing command) and take out the current scheduling command from the read scheduling queue 230… [0038] When the current time is in the write scheduling window, the sorting module 240 may execute step S530 to check whether the write scheduling queue 220 (the write command queue set) is empty queue. If it is determined that the write scheduling queue 220 is not empty queue in step S530, the sorting module 240 executes step S570 to reorder the write commands (the access commands) stored in the write scheduling queue 220 (the write command queue set). The implementation details of step S570 may be analogized with reference to the related description of FIG. 2, which is not repeated hereinafter. After one write command is selected from the write scheduling queue 220 (the write command queue set) in step S570, the sorting module 240 may execute step S580 to use the selected write command as the current scheduling command (the current executing command) and take out the current scheduling command from the write scheduling queue 220.” (see figs. 2, 6-8 and related text) commands to same bank/rank and same type (read) are selected with a first priority during a read scheduling window, once the read scheduling winding ends and the write scheduling window begins, commands to the same bank/rank and a different (from the read) type or the write type are selected with a fourth or different priority, once there are no more commands for the same bank, scheduling begins for a different bank and either a read or write window which corresponds to a second or different priority, once commands for that bank end and commands for a different band/rank continue according to the current window or command type which corresponds to a third priority].
Choi and Jin are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Choi to include prioritizes issuing the commands in an order of: a first priority for a combination of the same memory and the same command type; a second priority for a combination of a different memory and a different command type; a third priority for a combination of a different memory and the same command type; and a fourth priority for a combination of the same memory and a different command type as taught by Jin since doing so would provide the benefits of [“Accordingly, step S810 (the rank level step) may allow a plurality of access commands having the same rank address to be grouped together and executed in sequence so the memory 110 may be accessed more efficiently” (par. 0023) “[0035] During the process of executing the access commands, if the controller 120 frequently switches between the write command and the read command, the controller 120 and the memory 110 need to spend extra time for switching so that the access efficiency of the memory 110 is reduced. When all the consecutive access commands are the write commands (or the read commands), the memory 110 may be accessed more efficiently… Accordingly, step S515 to S535 allows the controller 120 to continuously perform reading (or continuously perform write) whenever possible to reduce the switching between the read command and the write command so the memory 110 may be accessed more efficiently.” (par. 0035)].
Therefore, it would have been obvious to combine Choi and JIn for the benefit of creating a storage system/method to obtain the invention as specified in claim 1.
3. The memory controller according to claim 1, wherein the control circuit, in a case where a command is issued to the second memory different from the first memory to which a command was issued immediately previously, issues a read command preferentially to a write command [Jin teaches a command having a different bank address may be selected, where during a read window, a read is selected preferentially to a write where “By executing steps S515 to S535, the read command stored by the read scheduling queue 230 (the read command queue set) may be obtained (executed) in one time window, and the write command stored by the write scheduling queue 220 (the write command queue set) may be obtained (executed) in another time window. Accordingly, step S515 to S535 allows the controller 120 to continuously perform reading (or continuously perform write) whenever possible to reduce the switching between the read command and the write command so the memory 110 may be accessed more efficiently.” (par. 0035) “ Here, a bank address of the second bank queue is different from the bank address of “the previous scheduling command”. When the selected bank queue is not empty, the access commands stored by the selected bank queue (which are the read commands at the time) are used as the second candidate command.” (par. 0052) (see figs. 2 and 6-8 and related text)] but does not expressly disclose issues a read command preferentially to a write command; however, regarding these limitations, Iwaki teaches [“[0094] On the other hand, in a case of the read priority mode, the request issue managing unit 350 extracts all of the read commands from the command queue 340 in order of arrival, processes these commands, and issues the write request. Then, after extracting all the read commands, the request issue managing unit 350 extracts the write commands from the command queue 340 in order of arrival, processes these commands, and issues the write request. Meanwhile the request issue managing unit 350 is an example of a command processing unit recited in claims.” (par. 0094)].
4. The memory controller according to claim 1, wherein the control circuit, in a case where a write command or a read command is issued to the second memory, which is different from the first memory, to which a write command was issued immediately previously, issues a read command preferentially to a write command [The rationale in the rejection of claim 3 is herein incorporated. Note during a read scheduling window read will be selected preferentially to a write, where a write scheduling window may end and a read scheduling window may begin, thus reads will be issued preferentially to writes (See figs. 6-8 and related text)].
5. The memory controller according to claim 1, wherein the control circuit, in a case where a write command or a read command is issued to the second memory, which is different from the first memory, to which a read command was issued immediately previously, issues a read command preferentially to a write command [The rationale in the rejection of claim 3 is herein incorporated. Note during a read scheduling window read will be selected preferentially to a write].
10. A method for controlling a memory controller for issuing read and write commands for accessing a plurality of memories that share a data signal, the method comprising: holding, in a hold circuit, access requests for the commands; and performing control to select an access request from access requests held in the hold circuit and issue a command, wherein the control, prioritizes issuing the commands in an order of: a first priority for a combination of the same memory and the same command type; a second priority for a combination of a different memory and a different command type; a third priority for a combination of a different memory and the same command type; and a fourth priority for a combination of the same memory and a different command type [The rationale in the rejection of claim 1 is herein incorporated].
11. A memory device comprising: a plurality of memories that share a data signal; and a memory controller for issuing read and write commands for accessing the plurality of memories, the controller comprising: a hold circuit configured to hold access requests for the commands; and a control circuit prioritizes issuing the commands in an order of: a first priority for a combination of the same memory and the same command type; a second priority for a combination of a different memory and a different command type; a third priority for a combination of a different memory and the same command type; and a fourth priority for a combination of the same memory and a different command type [The rationale in the rejection of claim 1 is herein incorporated].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2024/0184487) in view of Jin (US 2019/0369917) as applied in the rejection of claim 1 above, and further in view of Ikarashi (US 20180088864).
2. The combination of Choi and Jin teaches The memory controller according to claim 1, but does not expressly disclose wherein the control circuit, in a case where a command is issued to the second memory, which is different from the first memory to which a command was issued immediately previously, preferentially issues a command corresponding to a shortest predetermined period among predetermined periods set in advance after the shortest predetermined period has elapsed from the immediately previous issuance of a command; however, regarding these limitations, Ikarashi teaches [“[0039] In general, after a time of issuance of a certain command is established, the memory controller 32 counts a time taken until the next command, which is necessary to satisfy the restriction on the command interval, becomes issuable from the time of issuance of the certain command as the starting point. Although it is necessary to issue the commands at the shortest intervals specified in the DRAM specification in order to acquire a wide data transfer bandwidth that is a purpose of using the DRAMs 51 and 52” (see par. 0036; fig. 2 and related text)].
Choi, Jin and Ikarashi are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Choi and Jin to include wherein the control circuit, in a case where a command is issued to the second memory, which is different from the first memory to which a command was issued immediately previously, preferentially issues a command corresponding to a shortest predetermined period among predetermined periods set in advance after the shortest predetermined period has elapsed from the immediately previous issuance of a command as taught by Ikarashi since doing so would provide the benefits of [appropriate controlling DRAM access timings (par. 0008) and “reduce noise when accessing memory) (par. 0009)].
Therefore, it would have been obvious to combine Choi, Jin and Ikarashi for the benefit of creating a storage system/method to obtain the invention as specified in claim 2.
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2024/0184487) in view of Jin (US 2019/0369917) as applied in the rejection of claim 1 above, and further in view of Dearth et al. (20150378956).
6. The combination of Choi and Jin teaches The memory controller according to claim 1, wherein the control circuit performs control to, in a case where a read command is issued to the second memory, which is different from the first memory, to which a write command was issued immediately previously, issue the read command to the second memory in response to a lapse of a first predetermined period from the issuance of the write command, and in a case where a write command is issued to the second memory, which is different from the first memory, to which a write command was issued immediately previously, issue the write command to the second memory in response to a lapse of a second predetermined period from the issuance of the write command, and the second predetermined period is longer than the first predetermined period [Choi teaches “[0068] Referring together to FIGS. 2 and 4, the commands stored in the buffer 430 may be output to the first memory device 221 and the second memory device 222, based on the order control signal Ctrl_order. According to an embodiment, a time period taken for the memory controller 400 to output the first command CMD1 and/or the second command CMD2 may be defined by a specification or “spec.” The memory controller 400 may adjust an output timing of the first command CMD1 and/or the second command CMD2 to satisfy the spec.”. Jin teaches commands are issued to same memory banks or different memory banks according to read scheduling windows or write scheduling windows (figs. 2, 6-8 and related text)] but the combination does not expressly disclose a longer period for a write after a previous write than a write after a previous read; however, regarding these limitations, Dearth teaches [“[0006] The memory PHY typically is trained using sequences exchanged over an interface between the memory PHY and the DRAM before data can be accurately read from the DRAM or written to the DRAM. A training sequence may include multiple commands such as read commands, write commands, activate commands, or other commands that are used to perform other operations. The memory PHY or the DRAM may require commands in the training sequence to be separated by a specified delay time interval. For example, when a write command is followed by a read command, the DRAM may require a delay of 8 cycles between the write command and the read command. The delay time interval may be different for different types of commands. For example, the delay time interval between two write commands may be different than the delay time interval between a write command and a read command. The delay time interval may also be different for different types of DRAM and may change as new DRAM designs or timing standards are introduced.” “[0016]… delay time intervals between commands issued to a DRAM may be different for different types of commands and the delay time interval may also be different for different types of DRAM and may change as new DRAM designs are introduced. To account for timing requirements of different memory PHY or DRAM designs, training sequences can be flexibly defined by a programmable training engine that is implemented in the memory PHY. The training engine may be programmed using instruction words that include a first field to indicate a command and a second field to indicate a delay time interval that is to elapse before executing the command. Some embodiments of the instruction words may also include other fields that indicate a DRAM address used by the command, a bank of the DRAM used by the command, a repetition count for the command, and the like. Some embodiments of the memory PHY include registers for holding the instruction words and a start bit that can be written to initiate execution of the instruction words stored in the registers.” “[0017] Incorporating the delay time interval into the instruction word allows programmers to create training sequences that meet the requirements of different types of DRAM, as well as supporting the development of future training sequences that can meet the as-yet-unknown requirements of future DRAM designs. Furthermore, although two commands may need to be separated by a particular delay time interval, some embodiments of the memory PHY or DRAM may allow another type of command to be performed between the two commands. The delay time intervals indicated in the instruction words for the commands may therefore be set to values that allow the intermediate command to be executed while still meeting the delay time interval requirements for the other two commands.”]. Where, since Dearth teaches having different intervals between different types of commands, given Dearth’s teachings one of ordinary skill in the art would have found it obvious to have a longer interval between two write commands than the interval between a read and a write since doing so would involve modifying the value of the chosen interval and it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980), and doing so would at least provide flexibility of design.
Choi, Jin and Dearth are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Choi and Jin to include a different intervals between different types of commands for the different DRAMs as taught by Dearth since doing so would provide the benefits of [“[0017] Incorporating the delay time interval into the instruction word allows programmers to create training sequences that meet the requirements of different types of DRAM, as well as supporting the development of future training sequences that can meet the as-yet-unknown requirements of future DRAM designs. Furthermore, although two commands may need to be separated by a particular delay time interval, some embodiments of the memory PHY or DRAM may allow another type of command to be performed between the two commands. The delay time intervals indicated in the instruction words for the commands may therefore be set to values that allow the intermediate command to be executed while still meeting the delay time interval requirements for the other two commands.”]. Note that since Dearth teaches having different intervals between different types of commands, given Dearth’s teachings one of ordinary skill in the art would have found it obvious to have a longer interval between two write commands than the interval between a read and a write since doing so would involve modifying the value of the chosen interval and it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980), and doing so would at least provide flexibility of design.
Therefore, it would have been obvious to combine Choi, Jin and Dearth for the benefit of creating a storage system/method to obtain the invention as specified in claim 6.
7. The combination of Choi and Jin teaches The memory controller according to claim 1, wherein the control circuit, in a case where a write command is issued to the first memory, to which a read command was issued immediately previously, issue the write command to the first memory in response to a lapse of a third predetermined period from the issuance of the read command [Choi teaches “[0068] Referring together to FIGS. 2 and 4, the commands stored in the buffer 430 may be output to the first memory device 221 and the second memory device 222, based on the order control signal Ctrl_order. According to an embodiment, a time period taken for the memory controller 400 to output the first command CMD1 and/or the second command CMD2 may be defined by a specification or “spec.” The memory controller 400 may adjust an output timing of the first command CMD1 and/or the second command CMD2 to satisfy the spec.” Jin teaches commands are issued to same memory banks or different memory banks according to read scheduling windows or write scheduling windows where read or write scheduling windows may be switched (figs. 2, 6-8 and related text)] but the combination of Choi and Jin does not expressly disclose the write command to the first memory in response to a lapse of a third predetermined period from the issuance of the read command; however, regarding these limitations, Dearth teaches [“[0006] The memory PHY typically is trained using sequences exchanged over an interface between the memory PHY and the DRAM before data can be accurately read from the DRAM or written to the DRAM. A training sequence may include multiple commands such as read commands, write commands, activate commands, or other commands that are used to perform other operations. The memory PHY or the DRAM may require commands in the training sequence to be separated by a specified delay time interval. For example, when a write command is followed by a read command, the DRAM may require a delay of 8 cycles between the write command and the read command. The delay time interval may be different for different types of commands. For example, the delay time interval between two write commands may be different than the delay time interval between a write command and a read command. The delay time interval may also be different for different types of DRAM and may change as new DRAM designs or timing standards are introduced.” “[0016]… delay time intervals between commands issued to a DRAM may be different for different types of commands and the delay time interval may also be different for different types of DRAM and may change as new DRAM designs are introduced. To account for timing requirements of different memory PHY or DRAM designs, training sequences can be flexibly defined by a programmable training engine that is implemented in the memory PHY. The training engine may be programmed using instruction words that include a first field to indicate a command and a second field to indicate a delay time interval that is to elapse before executing the command. Some embodiments of the instruction words may also include other fields that indicate a DRAM address used by the command, a bank of the DRAM used by the command, a repetition count for the command, and the like. Some embodiments of the memory PHY include registers for holding the instruction words and a start bit that can be written to initiate execution of the instruction words stored in the registers.” “[0017] Incorporating the delay time interval into the instruction word allows programmers to create training sequences that meet the requirements of different types of DRAM, as well as supporting the development of future training sequences that can meet the as-yet-unknown requirements of future DRAM designs. Furthermore, although two commands may need to be separated by a particular delay time interval, some embodiments of the memory PHY or DRAM may allow another type of command to be performed between the two commands. The delay time intervals indicated in the instruction words for the commands may therefore be set to values that allow the intermediate command to be executed while still meeting the delay time interval requirements for the other two commands.”].
Choi, Jin and Dearth are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Choi and JIn to include the write command to the first memory in response to a lapse of a third predetermined period from the issuance of the read command as taught by Dearth since doing so would provide the benefits of [“[0017] Incorporating the delay time interval into the instruction word allows programmers to create training sequences that meet the requirements of different types of DRAM, as well as supporting the development of future training sequences that can meet the as-yet-unknown requirements of future DRAM designs. Furthermore, although two commands may need to be separated by a particular delay time interval, some embodiments of the memory PHY or DRAM may allow another type of command to be performed between the two commands. The delay time intervals indicated in the instruction words for the commands may therefore be set to values that allow the intermediate command to be executed while still meeting the delay time interval requirements for the other two commands.”].
Therefore, it would have been obvious to combine Choi, Jin and Dearth for the benefit of creating a storage system/method to obtain the invention as specified in claim 7.
8. The memory controller according to claim 1, wherein the control circuit performs control to, in a case where a read command is issued to the second memory, which is different from the first memory, to which a read command was issued immediately previously, issue the read command to the second memory in response to a lapse of a fourth predetermined period from the issuance of the read command, and in a case where a write command is issued to the second memory, which is different from the first memory, to which a read command was issued immediately previously, issue the write command to the second memory in response to a lapse of a fifth predetermined period from the issuance of the read command, and the fifth predetermined period is longer than the fourth predetermined period [The rationale in the rejection of claim 6 is herein incorporated where, for the same reasons indicated in claim 6, it would have been obvious to have a longer period between a read and write than between read commands].
9. The memory controller according to claim 1, wherein the control circuit, in a case where a write command is issued to the first memory, to which a read command was issued immediately previously, issues the write command to the first memory in response to a lapse of a sixth predetermined period from the issuance of the read command [The rationale in the rejection of claim 7 is herein incorporated, where it would have been obvious to have a sixth predetermined period from the issuance of the read command for the same reasons identified with respect to claim 7].
ACKNOWLEDGEMENT OF ISSUES RAISED BY APPLICANT
Response to Amendment
Applicant’s arguments regarding the double patenting rejections filed on 3/31/2026 are deemed persuasive. In view of the claim amendments presented on 3/31/2026 and Applicant’s arguments, the double patenting rejections have been withdrawn.
Applicant's arguments filed on 3/31/2026 with respect to the 35 USC 103 rejections have been fully considered and are deemed persuasive; however, they are moot in view of new grounds of rejection.
CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-11 have received an action on the merits and are subject to a final rejection.
b. DIRECTION OF FUTURE CORRESPONDENCES
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April 29, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135
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