DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1 and 11 recites at least one or more recitations of the step comprising to “store no parameter data”. It is requested that this is rewritten to instead state “not store the parameter data”. Furthermore, any additional recitations of “parameter data” should be revised to refer to the previous recitation. For example, Claim 1, Line 15 recites “parameter data” which should be --the parameter data--, and any similar recitations should be made in claim 11.
Claim 2, Line 10 recites “parameter data” which should be --the parameter data--.
Claim 2, Line 16 recites “a command sequence” which should be --the command sequence--. Line 17 further recites “an address of” which should be omitted from the claim such that the claim states that “the second command sequence… including… the second value.”
Claim 3, Line 3 recites “parameter data” which should be --the parameter data--.
Claim 4, Line 5 recites “parameter data” which should be --the parameter data--
Claims 6-10 are objected to because of the following informalities: it is unclear if the claims are intended to be construed as independent or dependent claims. Examiner suggests rewriting each of the memory system claims 6 to 10 by incorporating all limitations from the claim upon which it depends.
Claims 15-18 are similarly objected to because of the following informalities: it is unclear if the -claims are intended to be construed as independent or dependent claims. Examiner suggests rewriting each of the memory system claims 15 to 18 by incorporating all limitations from the claim upon which it depends.
Claim 12, Line 7 recites “parameter data” which should be --the parameter data--.
Claim 20, Lines 9-10 recites “a command sequence of the setting command including an address” which should be –the command sequence of the setting command including the address--. Lines 15-16 recites the same limitation and is objected to for the same reasons.
All claims dependent on any of the above identified claims inherits the same objections as discussed above.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2, 7 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 2:
Line 4 recites “the second address space.” There is insufficient antecedent basis for this limitation in the claim. While the term “common second address spaces” was recited in claim 1, it is unclear whether Applicant intended to refer to the command address space (plural), as the claimed limitation refers to a singular second address space. For the purposes of examination, it shall be interpreted that the limitations are referring to the command second address spaces.
Line 12 recites “the data being stored at a position…,” of which it is unclear as to which previous recitation of data is being referred to, as the claim previously recites data included in a first command sequence as well as data included in a second command sequence. For the purposes of examination, it shall be interpreted that the limitation is referring to the data of the second command sequence.
Claim 7 depends upon claim 2 and is rejected for the same reasons as claim 2, as outlined above.
Claim 20 recites the same limitations as identified in claim 2 and is rejected for the same reasons as claim 2, as outlined above.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims, and/or any claim objections, if applicable.
The following is an examiner’s statement of reasons for allowance:
Independent claim 1 recites the following limitations with features highlighted in combination with the other limitations of the claims most overcome the prior art of record:
“A semiconductor memory device comprising:
a terminal group to which a command sequence of a setting command is input, the command sequence including an address;
a first device including a first register group to which a first address space is mapped and a memory cell array, the first device being configured to
store parameter data in the first register group when the address is included in the first address space, and
store no parameter data in the first register group when the address is not included in the first address space; and
a second device provided between the terminal group and the first device, the second device including a second register group, the second register group including multiple pages to which common second address spaces exclusive of the first address space are mapped, the second device being configured to identify, based on the command sequence, a storage destination page of parameter data from among the multiple pages when the address is a first value.”
The most relevant prior art does not appear to teach or suggest the highlighted limitations in combination with the other recited limitations. The closest prior art is Fujiu et al. (US 2019/0391758 A1) and Oh (US 2023/0152993 A1). Fujiu et al. teaches a parameter write command called set feature which is used to store condition values related to an operation condition in a feature register, which is made up of an internal feature register and external feature register. The register areas that store feature data for the different planes are distinguishable from each other by features addresses. Thus, while Fujiu et al. teaches a first device including a first register group to which a first address space is mapped and a memory cell array, the first device being configured to store parameter data in the first register group when the address is included in the first address space. However, Fujiu et al. is silent with regards to a second device provided between the terminal group and the first device, the second device including a second register group, the second register group including multiple pages to which common second address spaces exclusive of the first address space are mapped, the second device being configured to identify, based on the command sequence, a storage destination page of parameter data from among the multiple pages when the address is a first value. The internal/external feature register of Fujiu et al., either of which can be analogous to a second register group, is not part of a second device positioned between the terminal group and the first device. That is, the first and second register groups of Fujiu et al. reside on the same device, thus, does not read on the entirety of the claim limitation. Oh teaches a special function register (SPR) storing parameters indicating connection characteristics between the storage device and host. The SPR resides in a storage controller between a host and the main non-volatile memory. Thus, while the SPR could be construed as a second register group of a second device, the SPR does not read on the claimed limitation in its entirety, as the second device of Oh is not provided between the terminal group and the first device. Secondly, Oh is silent with regards to first register group in a first device. Thus, the prior art of Fujiu et al. and Oh, both individually and in combination, does not teach the entirety of the claim limitation.
Claims 2-9 depend upon claim 1, and thus, is allowable for at least the same reasons as outlined above.
Independent claim 11 recites the following limitations with features highlighted in combination with the other limitations of the claims most overcome the prior art of record:
“A semiconductor memory device comprising:
a terminal group to which a command sequence of a setting command is input, the command sequence including an address included in a first address space;
a first device including a first register group and a memory cell array; and
a second device provided between the terminal group and the first device, the second device including a second register group and a memory in which first information has been stored, wherein
the first address space includes a first space and a second space exclusive of the first space, the first space being used for access to the first register group, the second space being used for access to the second register group,
the first information is information in which a correspondence between the second space and the second register group is recorded,
the first device is configured to
store parameter data in the first register group when the address is included in the first space, and
store no parameter data in the first register group when the address is not included in the first space, and
the second device is configured to
store parameter data in the second register group when the address is included in the second space, and
store no parameter data in the second register group when the address is not included in the second space.”
The most relevant prior art does not appear to teach or suggest the highlighted limitations in combination with the other recited limitations. The closest prior art is Fujiu et al. (US 2019/0391758 A1) and Oh (US 2023/0152993 A1). Fujiu et al. teaches a parameter write command called set feature which is used to store condition values related to an operation condition in a feature register, which is made up of an internal feature register and external feature register. The register areas that store feature data for the different planes are distinguishable from each other by features addresses. Thus, while Fujiu et al. teaches a first device including a first register group to which a first address space is mapped and a memory cell array, the first device being configured to store parameter data in the first register group when the address is included in the first address space. However, Fujiu et al. is silent with regards to a second device provided between the terminal group and the first device, the second device including a second register group, the second register group including multiple pages to which common second address spaces exclusive of the first address space are mapped, the second device being configured to identify, based on the command sequence, a storage destination page of parameter data from among the multiple pages when the address is a first value. The internal/external feature register of Fujiu et al., either of which can be analogous to a second register group, is not part of a second device positioned between the terminal group and the first device. That is, the first and second register groups of Fujiu et al. reside on the same device, thus, does not read on the entirety of the claim limitation. Oh teaches a special function register (SPR) storing parameters indicating connection characteristics between the storage device and host. The SPR resides in a storage controller between a host and the main non-volatile memory. Thus, while the SPR could be construed as a second register group of a second device, the SPR does not read on the claimed limitation in its entirety, as the second device of Oh is not provided between the terminal group and the first device. Secondly, Oh is silent with regards to first register group in a first device. Thus, the prior art of Fujiu et al. and Oh, both individually and in combination, does not teach the entirety of the claim limitation.
Claims 12-18 depend upon claim 11, and thus, is allowable for at least the same reasons.
Independent claim 19 recites the following limitations with features highlighted in combination with the other limitations of the claims most overcome the prior art of record:
“A method of controlling a semiconductor memory device, the semiconductor memory device including a terminal group, a first device, and a second device provided between the terminal group and the first device, the terminal group being a terminal group to which a command sequence of a setting command is input, the command sequence including an address, the first device including a first register group to which a first address space is mapped and a memory cell array, the second device including a second register group including multiple pages to which common second address spaces exclusive of the first address space are mapped, the method comprising:
identifying a storage destination page of parameter data from among the multiple pages when the address included in the command sequence received by the second device is a first value, the identifying being performed based on the command sequence.”
The most relevant prior art does not appear to teach or suggest the highlighted limitations in combination with the other recited limitations. The closest prior art is Fujiu et al. (US 2019/0391758 A1) and Oh (US 2023/0152993 A1). Fujiu et al. teaches a parameter write command called set feature which is used to store condition values related to an operation condition in a feature register, which is made up of an internal feature register and external feature register. The register areas that store feature data for the different planes are distinguishable from each other by features addresses. Thus, Fujiu et al. teaches the first device including a first register group to which a first address space is mapped and a memory cell array. However, Fujiu et al. is silent with regards to the second device including a second register group including multiple pages to which common second address spaces exclusive of the first address space are mapped, and identifying a storage destination page of parameter data from among the multiple pages when the address included in the command sequence received by the second device is a first value. The internal/external feature register of Fujiu et al., either of which can be analogous to a second register group, is not part of a second device positioned between the terminal group and the first device. That is, the first and second register groups of Fujiu et al. reside on the same device, thus, does not read on the entirety of the claim limitation. Oh teaches a special function register (SPR) storing parameters indicating connection characteristics between the storage device and host. The SPR resides in a storage controller between a host and the main non-volatile memory. Thus, while the SPR could be construed as a second register group of a second device, the SPR does not read on the claimed limitation in its entirety, as the second device of Oh is not provided between the terminal group and the first device. Secondly, Oh is silent with regards to first register group in a first device. Thus, the prior art of Fujiu et al. and Oh, both individually and in combination, does not teach the entirety of the claim limitation.
Claim 20 recites subject matter substantially similar to that as recited in claim 19, and thus, is found to be allowable for the reasons discussed supra.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Her et al. (US 2021/0026565 A1) teaches storing parameter in a target register corresponding to normal addresses as well as dummy data in a dummy register.
Seong (US 2018/0075910 A1) teaches executing a parameter set command when the address of the command is associated with a special register of a semiconductor memory device.
Lu et al. (US 2024/0004581 A1) teaches a set-feature operation which includes sending a signal with a logical unit number (LUN) address.
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JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/ Primary Examiner, Art Unit 2139