Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Horn et al. (USPN 11733878B1).
As per claim 1, Horn et al. discloses a memory system comprising:
a memory device comprising a plurality of blocks (column 2, lines 54-60 - FIG. 1 is a block diagram of a Data Storage Device (DSD) 106 according to one or more embodiments. As shown in the example of FIG. 1, DSD 106 includes Non-Volatile Memory (NVM) in the form of rotating magnetic disks 131 and 133. In other implementations, DSD 106 may include a different number of disks or a different type of NVM such as a solid-state memory in addition to rotating magnetic disks.; column 3, lines 38-42 - As discussed in more detail below with reference to FIG. 2A, data blocks of varying sizes, such as files or other data objects, can be partitioned into data sub-blocks each having a predetermined size that can span one or more sectors.); and
a memory controller configured to control the memory device (column 3, lines 7-16 - DSD 106 includes controller 120 that comprises circuitry such as one or more processors for executing instructions including a Central Processing Unit (CPU), microcontroller, Digital Signal Processor (DSP), Application-Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), Graphics Processing Unit (GPU), hard-wired logic, analog circuitry and/or a combination thereof. In some implementations, controller 120 can include a System on a Chip (SoC), which may be combined with one or both of host interface 126 and memory 140.);
wherein the plurality of blocks comprise: a first block comprising a first sub-block having a first size and a second sub-block having a second size different from the first size (column 3, lines 38-42 - As discussed in more detail below with reference to FIG. 2A, data blocks of varying sizes, such as files or other data objects, can be partitioned into data sub-blocks each having a predetermined size that can span one or more sectors. – the predetermined size can be different for each sub-block); and
a second block comprising a third sub-block having a third size and a fourth sub-block having a fourth size different from the third size, wherein the first size of the first sub-block is equal to the third size of the third sub-block, wherein the first sub-block and the third sub-block constitute a first super sub-block, wherein the second size of the second sub-block is equal to the fourth size of the fourth sub-block, wherein the second sub-block and the fourth sub-block constitute a second super sub-block (column 3, lines 38-42 - As discussed in more detail below with reference to FIG. 2A, data blocks of varying sizes, such as files or other data objects, can be partitioned into data sub-blocks each having a predetermined size that can span one or more sectors. – blocks can be portioned into sub-blocks of different sizes and different arrangements with other blocks),
wherein the memory controller comprises a mapping table managing first addresses of sub-blocks included in the first super sub-block and second addresses of sub-blocks included in the second super sub-block (column 6, line 60 – column 7, line 7 - In some implementations, the logical addresses of the data blocks that have been encoded into ECC sub-blocks can be included in a header of the ECC sub-blocks and/or of the ECC super-block so that the locations of the data blocks are self-identifying when being read. The logical addresses in the header of the ECC sub-block and/or of the ECC super-block may indicate the sequence of the data blocks encoded into the ECC sub-block and/or the ECC super-block. Controller 120 can use the logical addresses to determine the sequence of ECC sub-blocks written to the recording surface so that the sequence can be reconstructed during a read operation. In other implementations, controller 120 may maintain a mapping table or another type of data structure for determining the sequence of ECC sub-blocks written to the recording surface.), and
wherein the memory controller is further configured to perform a reliability protection operation on the memory device in units of sub-blocks or super sub-blocks and update the mapping table (column 3, lines 53-55 - In some implementations, controller 120 may execute ECC module 16 to perform the processes of FIGS. 4 to 6A and 6B, as discussed in more detail below.; column 4, lines 17-23 - ECC module 16 can provide for greater reliability in recovering from read errors by performing ECC at both a sub-block level and at a super-block level where the ECC super-block includes multiple ECC sub-blocks and redundant data that can be used with an algorithm to recover ECC sub-blocks with read errors that exceed the correction capability of the ECC sub-block.).
As per claims 2,15, Horn et al. discloses further comprising: a free sub-block pool comprising a fifth sub-block having a fifth size, wherein the fifth size of the fifth sub-block is equal to the first size of the first sub-block, wherein the memory device is configured to: copy valid data, stored in the first sub-block, to the fifth sub-block based on a number of error bits in data stored in the first sub-block being greater than or equal to a number of reference bits (column 5, line 65 – column 6, line 11 - FIG. 2B shows an example where the second ECC sub-block (i.e., SB2 and its associated ECC data) in the first ECC super-block fails the write-verify, which is designated in FIG. 2B with a shaded block for SB2 and its associated ECC data. The second ECC sub-block is duplicated by encoding the second ECC sub-block into the subsequent ECC super-block, ECC super-block 2. Instead of encoding ECC sub-blocks for SB4, SB5, and SB6 into ECC super-block 2 as in FIG. 2A, ECC sub-blocks for SB2, SB4, and SB5 are encoded into ECC super-block 2 in FIG. 2B to provide a copy of the ECC sub-block for the data sub-block SB2 in the next super-block. An ECC sub-block for SB6 can then be encoded into the ECC super-block that follows ECC super-block 2. – failing the write verify includes having a number of error bit greater than or equal to a number of reference bits).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12,13 are rejected under 35 U.S.C. 103 as being unpatentable over Horn et al. in view of Guo et al. (USPN 20230343400A1).
As per claim 12, Horn et al. fails to explicitly state wherein each of the plurality of blocks comprises a plurality of memory cells, vertically stacked on a substrate, wherein the first sub-block and the second sub-block included in the first block are separated by a first sub-block separation line disposed at a first height with respect to the substrate, and wherein the third sub-block and the fourth sub-block included in the second block are separated by a second sub-block separation line disposed at a same height as the first sub-block separation line.
Horn et al. does disclose in column 2, lines 54-60 - FIG. 1 is a block diagram of a Data Storage Device (DSD) 106 according to one or more embodiments. As shown in the example of FIG. 1, DSD 106 includes Non-Volatile Memory (NVM) in the form of rotating magnetic disks 131 and 133. In other implementations, DSD 106 may include a different number of disks or a different type of NVM such as a solid-state memory in addition to rotating magnetic disks.
Guo et al. discloses wherein each of the plurality of blocks comprises a plurality of memory cells, vertically stacked on a substrate, wherein the first sub-block and the second sub-block included in the first block are separated by a first sub-block separation line disposed at a first height with respect to the substrate, and wherein the third sub-block and the fourth sub-block included in the second block are separated by a second sub-block separation line disposed at a same height as the first sub-block separation line in paragraph 0123 - Again, the strings may be organized in rows grouped in a plurality of fingers (Fingers 0-3 of FIGS. 8A-8B) or strings (e.g., Str 0-3 of FIG. 13). The strings comprise each of a plurality of blocks. Referring back to FIG. 13, each of the plurality of blocks comprise a plurality of sub-blocks (e.g., SB0-SB2) arranged vertically in the stack and include a first sub-block (e.g., SB0) and a second sub-block (e.g., SB1) disposed vertically above the first sub-block and a third sub-block (e.g., SB2) disposed vertically above the first sub-block and the second sub-block. So, according to an aspect, the control means is further configured to program the memory cells connected to each of the plurality of word lines associated with each the plurality of sub-blocks in a reverse programming order (e.g., starting with the one of the plurality of word lines associated with each the plurality of sub-blocks disposed closest to a top of the stack and progressing with one of the plurality of word lines associated with each the plurality of sub-blocks disposed vertically below each previous one of the plurality of word lines).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the sub-block arranged vertically of Guo in a non-volatile memory of Horn. A person of ordinary skill in the art would have been motivated to make the modification because the sub-blocks are arranged in a format, as disclosed in paragraph 0123.
As per claim 13, Horn et al. fails to explicitly state wherein each of the first block and the second block comprises a lower channel structure, vertically formed on the substrate, and an upper channel structure formed on the lower channel structure, wherein the first sub-block separation line is disposed in a first boundary region between the lower channel structure and the upper channel structure of the first block, and wherein the second sub-block separation line is disposed in a second boundary region between the lower channel structure and the upper channel structure of the second block.
Horn et al. does disclose in column 2, lines 54-60 - FIG. 1 is a block diagram of a Data Storage Device (DSD) 106 according to one or more embodiments. As shown in the example of FIG. 1, DSD 106 includes Non-Volatile Memory (NVM) in the form of rotating magnetic disks 131 and 133. In other implementations, DSD 106 may include a different number of disks or a different type of NVM such as a solid-state memory in addition to rotating magnetic disks.
Guo et al. discloses wherein each of the first block and the second block comprises a lower channel structure, vertically formed on the substrate, and an upper channel structure formed on the lower channel structure, wherein the first sub-block separation line is disposed in a first boundary region between the lower channel structure and the upper channel structure of the first block, and wherein the second sub-block separation line is disposed in a second boundary region between the lower channel structure and the upper channel structure of the second block in paragraph 0123 - Again, the strings may be organized in rows grouped in a plurality of fingers (Fingers 0-3 of FIGS. 8A-8B) or strings (e.g., Str 0-3 of FIG. 13). The strings comprise each of a plurality of blocks. Referring back to FIG. 13, each of the plurality of blocks comprise a plurality of sub-blocks (e.g., SB0-SB2) arranged vertically in the stack and include a first sub-block (e.g., SB0) and a second sub-block (e.g., SB1) disposed vertically above the first sub-block and a third sub-block (e.g., SB2) disposed vertically above the first sub-block and the second sub-block. So, according to an aspect, the control means is further configured to program the memory cells connected to each of the plurality of word lines associated with each the plurality of sub-blocks in a reverse programming order (e.g., starting with the one of the plurality of word lines associated with each the plurality of sub-blocks disposed closest to a top of the stack and progressing with one of the plurality of word lines associated with each the plurality of sub-blocks disposed vertically below each previous one of the plurality of word lines).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the sub-block arranged vertically in the stack as strings of Guo in a non-volatile memory of Horn. A person of ordinary skill in the art would have been motivated to make the modification because the sub-blocks are arranged in a format, as disclosed in paragraph 0123.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Horn et al. in view of Yamaga et al. (USPN 20240403210A1).
As per claim 14, Horn et al. discloses a memory device comprising: a memory cell array comprising a plurality of blocks storing data (column 2, lines 54-60 - FIG. 1 is a block diagram of a Data Storage Device (DSD) 106 according to one or more embodiments. As shown in the example of FIG. 1, DSD 106 includes Non-Volatile Memory (NVM) in the form of rotating magnetic disks 131 and 133. In other implementations, DSD 106 may include a different number of disks or a different type of NVM such as a solid-state memory in addition to rotating magnetic disks.; column 3, lines 38-42 - As discussed in more detail below with reference to FIG. 2A, data blocks of varying sizes, such as files or other data objects, can be partitioned into data sub-blocks each having a predetermined size that can span one or more sectors.); and
a control logic configured to control the memory cell array (column 3, lines 7-16 - DSD 106 includes controller 120 that comprises circuitry such as one or more processors for executing instructions including a Central Processing Unit (CPU), microcontroller, Digital Signal Processor (DSP), Application-Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), Graphics Processing Unit (GPU), hard-wired logic, analog circuitry and/or a combination thereof. In some implementations, controller 120 can include a System on a Chip (SoC), which may be combined with one or both of host interface 126 and memory 140.), wherein the plurality of blocks comprise:
a first block comprising a first sub-block having a first size and a second sub-block having a second size different from the first size (column 3, lines 38-42 - As discussed in more detail below with reference to FIG. 2A, data blocks of varying sizes, such as files or other data objects, can be partitioned into data sub-blocks each having a predetermined size that can span one or more sectors. – the predetermined size can be different for each sub-block); and
a second block comprising a third sub-block having a third size and a fourth sub-block having a fourth size different from a size of the third sub-block, wherein the first size of the first sub-block is equal to the third size of the third sub-block, wherein the first sub-block and the third sub-block constitute a first super sub-block, wherein the second size of the second sub-block is equal to the fourth size of the fourth sub-block, wherein the second sub-block and the fourth sub-block constitute a second super sub-block (column 3, lines 38-42 - As discussed in more detail below with reference to FIG. 2A, data blocks of varying sizes, such as files or other data objects, can be partitioned into data sub-blocks each having a predetermined size that can span one or more sectors. – blocks can be portioned into sub-blocks of different sizes and different arrangements with other blocks), and
wherein the control logic is further configured to: control the memory cell array to perform at least one of a read reclaim operation, an active reclaim operation, in units of sub-blocks or super sub-blocks (column 3, lines 53-55 - In some implementations, controller 120 may execute ECC module 16 to perform the processes of FIGS. 4 to 6A and 6B, as discussed in more detail below.; column 4, lines 17-23 - ECC module 16 can provide for greater reliability in recovering from read errors by performing ECC at both a sub-block level and at a super-block level where the ECC super-block includes multiple ECC sub-blocks and redundant data that can be used with an algorithm to recover ECC sub-blocks with read errors that exceed the correction capability of the ECC sub-block.), and
Horn et al. fails to explicitly state wherein a mapping table managing first addresses of sub-blocks included in the first super sub-block and second addresses of sub-blocks included in the second super sub-block is updated based on the at least one of the read reclaim operation or the active reclaim operation being performed.
Horn et al. does disclose in column 6, line 60 – column 7, line 7 - In some implementations, the logical addresses of the data blocks that have been encoded into ECC sub-blocks can be included in a header of the ECC sub-blocks and/or of the ECC super-block so that the locations of the data blocks are self-identifying when being read. The logical addresses in the header of the ECC sub-block and/or of the ECC super-block may indicate the sequence of the data blocks encoded into the ECC sub-block and/or the ECC super-block. Controller 120 can use the logical addresses to determine the sequence of ECC sub-blocks written to the recording surface so that the sequence can be reconstructed during a read operation. In other implementations, controller 120 may maintain a mapping table or another type of data structure for determining the sequence of ECC sub-blocks written to the recording surface.
Yamaga et al. does disclose wherein a mapping table managing first addresses of sub-blocks included in the first super sub-block and second addresses of sub-blocks included in the second super sub-block is updated based on the at least one of the read reclaim operation or the active reclaim operation being performed in paragraph 0092 - In the garbage collection processing, when the sub-block 313 is copied, the directory table 402 and the mapping table 403 that manage the storage address of the sub-block also need to be updated to the copy destination address.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the sub-block read and copied during garbage collection of Yamaga in mapping table including sub-blocks of Horn. A person of ordinary skill in the art would have been motivated to make the modification because the sub-blocks and their locations are known within the mapping table, as disclosed in paragraph 0092.
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Masayoshi (JP2006126975A) in view of Horn et al. in further view of Yamaga et al. (USPN 20240403210A1).
As per claim 20, Masayoshi discloses a method of operating a memory system comprising a plurality of blocks (By the way, the memory | storage part 13 consists of flash memory, for example, and is comprised by several (for example, 254 pieces) storage blocks B1-B253 as shown in FIG. Each of the storage storage blocks B1 to B253 is further composed of a plurality of (for example, 254 in the figure) subblocks VSB1 to VSB253, and data is written, read and erased in units of these subblocks.), the method comprising:
selecting a first sub-block for which a reclaim operation is requested, from among sub-blocks included in each of the plurality of blocks, as a source sub-block (That is, as shown in FIG. 6, the control unit 12 first searches for a block having the largest ratio of the number of used sub-blocks as a garbage collection process target block in step 6a.);
allocating a second sub-block having a same size as the source sub-block and being in an empty state, from among the sub-blocks included in each of the plurality of blocks, as a destination sub-block (In step 6b, a block having an unused sub-block is searched as a rearrangement destination block.); and
moving valid data stored in the source sub-block to the destination sub-block in units of sub-blocks (Next, the control unit 12 enters a copy period. In step 6c, the control unit 12 selects one sub-block in use from the searched garbage collection processing target block, and the necessary data stored in the selected sub-block is Copy to one of the unused sub-blocks in the searched relocation destination block. For example, as shown in FIG. 7, if the subblock VSB100 of the storage block B1 is in use, the necessary data stored in the subblock VSB100 is copied to the unused subblock VSB1 of the relocation destination storage block B3. .).
Masayoshi fails to explicitly state included in a first super sub-block, included in a second super sub-block.
Masayoshi does disclose subblocks.
Horn et al. does disclose included in a first super sub-block, included in a second super sub-block in column 3, lines 53-55 - In some implementations, controller 120 may execute ECC module 16 to perform the processes of FIGS. 4 to 6A and 6B, as discussed in more detail below.; column 4, lines 17-23 - ECC module 16 can provide for greater reliability in recovering from read errors by performing ECC at both a sub-block level and at a super-block level where the ECC super-block includes multiple ECC sub-blocks and redundant data that can be used with an algorithm to recover ECC sub-blocks with read errors that exceed the correction capability of the ECC sub-block.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include super sub-blocks of Horn of in sub-blocks of Masayoshi. A person of ordinary skill in the art would have been motivated to make the modification because the sub-blocks are organized into super sub-blocks, as disclosed in column 4, lines 17-23.
Masayoshi and Horn et al. fail to explicitly state updating a mapping table managing first addresses of sub-blocks included in the first super sub-block and second addresses of sub-blocks included in the second super sub-block.
Horn et al. does disclose in column 6, line 60 – column 7, line 7 - In some implementations, the logical addresses of the data blocks that have been encoded into ECC sub-blocks can be included in a header of the ECC sub-blocks and/or of the ECC super-block so that the locations of the data blocks are self-identifying when being read. The logical addresses in the header of the ECC sub-block and/or of the ECC super-block may indicate the sequence of the data blocks encoded into the ECC sub-block and/or the ECC super-block. Controller 120 can use the logical addresses to determine the sequence of ECC sub-blocks written to the recording surface so that the sequence can be reconstructed during a read operation. In other implementations, controller 120 may maintain a mapping table or another type of data structure for determining the sequence of ECC sub-blocks written to the recording surface.
Yamaga et al. does disclose updating a mapping table managing first addresses of sub-blocks included in the first super sub-block and second addresses of sub-blocks included in the second super sub-block in paragraph 0092 - In the garbage collection processing, when the sub-block 313 is copied, the directory table 402 and the mapping table 403 that manage the storage address of the sub-block also need to be updated to the copy destination address.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the sub-block read and copied during garbage collection of Yamaga in mapping table including sub-blocks of Horn. A person of ordinary skill in the art would have been motivated to make the modification because the sub-blocks and their locations are known within the mapping table, as disclosed in paragraph 0092.
There is no prior art rejection for claims 3-11,16-19 because either no prior art could be found or no reason to combine with prior art found.
Response to Arguments
Applicant's arguments and amendments filed 07/07/2026 have been fully considered. A new reference has been found to reject the added limitations. Please see the above rejection. Horn et al. does disclose having a mapping table with super sub-blocks and sub-blocks. Please see the above rejection..
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Yolanda L Wilson whose telephone number is (571)272-3653. The examiner can normally be reached M-F (7:30 am - 4 pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Yolanda L Wilson whose telephone number is (571)272-3653. The examiner can normally be reached M-F (7:30 am - 4 pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Yolanda L Wilson/Primary Examiner, Art Unit 2113
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