DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Information Disclosure Statement
An information disclosure statement (IDS) was submitted on 09 December 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8-10, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20220222138 A1) in view of Yoo (US 20220172785 A1).
Referring to claims 1 and 19, taking claim 1 as exemplary, Park teaches
A memory controller configured to control a memory device comprising a plurality of memory cells, the memory controller ([Park abstract, 0007] A memory controller may control the memory device, memory cell array having a plurality of memory cells) comprising: a valley search manager configured to perform a valley search operation to search for a valley between threshold voltage distributions associated with the plurality of memory cells and obtain a valley read level corresponding to the valley; ([Park 0030, 0079] the logic circuit 12 may include an on-chip valley search (OVS) circuit 13. The OVS circuit 13 may execute an on-chip valley search operation.) configured to: model a cumulative cell count function between the threshold voltage distributions based on a plurality of read levels, ([Park 0038] For example, the processor may input the cell count information, received as the detection information, to the machine learning model 25. The machine learning model 25 may receive the detection information, e.g., the cell count information, or the like, to be pre-trained to output an optimum offset voltage for a read voltage. According to embodiments, the machine learning model 25 may additionally receive addresses of memory cells on which an optimal read operation is executed, deterioration information of the memory cells, and the like.) generate a cumulative read level between the threshold voltage distributions based on the cumulative cell count function, ([Park abstract, 0005, 0064, 0074] A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on the cell count information when an error in read data, received from the memory device performing a read operation is not corrected. to store a machine learning model that receives cell count information corresponding to a threshold voltage distribution of memory cells included in the at least one memory device and generates a dynamic offset voltage for the read operation. The memory device may execute an OVS read operation including a first sensing operation, in which a cell count representing a distribution of threshold voltages of selected memory cells is collected and a detection case based on the cell count is determined, and a second sensing operation in which a development time is changed depending on an offset voltage corresponding to the detection case, determined in the first sensing operation, to generate read data.).
Park does not explicitly disclose and a read level generator and generate an optimal read level based on the valley read level and the cumulative read level. Park does disclose the memory controller 20 may instruct the memory device 10 to execute an optimal read operation including an OVS operation ([Park 0038-0041, 0078-0079, 0133-0134, Fig. 5]).
Yoo teaches and a read level generator ([Yoo 0040, 0169-0174, Figs. 7, 14, 16] the read level manager 111 may search an optimal read level or control a plurality of read levels. In operation S540, the nonvolatile memory device 220 may search an optimal read level) and generate an optimal read level based on the valley read level and the cumulative read level ([Yoo 0040, 0169-0174, Figs. 7, 16] through a valley search operation, the read level manager 111 may search an optimal read level or control a plurality of read levels. In operation S540, the nonvolatile memory device 220 may search an optimal read level. For example, the nonvolatile memory device 220 may set a window based on the set operation parameters and may perform the cell-counting operation based on a plurality of levels included in the set window. The read level manager 226 of the nonvolatile memory device 220 may search an optimal read level based on cell-counting results. The valley search operation for searching an optimal read level is similar to the above valley search operation except that the valley search operation is performed at the nonvolatile memory device 220, and thus, additional description will be omitted to avoid redundancy. In operation S550, the nonvolatile memory device 220 may perform a read operation by using optimal read levels.).
Park and Yoo are analogous art because they are from the same field of endeavor in storage devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Park and Yoo before him or her to modify the memory controller of Park to include the read level manager of Yoo, thereafter the memory controller is connected to read level manager. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the memory controller to have more improved reliability regarding read levels as suggested by Yoo. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Park with Yoo to obtain the invention as specified in the instant application claims.
With regards to the non-exemplary limitations of claim 19, Park additionally teaches generate cumulative cell count values respectively corresponding to a plurality of read levels, ([Park 0008, claim 24] the memory device such that an on-chip valley search (OVS) operation is executed to generate cell count information and a read operation is executed depending on a detection case determined based on the cell count information) receive the cumulative cell count values and generates a valley read level corresponding to the valley based on the cumulative cell count values, model a cumulative cell count function that takes the plurality of read levels as input and outputs the cumulative cell count values respectively corresponding to the plurality of read levels, ([Park 0008, 0029-0030, 0040,] the memory device such that an on-chip valley search (OVS) operation is executed to generate cell count information and a read operation is executed depending on a detection case determined based on the cell count information. The memory interface 14 may output read data. The OVS circuit 13 may execute an on-chip valley search operation. The on-chip valley search operation may include a first sensing operation, in which a detection case is determined based on a cell count, and a second sensing operation in which data is read from selected memory cells by changing development time and/or a level of a read voltage depending on the detection case ).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claim 8, Park in view of Yoo teaches
The memory controller of claim 1, wherein the read level generator is further configured to model the cumulative cell count function as a cubic function, based on at least four read levels and at least four cumulative cell count values respectively corresponding to the at least four read levels ([Park 0088] a read operation of a least significant bit (LSB) may include a first read operation using a first read voltage RP1 between the erase state E and the first program state P1 and a second read operation using a fifth read voltage RP5 between the fourth program state P4 and the fifth read voltage RPS. Similarly, a read operation of a most significant bit may include a first read operation using a third read voltage RP3 between the second program state P2 and the third program state P3 and a second read operation using a seventh read voltage RP7 between the sixth program state P6 and the seventh program state P7. A read operation of an intermediate significant bit may include a first read operation using a second read voltage RP2 between the first program state P1 and the second program state P2, a second read operation using a fourth read voltage RP4 between the third program state P3 and the fourth program state, and a third read operation using a sixth read voltage RP6 between the fifth program state P5 and the sixth program state P6.).
Referring to claim 9, Park in view of Yoo teaches
The memory controller of claim 1, wherein, based on a first threshold voltage distribution and a second threshold distribution respectively corresponding to two adjacent states being symmetrical to each other, the optimal read level is equal to the valley read level, and wherein the two adjacent states are among a plurality of states respectively representing values stored in the plurality of memory cells ([Yoo 0085, 0112-0116] the valley search operation illustrated in FIG. 7 may be applied to search a valley between adjacent program states. The memory controller 110 may perform the valley search operation in the third charge loss window WD_3a. In this case, a valley between the second and third charge loss states P2a and P3a, e.g., an optimal read level may be normally searched.).
The same motivation that was utilized for combining Park and Yoo as set forth in claim(s) 1 is equally applicable to this/these claim(s).
Referring to claim 10, Park in view of Yoo teaches
The memory controller of claim 1, wherein the valley search manager is further configured to: obtain cumulative cell count values respectively corresponding to the plurality of read levels through the valley search operation, and generate the valley read level based on the cumulative cell count values ([Yoo 0040, 0169-0174, Figs. 7, 16] through a valley search operation, the read level manager 111 may search an optimal read level or control a plurality of read levels. In operation S540, the nonvolatile memory device 220 may search an optimal read level. For example, the nonvolatile memory device 220 may set a window based on the set operation parameters and may perform the cell-counting operation based on a plurality of levels included in the set window. The read level manager 226 of the nonvolatile memory device 220 may search an optimal read level based on cell-counting results. The valley search operation for searching an optimal read level is similar to the above valley search operation except that the valley search operation is performed at the nonvolatile memory device 220, and thus, additional description will be omitted to avoid redundancy. In operation S550, the nonvolatile memory device 220 may perform a read operation by using optimal read levels.).
The same motivation that was utilized for combining Park and Yoo as set forth in claim(s) 1 is equally applicable to this/these claim(s).
Allowable Subject Matter
Claims 2-7, 11, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12-18 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art made of record teaches a method for operating a memory controller but fails to teach the combination including the limitations of:
(Claim(s) 12) “generating a valley read level corresponding to the valley based on the plurality of read points; modeling a cumulative cell count function between the threshold voltage distributions based on the plurality of read points and generating a cumulative read level between the threshold voltage distributions based on the cumulative cell count function; and generating an optimal read level by applying a valley weight to the valley read level and applying a cumulative weight to the cumulative read level”
As dependent claims 13-18 depend from an allowable base claim; they are at least allowable for the same reasons as noted supra. Support for the above noted limitations can be found in at least paragraphs [0051-0055, 0072-0074, 0144-0158, Figs. 9-12] of Applicant' s specification.
The prior art made of record, Park (US 20220222138 A1) and Yoo (US 20220172785 A1), neither anticipates nor renders obvious the above recited combinations for at least the reasons specified.
The prior art made of record, on the 892 and/or 1449 forms, in the case does not fairly teach or suggest the claimed limitations, nor does it render the claimed invention obvious. Therefore this case is passed to issue.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5.
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132