Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the arguments filed on 03/23/2026. Claims 1, 3-9, 11-16 and 19-21 are pending. Applicant’s amendments are considered and 35 U.S.C. 112(f) claim interpretation is withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by SUZUKI et al. (US 20220414044 A1) hereinafter SUZUKI.
Regarding claim 21, SUZUKI teaches The memory system according to The memory system according to wherein the memory chip includes: an I/O circuit coupled to the first terminal group, the I/O circuit configured to input or output the data, (See Fig 2, paragraph [0052], illustrates channel interface 103 is an I/O interface which is configured to input or output data with the memory chip CP and host via the channels CH1 and CH2)
and a control circuit coupled to the second terminal group, the control circuit configured to control the memory chip, and wherein the memory controller includes a memory interface circuit coupled to the first terminal group and the second terminal group (See Fig 2, paragraph [0061], illustrates controller 101 includes a channel interface 103 coupled to channels CH1 and CH2)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-5, 9 and 14 are rejected under 35 U.S.C. 103 as being
unpatentable over Yu et al. (US 20090037652 A1) in view of YASUDA et al. (US 20220398043 A1) hereinafter Yu and YASUDA.
Regarding claim 1, Yu teaches A memory system comprising: a memory chip
including a first terminal group used for transmitting or receiving data and (See Fig 1A, paragraph [0037] and [0038], illustrates a memory system which includes memory chip 68, controller 76 for driving and sending signals thru bus 38)
a second terminal group used for receiving a packet, and configured to store the data in a non-volatile manner; (See Fig 1A, paragraph [0038] and [0041], illustrates a second controller 76’ for detecting and generating packets for start and stop patterns and also is configured to store data in flash memory 68 in nonvolatile manner)
and a memory controller configured to control the memory chip, transmit or receive the data to and from the memory chip via the first terminal group, and transmit the packet to the memory chip via the second terminal group, (See Fig 1A, paragraph [0041], illustrates smart storage transaction manager 36 sends and receives data and packets to and from memory chip 68 via two NVM CTRLs 76)
Yu teaches memory system with data packet management above. However, Yu does not explicitly teach wherein in a case where a first data transfer from the memory controller to the memory chip via the first terminal group is performed once within a predetermined time period,
the memory controller transmits to the memory chip a first packet indicating a start of the first data transfer and a second packet indicating an end of the first data transfer via the second terminal group,
and in a case where the second data transfer and a third data transfer from the memory controller to the memory chip via the first terminal group are successively performed within the predetermined time period, the memory controller transmits to the memory chip a third packet indicating a start of the third data transfer via the second terminal group between a first the second data transfer and the third data transfer,
and omits transmitting a fourth packet corresponding to indicating an end of the second data transfer between the second data transfer and the third data transfer
On the other hand, YASUDA which also relates to memory system with data
packet management teaches wherein in a case where a first data transfer from the memory controller to the memory chip via the first terminal group is performed once within a predetermined time period, (See Fig 1 and 4, paragraph [0076], illustrates data transfer is done from host or memory controller to memory chip MC0 via first channel group CH0 within a time period)
the memory controller transmits to the memory chip a first packet indicating a start of the first data transfer and a second packet indicating an end of the first data transfer via the second terminal group, (See Fig 1 and 5, paragraph [0083], illustrates periods tWHR2(1) to tWHR2(8) are alternately started and ended via first group channel Ch0 and second group channel Ch1 for data transfer operation for two memory chips)
and in a case where the second data transfer and a third data transfer from the memory controller to the memory chip via the first terminal group are successively performed within the predetermined time period, the memory controller transmits to the memory chip a third packet indicating a start of the third data transfer via the second terminal group between a first the second data transfer and the third data transfer, (See Fig 1 and 5, paragraph [0087], illustrates periods tR(1) to tR(8) start and end alternately for first group channel Ch0 and the second group channel Ch1 where sense operation indicating start or ending data transfer may be performed in parallel between first group channel Ch0 and second group channel Ch1)
and omits transmitting a fourth packet corresponding to indicating an end of the second data transfer between the second data transfer and the third data transfer (See Fig 1 and 5, paragraph [0087], illustrates sense operation of ending of data transfer operations for first group and second group via first and second channels can be done in parallel when transfer operation happens omitting need of transmitting exclusive sense operation for another transfer)
Both Yu and YASUDA relate to memory system with data packet management
(see Yu, abstract, and see YASUDA, abstract, regarding data packet management in
memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu with YASUDA by incorporating
data packet management in memory system, as taught by YASUDA, to
enable data transfer to be done from host or memory controller to memory chip MC0 via first channel group CH0 within a time period and periods tWHR2(1) to tWHR2(8) to be alternately started and ended via first group channel Ch0 and second group channel Ch1 for data transfer operation for two memory chips and periods tR(1) to tR(8) to start and end alternately for first group channel Ch0 and the second group channel Ch1 where sense operation indicating start or ending data transfer may be performed in parallel between first group channel Ch0 and second group channel Ch1 and sense operation of ending of data transfer operations for first group and second group via first and second channels may be done in parallel when transfer operation happens omitting need for transmitting exclusive sense operation for one transfer. The combined system of Yu – YASUDA allows data transfer performance between the host and the plurality of chips to be improved as mentioned in paragraph [0042]. Therefore, the combination of Yu - YASUDA improves data transfer performance. See YASUDA, paragraph [0041].
Examiner notes that claim 1 recites, “in a case where a transfer operation of the data to the memory chip is performed once, the memory controller transmits to the memory chip a first packet indicating a start of data transfer and a second packet indicating end of the data transfer, and in a case where the transfer operation of the data to the memory chip is successively performed twice, the memory controller transmits to the memory chip the first packet corresponding to a second data transfer between a first data transfer and the second data transfer, and does not transmit the second packet corresponding to the first data transfer” However, the broadest reasonable interpretation is that memory controller transmits data to memory chip either single packet to start data transfer or two successive packets to transfer data. See MPEP 2111.04, contingent limitations, See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016). Also See MPEP 2103.I.C, Review the claims where Language that suggests or makes a feature or step optional but does not require that feature or step does not limit the scope of a claim under the broadest reasonable claim interpretation.
Regarding claim 4, Yu in view of YASUDA teaches memory system with data packet management in claim 1. However, Yu - YASUDA combination does not explicitly teach The memory system according to claim 1, wherein each of the third packet and the fourth packet includes a packet header indicating types of information and a packet body indicating contents of information
On the other hand, Yu which also relates to memory system with data
packet management teaches The memory system according to claim 1, wherein each of the third packet and the fourth packet includes a packet header indicating types of information and a packet body indicating contents of information. (See Fig 2, paragraph [0054], illustrates a combined packet may include command which says what type of transaction, data as contents and handshake information to end transaction)
The same motivation that was utilized for combining Yu and YASUDA as set
forth in claim 1 is equally applicable to claim 4.
Regarding claim 5, Yu in view of YASUDA teaches memory system with data packet management in claim 4. However, Yu - YASUDA combination does not explicitly teach The memory system according to claim 4, wherein the types of information include a command, an address and status information
On the other hand, Yu which also relates to memory system with data
packet management teaches The memory system according to claim 4, wherein the types of information include a command, an address and status information. (See Fig 2, paragraph [0050], illustrates Virtual storage bridges 42, 43 are protocol bridges that detect or generate packet inserts higher level functions like device addresses, packet types and commands)
The same motivation that was utilized for combining Yu and YASUDA as set
forth in claim 1 is equally applicable to claim 5.
Regarding claim 9, Yu teaches A memory system comprising: a first memory chip and a second memory chip, each of which includes a first terminal group used for transmitting or receiving data (See Fig 1A, paragraph [0037] and [0038], illustrates a memory system which includes memory chip 68, controller 76 for driving and sending signals thru bus 38)
and a second terminal group used for receiving a packet, and each of which is configured to store the data in a non-volatile manner; (See Fig 1A, paragraph [0038] and [0041], illustrates a second controller 76’ for detecting and generating packets for start and stop patterns and also is configured to store data in flash memory 68 in non volatile manner)
a bridge chip coupled to the first terminal group and the second terminal group of the first memory chip via a first channel and coupled to the first terminal group and the second terminal group of the second memory chip via a second channel; and (See Fig 1A, paragraph [0043], illustrates a virtual storage bridge 42 is connected to terminal groups NVM CTRL 76 via MUX/DEMUX 41 thru 2 channels or buses)
a memory controller coupled to the bridge chip and transmitting or receiving the data to and from the first memory chip and the second memory chip via the bridge chip, (See Fig 1A, paragraph [0041], illustrates smart storage transaction manager 36 sends and receives data and packets to and from memory chip 68 via two NVM CTRLs 76)
Yu teaches memory system with data packet management above. However, Yu does not explicitly teach wherein in a case where a first data transfer from the memory controller to the bridge chip is performed once within a predetermined time period,
the memory controller transmits to the bridge chip a first packet indicating a start of the first data transfer and a second packet indicating an end of the first data transfer,
and in a case where the second data transfer and a third data transfer from the memory controller to the bridge chip are successively performed within the predetermined time period, the memory controller transmits to the bridge chip a third packet indicating a start of the third data transfer via the second terminal group between a first the second data transfer and the third data transfer,
and omits transmitting a fourth packet corresponding to indicating an end of the second data transfer between the second data transfer and the third data transfer
On the other hand, YASUDA which also relates to memory system with data
packet management teaches wherein in a case where a first data transfer from the memory controller to the bridge chip is performed once within a predetermined time period, (See Fig 1 and 4, paragraph [0076], illustrates data transfer is done from host or memory controller to memory chip MC0 via first channel group CH0 within a time period)
the memory controller transmits to the bridge chip a first packet indicating a start of the first data transfer and a second packet indicating an end of the first data transfer, (See Fig 1 and 5, paragraph [0083], illustrates periods tWHR2(1) to tWHR2(8) are alternately started and ended via first group channel Ch0 and second group channel Ch1 for data transfer operation for two memory chips)
and in a case where the second data transfer and a third data transfer from the memory controller to the bridge chip are successively performed within the predetermined time period, the memory controller transmits to the bridge chip a third packet indicating a start of the third data transfer via the second terminal group between a first the second data transfer and the third data transfer, (See Fig 1 and 5, paragraph [0087], illustrates periods tR(1) to tR(8) start and end alternately for first group channel Ch0 and the second group channel Ch1 where sense operation indicating start or ending data transfer may be performed in parallel between first group channel Ch0 and second group channel Ch1)
and omits transmitting a fourth packet corresponding to indicating an end of the second data transfer between the second data transfer and the third data transfer (See Fig 1 and 5, paragraph [0087], illustrates sense operation of ending of data transfer operations for first group and second group via first and second channels can be done in parallel when transfer operation happens omitting need of transmitting exclusive sense operation for another transfer)
Both Yu and YASUDA relate to memory system with data packet management
(see Yu, abstract, and see YASUDA, abstract, regarding data packet management in
memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu with YASUDA by incorporating
data packet management in memory system, as taught by YASUDA, to
enable data transfer to be done from host or memory controller to memory chip MC0 via first channel group CH0 within a time period and periods tWHR2(1) to tWHR2(8) to be alternately started and ended via first group channel Ch0 and second group channel Ch1 for data transfer operation for two memory chips and periods tR(1) to tR(8) to start and end alternately for first group channel Ch0 and the second group channel Ch1 where sense operation indicating start or ending data transfer may be performed in parallel between first group channel Ch0 and second group channel Ch1 and sense operation of ending of data transfer operations for first group and second group via first and second channels may be done in parallel when transfer operation happens omitting need for transmitting exclusive sense operation for one transfer. The combined system of Yu – YASUDA allows data transfer performance between the host and the plurality of chips to be improved as mentioned in paragraph [0042]. Therefore, the combination of Yu - YASUDA improves data transfer performance. See YASUDA, paragraph [0041].
Examiner notes that claim 1 recites, “in a case where a transfer operation of the data to the memory chip is performed once, the memory controller transmits to the memory chip a first packet indicating a start of data transfer and a second packet indicating end of the data transfer, and in a case where the transfer operation of the data to the memory chip is successively performed twice, the memory controller transmits to the memory chip the first packet corresponding to a second data transfer between a first data transfer and the second data transfer, and does not transmit the second packet corresponding to the first data transfer” However, the broadest reasonable interpretation is that memory controller transmits data to memory chip either single packet to start data transfer or two successive packets to transfer data. See MPEP 2111.04, contingent limitations, See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016). Also See MPEP 2103.I.C, Review the claims where Language that suggests or makes a feature or step optional but does not require that feature or step does not limit the scope of a claim under the broadest reasonable claim interpretation.
Regarding claim 14, Yu in view of YASUDA teaches memory system with data packet management in claim 9. However, Yu - YASUDA combination does not explicitly teach The memory system according to claim 9, wherein in a case where data is transmitted through a fourth data transfer from the first memory chip to the memory controller via the bridge chip, the bridge chip transmits a fifth packet indicating a start of the fourth data transfer before the fourth data transfer.
On the other hand, Yu which also relates to memory system with data
packet management teaches The memory system according to claim 9, wherein in a case where data is transmitted through a fourth data transfer from the first memory chip to the memory controller via the bridge chip, the bridge chip transmits a fifth packet indicating a start of the fourth data transfer before the fourth data transfer. (See Fig 1A, paragraph [0043], illustrates packets for the nest transaction can be re-ordered by smart storage switch 30 which includes virtual buffer bridge 32 and send NVM controllers 76)
The same motivation that was utilized for combining Yu and YASUDA as set
forth in claim 9 is equally applicable to claim 14.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20090037652 A1) in view of YASUDA et al. (US 20220398043 A1) and further in view of SUZUKI et al. (US 20220414044 A1) hereinafter Yu and YASUDA and SUZUKI.
Regarding claim 16, Yu teaches A memory system comprising: a first memory chip and a second memory chip, each of which includes a first terminal group used for transmitting or receiving data and (See Fig 1A, paragraph [0037] and [0038], illustrates a memory system which includes memory chip 68, controller 76 for driving and sending signals thru bus 38)
a second terminal group used for receiving a packet, and each of which is configured to store the data in a non-volatile manner; (See Fig 1A, paragraph [0038] and [0041], illustrates a second controller 76’ for detecting and generating packets for start and stop patterns and also is configured to store data in flash memory 68 in nonvolatile manner)
a bridge chip coupled to the first terminal group and the second terminal group of the first memory chip via a first channel and coupled to the first terminal group and the second terminal group of the second memory chip via a second channel; and (See Fig 1A, paragraph [0043], illustrates a virtual storage bridge 42 is connected to terminal groups NVM CTRL 76 via MUX/DEMUX 41 thru 2 channels or buses)
a memory controller coupled to the bridge chip and configured to transmit or receive the data to or from the first memory chip and the second memory chip via the bridge chip, (See Fig 1A, paragraph [0041], illustrates smart storage transaction manager 36 sends and receives data and packets to and from memory chip 68 via two NVM CTRLs 76)
wherein the bridge chip includes: a counter that counts a transferred data size of the data transfer a first memory corresponding to the first channel; a second memory corresponding to the second channel; and a switch that selectively couples either the first memory or the second memory to the memory controller based on the transferred data size counted and the threshold data size (See Fig 7, paragraph [0083] and [0086], illustrates at step 190 NVM controller 76 receives a special command from the smart storage switch and make determination of physical capacity of flash memory controlled by the NVM controller where data stripe depth is set by smart switch based on data size)
Yu teaches memory system with data packet management above. However, Yu does not explicitly teach and the memory controller transmits a first packet indicating a start of the second data transfer to the bridge chip during the first data transfer, and omits transmitting a second packet indicating an end of the first data transfer between the first data transfer and the second data transfer
On the other hand, YASUDA which also relates to memory system with data
packet management teaches and the memory controller transmits a first packet indicating a start of the second data transfer to the bridge chip during the first data transfer, and omits transmitting a second packet indicating an end of the first data transfer between the first data transfer and the second data transfer (See Fig 1 and 5, paragraph [0087], illustrates sense operation of ending of data transfer operations for first group and second group via first and second channels can be done in parallel when transfer operation happens omitting need of transmitting exclusive sense operation for another transfer)
Both Yu and YASUDA relate to memory system with data packet management
(see Yu, abstract, and see YASUDA, abstract, regarding data packet management in
memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu with YASUDA by incorporating
data packet management in memory system, as taught by YASUDA, to
enable data transfer to be done from host or memory controller to memory chip MC0 via first channel group CH0 within a time period and periods tWHR2(1) to tWHR2(8) to be alternately started and ended via first group channel Ch0 and second group channel Ch1 for data transfer operation for two memory chips and periods tR(1) to tR(8) to start and end alternately for first group channel Ch0 and the second group channel Ch1 where sense operation indicating start or ending data transfer may be performed in parallel between first group channel Ch0 and second group channel Ch1 and sense operation of ending of data transfer operations for first group and second group via first and second channels may be done in parallel when transfer operation happens omitting need for transmitting exclusive sense operation for one transfer. The combined system of Yu – YASUDA allows data transfer performance between the host and the plurality of chips to be improved as mentioned in paragraph [0042]. Therefore, the combination of Yu - YASUDA improves data transfer performance. See YASUDA, paragraph [0041].
Yu in view of YASUDA teaches memory system with data packet management above. However, Yu - YASUDA combination does not explicitly teach wherein the bridge chip is configured to set a threshold data size of a data transfer between the memory controller and the first memory chip through the bridge chip, or between the memory controller and the second memory chip through the bridge chip;
wherein in a case where a first data transfer from the first memory chip to the memory controller through the bridge chip and a second data transfer from the second memory chip to the memory controller through the bridge chip are executed in succession, the counter configures the switch to change the coupling of the memory controller from the first memory to the second memory, upon the transferred data size of the first data transfer reaching the threshold data size,
On the other hand, SUZUKI which also relates to memory system with data
packet management teaches wherein the bridge chip is configured to set a threshold data size of a data transfer between the memory controller and the first memory chip through the bridge chip, or between the memory controller and the second memory chip through the bridge chip; (See Fig 10, paragraph [0176], illustrates controller 101b calculates a data size by multiplying a size of data concerned indicated by the size information register 121 by (1−1/N), and set the value to the threshold for data moving through bridge chip to memory chips)
wherein in a case where a first data transfer from the first memory chip to the memory controller through the bridge chip and a second data transfer from the second memory chip to the memory controller through the bridge chip are executed in succession, the counter configures the switch to change the coupling of the memory controller from the first memory to the second memory, upon the transferred data size of the first data transfer reaching the threshold data size, (See Fig 11 and 12, paragraph [0188] and [0190], illustrates in step S803 controller makes determination if amount of data in buffer reached threshold and based on that host causes chip enable CEn to transition from active state to inactive state and vice versa. In other words, switching bridge enable CEn causes active state to switch for data transfer between channels for two different memory chips)
Both Yu and YASUDA and SUZUKI relate to memory system with data packet management (see Yu, abstract, and see YASUDA, abstract, and see SUZUKI, abstract, regarding data packet management in memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu - YASUDA combination with SUZUKI by incorporating data packet management in memory system, as taught by SUZUKI, to
enable controller 101b to calculate a data size by multiplying a size of data concerned indicated by the size information register 121 by (1−1/N), and set the value to the threshold for data moving through bridge chip to memory chips and controller makes determination if amount of data in buffer reached threshold and based on that host causes chip enable CEn to transition from active state to inactive state and vice versa. In other words, switching bridge enable CEn causes active state to switch for data transfer between channels for two different memory chips. The combined system of Yu – YASUDA - SUZUKI allows improvement in data transfer rate between the host HA and the memory chips CP as mentioned in paragraph [0090]. Therefore, the combination of Yu - YASUDA - SUZUKI improves transfer performance. See SUZUKI, paragraph [0032].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of YASUDA and further in view of UM10204 I2C-bus specification and user manual (Rev. 03 -19 June 2007) hereinafter UM10204.
Regarding claim 12, Yu in view of YASUDA teaches memory system with data packet management in claim 9. However, Yu - YASUDA combination does not explicitly teach The memory system according to claim 9, wherein in a case where a fourth data transfer and a fifth data transfer from the bridge chip to the first memory chip are successively performed within the predetermined time period, the bridge chip transmits to the first memory chip a fifth packet indicating a start of the fourth data transfer between the fourth data transfer and the fifth data transfer and a sixth packet indicating an end of the fifth data transfer between the fourth data transfer and the fifth data transfer, wherein the fourth data transfer from the bridge chip to the first memory chip corresponds to the second data transfer from the memory controller to the bridge chip, and wherein the fifth data transfer from the bridge chip to the first memory chip corresponds to the third data transfer from the memory controller to the bridge chip
On the other hand, UM10204 which also relates to memory system with data packet management teaches The memory system according to claim 9, wherein in a case where a fourth data transfer and a fifth data transfer from the bridge chip to the first memory chip are successively performed within the predetermined time period, the bridge chip transmits to the first memory chip a fifth packet indicating a start of the fourth data transfer between the fourth data transfer and the fifth data transfer and a sixth packet indicating an end of the fifth data transfer between the fourth data transfer and the fifth data transfer, wherein the fourth data transfer from the bridge chip to the first memory chip corresponds to the second data transfer from the memory controller to the bridge chip, and wherein the fifth data transfer from the bridge chip to the first memory chip corresponds to the third data transfer from the memory controller to the bridge chip. (See Fig 5, paragraph 3.4, page 9, illustrates START and STOP conditions are generated by master where bus is considered to be busy after START and free again after STOP condition and also busy stays busy if repeated START is generated instead of STOP condition. In other words, first and second packets can be transmitted before first data transfer and examiner considers same repeated operations for number of data transfers)
Both Yu and YASUDA and UM10204 relate to memory system with data packet management (see Yu, abstract, and see YASUDA, abstract, see UM10204, abstract, regarding data packet management in memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu - YASUDA combination with UM10204 by incorporating data packet management in memory system, as taught by UM10204, to
enable data packet management where first and second packets can be transmitted before first data transfer. The combined system of Yu - YASUDA – UM10204 allows comprehensive introduction to data transfer, handshaking and bus arbitration as mentioned in page 3 paragraph 1. Therefore, the combination of Yu - YASUDA - UM10204 improves data transfer scheme. See UM10204, page 3 paragraph 1.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of YASUDA and further in view of SUZUKI and further in view of UM10204 I2C-bus specification and user manual (Rev. 03 -19 June 2007).
Regarding claim 20, Yu in view of YASUDA and further in view of SUZUKI teaches memory system with data packet management in claim 16. However, Yu - YASUDA - SUZUKI combination does not explicitly teach The memory system according to claim 16, wherein upon receipt of a command from the memory controller indicating an execution of an output operation of data of the first data transfer, the bridge chip transmits to the first memory chip a first packet indicating a start of a third data transfer corresponding to the output operation from the first memory chip to the bridge chip before the bridge chip receiving, from the memory controller, a second packet indicating a start of a fourth data transfer corresponding to the output operation from the bridge chip to the memory controller. the first packet corresponding to the transfer operation of the first data is received from the memory controller
On the other hand, Yu which also relates to memory system with data packet management teaches The memory system according to claim 16, wherein upon receipt of a command from the memory controller indicating an execution of an output operation of data of the first data transfer, the bridge chip transmits to the first memory chip a first packet indicating a start of a third data transfer corresponding to the output operation from the first memory chip to the bridge chip before the bridge chip receiving, from the memory controller, a second packet indicating a start of a fourth data transfer corresponding to the output operation from the bridge chip to the memory controller. the first packet corresponding to the transfer operation of the first data is received from the memory controller. (See Fig 1A, paragraph [0043], illustrates smart storage transaction manager 36 can re-order packets rather than having all packets for a first transaction complete before the next transaction begins where packets for next transaction are re-ordered before sending to NVM controller. In other words, transactions can be overlapped)
Both Yu and YASUDA and SUZUKI and UM10204 relate to memory system with data packet management (see Yu, abstract, and see YASUDA, and see SUZUKI, abstract, see UM10204, abstract, regarding data packet management in memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu - YASUDA - SUZUKI combination with UM10204 by incorporating data packet management in memory system, as taught by UM10204, to enable smart storage transaction manager 36 to re-order packets rather than having all packets for a first transaction complete before the next transaction begins where packets for next transaction are re-ordered before sending to NVM controller. In other words, transactions can be overlapped. The combined system of Yu – YASUDA - SUZUKI – UM10204 allows comprehensive introduction to data transfer, handshaking and bus arbitration as mentioned in page 3 paragraph 1. Therefore, the combination of Yu - YASUDA - SUZUKI - UM10204 improves data transfer scheme. See UM10204, page 3 paragraph 1.
Claim 3, 6-7, 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of YASUDA and further in view of Park et al. (US 20040252689 A1) hereinafter Park.
Regarding claim 3, Yu in view of YASUDA teaches memory system with data packet management in claim 1. However, Yu - YASUDA combination does not explicitly teach The memory system according to claim 1, wherein the memory controller executes i) a part of transmission of the third packet to the memory chip via the second terminal group and ii) a part the second data transfer or the third data transfer via the first terminal group in parallel
On the other hand, Park which also relates to memory system with data packet management teaches The memory system according to claim 1, wherein the memory controller executes i) a part of transmission of the third packet to the memory chip via the second terminal group and ii) a part the second data transfer or the third data transfer via the first terminal group in parallel. (See Fig 1, paragraph [0031], illustrates Data packets are preferably transmitted from memory controller 110 in either a parallel and/or series manner where data packets PKT0[m:0] through PKTn[m:0] are transferred to packet controller 120 during predetermined clock cycle)
Both Yu and YASUDA and Park relate to memory system with data packet management (see Yu, abstract, and see YASUDA, abstract, and see Park, abstract, regarding data packet management in memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu - YASUDA combination with Park by incorporating data packet management in memory system, as taught by Park, to
enable Data packets to be preferably transmitted from memory controller in either a parallel and/or series manner where data packets are transferred to packet controller during predetermined clock cycle. The combined system of Yu - YASUDA – Park allows synchronous memory reception of the address and control signals in response to the clock signal as mentioned in paragraph [0009]. Therefore, the combination of Yu - YASUDA - Park improves pin efficiency. See Park, paragraph [0007].
Regarding claim 6, Yu in view of YASUDA teaches memory system with data packet management in claim 1. However, Yu - YASUDA combination does not explicitly teach The memory system according to claim 1, wherein the first terminal group includes a first terminal used for input/output of a first signal indicating the data, a second terminal used for input/output of a strobe signal of the first signal, and a third terminal used for input of a read enable signal
On the other hand, Park which also relates to memory system with data packet management teaches The memory system according to claim 1, wherein the first terminal group includes a first terminal used for input/output of a first signal indicating the data, a second terminal used for input/output of a strobe signal of the first signal, and a third terminal used for input of a read enable signal. (See Fig 2, paragraph [0038], illustrates standard memory access where data packets are converted into address signals, control signals which includes strobe signals and enable signals)
Both Yu and YASUDA and Park relate to memory system with data packet management (see Yu, abstract, and see YASUDA, abstract, and see Park, abstract, regarding data packet management in memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu - YASUDA combination with Park by incorporating data packet management in memory system, as taught by Park, to enable standard memory access where data packets are converted into address signals, control signals which includes strobe signals and enable signals. The combined system of Yu - YASUDA – Park allows synchronous memory reception of the address and control signals in response to the clock signal as mentioned in paragraph [0009]. Therefore, the combination of Yu - YASUDA - Park improves pin efficiency. See Park, paragraph [0007].
Regarding claim 7, Yu in view of YASUDA teaches memory system with data packet management in claim 6. However, Yu - YASUDA combination does not explicitly teach The memory system according to claim 6, wherein the second terminal group includes a fourth terminal used for input/output of a second signal indicating the first packet and the second packet, a fifth terminal used for transmission of a strobe signal of the second signal, and a sixth terminal used for input of a chip enable signal
On the other hand, Park which also relates to memory system with data packet management teaches The memory system according to claim 6, wherein the second terminal group includes a fourth terminal used for input/output of a second signal indicating the first packet and the second packet, a fifth terminal used for transmission of a strobe signal of the second signal, and a sixth terminal used for input of a chip enable signal. (See Fig 2, paragraph [0038], illustrates standard memory access where data packets are converted into address signals, control signals which includes strobe signals and enable signals)
The same motivation that was utilized for combining Yu - YASUDA combination and Park as set forth in claim 6 is equally applicable to claim 7.
Regarding claim 11, Yu in view of YASUDA teaches memory system with data packet management in claim 9. However, Yu - YASUDA combination does not explicitly teach The memory system according to claim 9, wherein the memory controller executes i)a part of transmission of the third packet to the bridge chip and ii)_a part of the second data transfer or the third data transfer in parallel
On the other hand, Park which also relates to memory system with data packet management teaches The memory system according to claim 9, wherein the memory controller executes i)a part of transmission of the third packet to the bridge chip and ii)_a part of the second data transfer or the third data transfer in parallel. (See Fig 1, paragraph [0031], illustrates Data packets are preferably transmitted from memory controller 110 in either a parallel and/or series manner where data packets PKT0[m:0] through PKTn[m:0] are transferred to packet controller 120 during predetermined clock cycle)
Both Yu and YASUDA and Park relate to memory system with data packet management (see Yu, abstract, and see YASUDA, abstract, and see Park, abstract, regarding data packet management in memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu - YASUDA combination with Park by incorporating data packet management in memory system, as taught by Park, to
enable Data packets to be preferably transmitted from memory controller in either a parallel and/or series manner where data packets are transferred to packet controller during predetermined clock cycle. The combined system of Yu - YASUDA – Park allows synchronous memory reception of the address and control signals in response to the clock signal as mentioned in paragraph [0009]. Therefore, the combination of Yu - YASUDA - Park improves pin efficiency. See Park, paragraph [0007].
Regarding claim 13, Yu in view of YASUDA teaches memory system with data packet management in claim 9. However, Yu - YASUDA combination does not explicitly teach The memory system according to claim 9, wherein the bridge chip executes i)a part of fourth data transfer to the first memory chip and ii)_a part of fifth data transfer to the second memory chip in parallel
On the other hand, Park which also relates to memory system with data packet management teaches The memory system according to claim 9, wherein the bridge chip executes i)a part of fourth data transfer to the first memory chip and ii)_a part of fifth data transfer to the second memory chip in parallel. (See Fig 1, paragraph [0031], illustrates Data packets are preferably transmitted from memory controller 110 in either a parallel and/or series manner where data packets PKT0[m:0] through PKTn[m:0] are transferred to packet controller 120 during predetermined clock cycle)
Both Yu and YASUDA and Park relate to memory system with data packet management (see Yu, abstract, and see YASUDA, abstract, and see Park, abstract, regarding data packet management in memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu - YASUDA combination with Park by incorporating data packet management in memory system, as taught by Park, to
enable Data packets to be preferably transmitted from memory controller in either a parallel and/or series manner where data packets are transferred to packet controller during predetermined clock cycle. The combined system of Yu - YASUDA – Park allows synchronous memory reception of the address and control signals in response to the clock signal as mentioned in paragraph [0009]. Therefore, the combination of Yu - YASUDA - Park improves pin efficiency. See Park, paragraph [0007].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over
Yu in view of YASUDA and further in view of Park and further in view of SUZUKI et al. (US 20210294521 A1) hereinafter Yu and Park and SUZUKI2.
Regarding claim 8, Yu in view of YASUDA and further in view of Park teaches memory system with data packet management in claim 7. However, Yu - YASUDA - Park combination does not explicitly teach The memory system according to claim 7, wherein the memory chip captures the second signal received from the fourth terminal, based on rising and falling of the strobe signal received from the fifth terminal
On the other hand, SUZUKI2 which also relates to memory system with data packet management teaches The memory system according to claim 7, wherein the memory chip captures the second signal received from the fourth terminal, based on rising and falling of the strobe signal received from the fifth terminal. (See Fig 2, 3A-3C, paragraph [0022], illustrates double edge of timing signals which means both rising and falling edges are used for strobing transfer data)
Both Yu, YASUDA, Park and SUZUKI2 relate to memory system with data packet management (see Yu, abstract, see YASUDA, abstract, see Park, abstract, and see SUZUKI2, abstract, regarding data packet management in memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu - YASUDA - Park combination with SUZUKI2 by incorporating data packet management in memory system, as taught by SUZUKI2, to enable double edge of timing signals which means both rising and falling edges are used for strobing transfer data. The combined system of Yu - YASUDA - Park – SUZUKI2 allows communication speed between the bridge chip and external terminal to not exceed the communication speed of the channel for each memory channel as mentioned in paragraph [0015]. Therefore, the combination of Yu - YASUDA - Park – SUZUKI2 improves data transfer speed. See SUZUKI2, paragraph [0016].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over
Yu in view of YASUDA and further in view of SUZUKI et al. (US 20210294521 A1) hereinafter Yu and SUZUKI2.
Regarding claim 15, Yu in view of YASUDA teaches memory system with data packet management in claim 9. However, Yu - YASUDA combination does not explicitly teach The memory system according to claim 9, wherein a data transfer speed between the memory controller and the bridge chip is higher than a data transfer speed between the bridge chip and the first memory chip or the second memory chip
On the other hand, SUZUKI2 which also relates to memory system with data packet management teaches The memory system according to claim 9, wherein a data transfer speed between the memory controller and the bridge chip is higher than a data transfer speed between the bridge chip and the first memory chip or the second memory chip. (See Fig 1, paragraph [0013], illustrates communication speed between the bridge chip and external terminal may not exceed the communication speed of the channel for each memory channel. In other words, speed of memory controller and bridge chip is higher than bridge chip and external terminal)
Both Yu, YASUDA and SUZUKI2 relate to memory system with data packet management (see Yu, abstract, see YASUDA, abstract, and see SUZUKI2, abstract, regarding data packet management in memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu - YASUDA combination with SUZUKI2 by incorporating data packet management in memory system, as taught by SUZUKI2, to enable double edge of timing signals which means both rising and falling edges are used for strobing transfer data. The combined system of Yu - YASUDA - SUZUKI2 allows communication speed between the bridge chip and external terminal to not exceed the communication speed of the channel for each memory channel as mentioned in paragraph [0015]. Therefore, the combination of Yu - YASUDA - SUZUKI2 improves data transfer speed. See SUZUKI2, paragraph [0016].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over
Yu in view of YASUDA and further in view of SUZUKI and further in view of Park et al. (US 20040252689 A1) hereinafter Park.
Regarding claim 19, Yu in view of YASUDA and further in view of SUZUKI teaches memory system with data packet management in claim 16. However, Yu - YASUDA - SUZUKI combination does not explicitly teach The memory system according to claim 16, wherein data transferred by the first data transfer includes a plurality of data frames, and the memory controller transmits the first packet indicating the start of the second data transfer to the bridge chip during transfer of a last data frame of the plurality of data frames from the bridge chip to the memory controller
On the other hand, Park which also relates to memory system with data packet management teaches The memory system according to claim 16, wherein data transferred by the first data transfer includes a plurality of data frames, and the memory controller transmits the first packet indicating the start of the second data transfer to the bridge chip during transfer of a last data frame of the plurality of data frames from the bridge chip to the memory controller. (See Fig 2 and 3, paragraph [0041] and [0042], illustrates Data packets are preferably transmitted from memory controller 110 or data transfer operations can be done in overlapping or in parallel fashion)
Both Yu, YASUDA, SUZUKI and Park relate to memory system with data packet management (see Yu, abstract, see YASUDA, abstract, see SUZUKI, abstract, and see Park, abstract, regarding data packet management in memory system).
Therefore, it would have been obvious to one of ordinary skill at the time the
invention was effectively filed to combine Yu - YASUDA - SUZUKI combination with Park by incorporating data packet management in memory system, as taught by Park, to enable double edge of timing signals which means both rising and falling edges are used for strobing transfer data. The combined system of Yu - YASUDA - SUZUKI - Park allows synchronous memory reception of the address and control signals in response to the clock signal as mentioned in paragraph [0009]. Therefore, the combination of Yu - YASUDA - SUZUKI - Park improves pin efficiency. See Park, paragraph [0007].
Response to Arguments
Applicant’s arguments filed on 03/23/2026 have been fully considered but they
are not persuasive.
Applicant’s first argument is claims 1,9 and 16 mapping by primary reference
Yu in page 12 of the response: Yu does not disclose a memory system having the above elements. The Office Action points to controller 76 for driving and sending signals and controller 76' for detecting and generating packets. Yu states that controllers 76 provide driving and receiving differential signals and detecting and generating packets and are located in the smart storage switch 30. Yu does not disclose that the memory chips 68 have the controllers 76, 76'. Yu does not disclose the memory chip of Claim 1 having the two terminal groups
In summary, applicant argued that primary reference Yu does not
teach memory chips having controllers and two terminal groups. The amendment necessitates adding secondary reference YASUDA in this regard. For further clarification examiner cites portion from YASUDA. Also, for applicant’s understanding examiner would like to explain the teachings of YASUDA and examiner’s interpretation in more detail here. See Fig 1 and 4, paragraph [0076], YASUDA teaches data transfer is done from host or memory controller to memory chip MC0 via first channel group CH0 within a time period. Also See Fig 1 and 5, paragraph [0083], YASUDA teaches periods tWHR2(1) to tWHR2(8) are alternately started and ended via first group channel Ch0 and second group channel Ch1 for data transfer operation for two memory chips. In the cited portions YASUDA clearly teaches data transfer is done by memory controller via first channel group CH0 and second channel group CH1. Thus, the rejection of amended claims 1,9 and 16 are maintained.
Applicant’s second argument is claims 1,9 and 16 mapping by primary reference
Yu in page 12 of the response: The Office Action points to [0043] regarding the last two above-noted paragraphs. The memory controller of Claim 1 transmits to the memory chip a third packet indicating a start of the third data transfer via the second terminal group between the second data transfer and the third data transfer, and omits transmitting a fourth packet indicating an end of the second data transfer between the second data transfer and the third data transfer. [0043] merely describes reordering packets to allow more time for access to occur for the next transaction so that transactions are overlapped by the reordering. There is no mention of a memory controller omitting a packet indicating an end of a second data transfer between the second and third data transfers as recited in Claim 1. Yu is also missing this element of Claim 1
In summary, applicant argued that primary reference Yu does not
teach omitting a particular data transfer indicating other data transfers are happening. The amendment necessitates adding secondary reference YASUDA in this regard. For further clarification examiner cites portion from YASUDA. Also, for applicant’s understanding examiner would like to explain the teachings of YASUDA and examiner’s interpretation in more detail here. See Fig 1 and 5, paragraph [0087], YASUDA teaches sense operation of ending of data transfer operations for first group and second group via first and second channels can be done in parallel when transfer operation happens omitting need of transmitting exclusive sense operation for another transfer. In the cited portions YASUDA clearly teaches data transfer operations can be done in parallel when transfer operation happens omitting need of transmitting exclusive sense operation for another transfer. Thus, the rejection of amended claims 1,9 and 16 are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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