DETAILED ACTION
1. This Office Action is taken in response to Applicants’ application 18/974,331 filed on 12/9/2024.
Claims 1-20 are pending for consideration.
2. Examiner’s Note
(1) In the case of amending the Claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. This will assist in expediting compact prosecution. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.131(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient.
(2) Examiner has cited particular columns/paragraph and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Objections
3. Claims 1-15 are objected to because of the following informalities:
Claim 1 recites “a storage cluster that includes one or more storage devices;” and “wherein the storage devices of the storage cluster include a first storage device and a second storage device.” The phrase “wherein the storage devices” should be “wherein the one or more storage devices.”
In fact, since the limitation “wherein the storage devices of the storage cluster include a first storage device and a second storage device” further limits the “one or more storage devices” to be a first storage device and a second storage device, the condition “one or more storage devices” does not apply at all. Applicant may consider combining these two limitations to recite “a storage cluster that includes a first storage device and a second storage device” instead, lust like in claim 16.
Claim 11 suffers from the same deficiency as in claim 1.
Claims 2-10 are objected to by virtue of their dependency from claim 1.
Claims 12-15 are objected to by virtue of their dependency from claim 11.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1-2, and 8-9 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Nguyen et al. (US Patent Application Publication 2018/0024768, hereinafter Nguyen).
As to claim 1, Nguyen teaches A computing system [as shown in figures 1-2, and 5] comprising:
a storage cluster that includes one or more storage devices [as shown in figures 1-2; figure 2 shows a plurality of storage devices (240a-240e), where each storage device includes, as shown in figure 1, a volatile portion (114), and a non-volatile portion (124)] and
a switch providing an interface between the storage devices in the storage cluster [as shown in figure 2, where the corresponding “switch” is a “memory bus” (230) providing an interface between the storage devices in the storage cluster], wherein the storage devices of the storage cluster include a first storage device and a second storage device [as shown in figures 1-2; figure 2 shows a plurality of storage devices (240a-240e), where each storage device includes, as shown in figure 1, a volatile portion (114), and a non-volatile portion (124)], wherein the first storage device includes:
a first storage controller [memory controller, figure 2, 202];
a first non-volatile memory configured to be controlled by the first storage controller [as shown in figures 1-2; figure 2 shows a plurality of storage devices (240a-240e), where each storage device includes, as shown in figure 1, a volatile portion (114), and a non-volatile portion (124)]; and
a first volatile memory that includes a first memory region and a second memory region [as shown in figures 1-2; figure 2 shows a plurality of storage devices (240a-240e), where each storage device includes, as shown in figure 1, a volatile portion with a plurality of regions (114a-114d)], wherein the first storage device is configured to provide first data stored in the first memory region to the second storage device through the switch, based on power not being supplied at the first storage device, and wherein the first data is caching data [Memory controller 102 can transfer the persistent data 134 from the volatile portion 114 of the memory module 104 to the non-volatile portion 124 of the memory module 104, in response to the power loss condition … Although backed up persistent data 144 is shown as a single block of data, examples are not so limiting. Backed up persistent data 144 may be spread as multiple blocks throughout multiple non-volatile portions 124 of the memory module 104 … (¶ 0018-0019); In the example of FIG. 2, the memory controller can partition a subset of the memory modules 240 into non-volatile portions and volatile portions … Accordingly, memory modules 240b and 240d include both non-volatile portions and volatile portions … The backup power supply 210 can be used to perform backups, for example, in response to a power loss condition. For example, the CPU 220 may receive a power loss signal 250 indicating a power loss. Upon loss of power to the system 200, the backup power supply 210 may serve as a local finite power source to provide enough energy to continue to allow the CPU's memory controller 202 (including the DMA engine 212) to transfer the persistent data from the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, as described above … Method 300 includes moving, by the memory controller, the persistent data from the volatile portions of the plurality of memory modules to the non-volatile portions of the memory modules, in response to the interruption of primary power supply, using backup power provided by a backup power supply, at 330. For example, memory controller 202 can receive a power loss signal 250 indicating a power loss condition has occurred. In response to the power loss condition, memory controller can move the persistent data from any of the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, using backup power provided by the backup power supply 210 … (¶ 0021-0027)].
As to claim 2, Nguyen teaches The computing system of The computing system of wherein the first storage device further includes: a Power Loss Protection (PLP) circuit [The backup power supply 210 can be used to perform backups, for example, in response to a power loss condition. For example, the CPU 220 may receive a power loss signal 250 indicating a power loss. Upon loss of power to the system 200, the backup power supply 210 may serve as a local finite power source to provide enough energy to continue to allow the CPU's memory controller 202 (including the DMA engine 212) to transfer the persistent data from the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, as described above. Thus, the backup power supply 210 may provide enough energy to power at least the memory controller 202 (and the DMA engine 212), the memory bus 230, and the memory modules 240. Additional modules (not specifically shown) within the CPU 220 may also be powered as needed … (¶ 0022-0023)]; and a PLP battery connected to the PLP circuit, wherein the PLP circuit is configured to flush second data stored in the second memory region to the first non-volatile memory region using the PLP battery, based on the power not being supplied at the first storage device [The backup power supply 210 can be used to perform backups, for example, in response to a power loss condition. For example, the CPU 220 may receive a power loss signal 250 indicating a power loss. Upon loss of power to the system 200, the backup power supply 210 may serve as a local finite power source to provide enough energy to continue to allow the CPU's memory controller 202 (including the DMA engine 212) to transfer the persistent data from the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, as described above. Thus, the backup power supply 210 may provide enough energy to power at least the memory controller 202 (and the DMA engine 212), the memory bus 230, and the memory modules 240. Additional modules (not specifically shown) within the CPU 220 may also be powered as needed. Backup power supply 210 can be an energy component to convert stored energy to electrical energy to deliver power to components described above. Examples of backup power supply 210 can include, but are not limited to, a rechargeable battery, a capacitor (e.g., supercapacitor, ultracapacitor, etc.), a flywheel, and the like … (¶ 0022-0023)].
As to claim 8, Nguyen teaches The computing system of claim 1, further comprising: a memory device connected to the storage cluster through the switch, wherein the memory device includes a memory controller, wherein the memory controller is configured to, based on the power not being supplied at the first storage device, receive a request corresponding to the first data from the first storage device, and wherein the memory controller is configured to, based on receiving the request, generate information indicative of transmitting the first data to the second storage device [Memory controller 102 can transfer the persistent data 134 from the volatile portion 114 of the memory module 104 to the non-volatile portion 124 of the memory module 104, in response to the power loss condition … Although backed up persistent data 144 is shown as a single block of data, examples are not so limiting. Backed up persistent data 144 may be spread as multiple blocks throughout multiple non-volatile portions 124 of the memory module 104 … (¶ 0018-0019); In the example of FIG. 2, the memory controller can partition a subset of the memory modules 240 into non-volatile portions and volatile portions … Accordingly, memory modules 240b and 240d include both non-volatile portions and volatile portions … The backup power supply 210 can be used to perform backups, for example, in response to a power loss condition. For example, the CPU 220 may receive a power loss signal 250 indicating a power loss. Upon loss of power to the system 200, the backup power supply 210 may serve as a local finite power source to provide enough energy to continue to allow the CPU's memory controller 202 (including the DMA engine 212) to transfer the persistent data from the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, as described above … Method 300 includes moving, by the memory controller, the persistent data from the volatile portions of the plurality of memory modules to the non-volatile portions of the memory modules, in response to the interruption of primary power supply, using backup power provided by a backup power supply, at 330. For example, memory controller 202 can receive a power loss signal 250 indicating a power loss condition has occurred. In response to the power loss condition, memory controller can move the persistent data from any of the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, using backup power provided by the backup power supply 210 … (¶ 0021-0027)].
As to claim 9, Nguyen teaches The computing system of wherein the memory controller is configured to provide the information to the first storage controller through the switch, and wherein the first storage controller is configured to provide the first data to the second storage device through the switch in response to receiving the information [Memory controller 102 can transfer the persistent data 134 from the volatile portion 114 of the memory module 104 to the non-volatile portion 124 of the memory module 104, in response to the power loss condition … Although backed up persistent data 144 is shown as a single block of data, examples are not so limiting. Backed up persistent data 144 may be spread as multiple blocks throughout multiple non-volatile portions 124 of the memory module 104 … (¶ 0018-0019); In the example of FIG. 2, the memory controller can partition a subset of the memory modules 240 into non-volatile portions and volatile portions … Accordingly, memory modules 240b and 240d include both non-volatile portions and volatile portions … The backup power supply 210 can be used to perform backups, for example, in response to a power loss condition. For example, the CPU 220 may receive a power loss signal 250 indicating a power loss. Upon loss of power to the system 200, the backup power supply 210 may serve as a local finite power source to provide enough energy to continue to allow the CPU's memory controller 202 (including the DMA engine 212) to transfer the persistent data from the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, as described above … Method 300 includes moving, by the memory controller, the persistent data from the volatile portions of the plurality of memory modules to the non-volatile portions of the memory modules, in response to the interruption of primary power supply, using backup power provided by a backup power supply, at 330. For example, memory controller 202 can receive a power loss signal 250 indicating a power loss condition has occurred. In response to the power loss condition, memory controller can move the persistent data from any of the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, using backup power provided by the backup power supply 210 … (¶ 0021-0027)].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 4-7, 10-13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen et al. (US Patent Application Publication 2018/0024768, hereinafter Nguyen), and in view of Song et al. (US Patent Application Publication 2023/0350603, hereinafter Song).
As to claim 4, Nguyen teaches the storage cluster through the switch [as shown in figures 1-2; figure 2 shows a plurality of storage devices (240a-240e), where each storage device includes, as shown in figure 1, a volatile portion (114), and a non-volatile portion (124); as shown in figure 2, where the corresponding “switch” is a “memory bus” (230) providing an interface between the storage devices in the storage cluster], and an auxiliary power supply [The backup power supply 210 can be used to perform backups, for example, in response to a power loss condition. For example, the CPU 220 may receive a power loss signal 250 indicating a power loss. Upon loss of power to the system 200, the backup power supply 210 may serve as a local finite power source to provide enough energy to continue to allow the CPU's memory controller 202 (including the DMA engine 212) to transfer the persistent data from the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, as described above. Thus, the backup power supply 210 may provide enough energy to power at least the memory controller 202 (and the DMA engine 212), the memory bus 230, and the memory modules 240. Additional modules (not specifically shown) within the CPU 220 may also be powered as needed. Backup power supply 210 can be an energy component to convert stored energy to electrical energy to deliver power to components described above. Examples of backup power supply 210 can include, but are not limited to, a rechargeable battery, a capacitor (e.g., supercapacitor, ultracapacitor, etc.), a flywheel, and the like … (¶ 0022-0023)].
Regarding claim 4, Nguyen does not expressively teach a host connected to the storage cluster through the switch.
However, a host connected to the storage cluster through the switch is well known and a common practice in the art.
For example, Song specifically teaches a host connected to the storage cluster through the switch [host as shown in figures 1-2 and 5; FIG. 2 is a block diagram of a memory system 200 with an NVM module 202 with an IME circuit 204 with two encryption functions according to at least one embodiment … The memory system 200 is similar to the memory system 100 as noted by similar reference numbers, except the memory expansion device 208 can encrypt the unencrypted data 201, received from a host 212, using the IME circuit 104 to obtain encrypted data 203 before storing the encrypted data 203 in DRAM 214, or pass the unencrypted data 201 to the memory controller 210 as-is for storing unencrypted data 205 in DRAM 214 … (¶ 0019); FIG. 5 is a block diagram of an integrated circuit 500 with a memory controller 510, an encryption circuit 504, and a management processor 505 according to at least one embodiment … The integrated circuit 500 includes a first interface 502 coupled to the one or more host systems, a second interface 508 coupled to one or more volatile memory devices (not illustrated in FIG. 5), and a third interface 512 coupled to one or more non-volatile memory devices (not illustrated in FIG. 5). The one or more volatile memory devices can be DRAM devices. The integrated circuit 500 can be part of a single-host memory expansion integrated circuit, a multi-host memory pooling integrated circuit coupled to multiple host systems over multiple cache-coherent interconnects, or the like (¶ 0038)], a host processor configured to communicate with the first storage controller [as shown in figure 2, where there is a host (212), and a memory controller (210), which is the corresponding “first storage controller”]; a baseboard management controller (BMC) [as shown in figure 2, the management processor (206)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of claimed invention to have a host connected to the storage cluster through the switch, as specifically demonstrated by Song, and to incorporate it into the existing scheme disclosed by Nguyen, in order to support a host system, which is well known and a common practice in the art.
As to claim 5, Nguyen in view of Song teaches The computing system of claim 4, wherein the first storage device further includes a microcontroller that communicates with the BMC [Song – as shown in figure 2, where the memory controller (210) communicates with the BMC/management processor (206)], and wherein, the auxiliary power supply is configured to, based on the power not being supplied at the first storage device, supply auxiliary power to the microcontroller [Nguyen -- The backup power supply 210 can be used to perform backups, for example, in response to a power loss condition. For example, the CPU 220 may receive a power loss signal 250 indicating a power loss. Upon loss of power to the system 200, the backup power supply 210 may serve as a local finite power source to provide enough energy to continue to allow the CPU's memory controller 202 (including the DMA engine 212) to transfer the persistent data from the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, as described above. Thus, the backup power supply 210 may provide enough energy to power at least the memory controller 202 (and the DMA engine 212), the memory bus 230, and the memory modules 240. Additional modules (not specifically shown) within the CPU 220 may also be powered as needed. Backup power supply 210 can be an energy component to convert stored energy to electrical energy to deliver power to components described above. Examples of backup power supply 210 can include, but are not limited to, a rechargeable battery, a capacitor (e.g., supercapacitor, ultracapacitor, etc.), a flywheel, and the like … (¶ 0022-0023); Song -- Technologies for securing dynamic random access memory contents to nonvolatile memory in a persistent memory module are described. One persistent memory module includes an inline memory encryption (IME) circuit that receives a data stream from a host, encrypts the data stream into encrypted data, and stores the encrypted data in DRAM. A management processor transfers the encrypted data from the DRAM to persistent storage memory responsive to a signal associated with a power-loss or power-down event (abstract)].
As to claim 6, Nguyen in view of Song teaches The computing system of claim 5, wherein the BMC is configured to, based on the power not being supplied at the first storage device, communicate with the microcontroller to monitor a status of the first storage device [Nguyen -- The backup power supply 210 can be used to perform backups, for example, in response to a power loss condition. For example, the CPU 220 may receive a power loss signal 250 indicating a power loss. Upon loss of power to the system 200, the backup power supply 210 may serve as a local finite power source to provide enough energy to continue to allow the CPU's memory controller 202 (including the DMA engine 212) to transfer the persistent data from the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, as described above. Thus, the backup power supply 210 may provide enough energy to power at least the memory controller 202 (and the DMA engine 212), the memory bus 230, and the memory modules 240. Additional modules (not specifically shown) within the CPU 220 may also be powered as needed. Backup power supply 210 can be an energy component to convert stored energy to electrical energy to deliver power to components described above. Examples of backup power supply 210 can include, but are not limited to, a rechargeable battery, a capacitor (e.g., supercapacitor, ultracapacitor, etc.), a flywheel, and the like … (¶ 0022-0023); Song -- Technologies for securing dynamic random access memory contents to nonvolatile memory in a persistent memory module are described. One persistent memory module includes an inline memory encryption (IME) circuit that receives a data stream from a host, encrypts the data stream into encrypted data, and stores the encrypted data in DRAM. A management processor transfers the encrypted data from the DRAM to persistent storage memory responsive to a signal associated with a power-loss or power-down event (abstract)].
As to claim 7, Nguyen in view of Song teaches The computing system of claim 5, wherein the first storage controller is configured to, based on the microcontroller being supplied with the auxiliary power from the auxiliary power supply, provide the first data to the second storage device through the switch [Nguyen -- The backup power supply 210 can be used to perform backups, for example, in response to a power loss condition. For example, the CPU 220 may receive a power loss signal 250 indicating a power loss. Upon loss of power to the system 200, the backup power supply 210 may serve as a local finite power source to provide enough energy to continue to allow the CPU's memory controller 202 (including the DMA engine 212) to transfer the persistent data from the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, as described above. Thus, the backup power supply 210 may provide enough energy to power at least the memory controller 202 (and the DMA engine 212), the memory bus 230, and the memory modules 240. Additional modules (not specifically shown) within the CPU 220 may also be powered as needed. Backup power supply 210 can be an energy component to convert stored energy to electrical energy to deliver power to components described above. Examples of backup power supply 210 can include, but are not limited to, a rechargeable battery, a capacitor (e.g., supercapacitor, ultracapacitor, etc.), a flywheel, and the like … (¶ 0022-0023); Memory controller 102 can transfer the persistent data 134 from the volatile portion 114 of the memory module 104 to the non-volatile portion 124 of the memory module 104, in response to the power loss condition … Although backed up persistent data 144 is shown as a single block of data, examples are not so limiting. Backed up persistent data 144 may be spread as multiple blocks throughout multiple non-volatile portions 124 of the memory module 104 … (¶ 0018-0019); In the example of FIG. 2, the memory controller can partition a subset of the memory modules 240 into non-volatile portions and volatile portions … Accordingly, memory modules 240b and 240d include both non-volatile portions and volatile portions … The backup power supply 210 can be used to perform backups, for example, in response to a power loss condition. For example, the CPU 220 may receive a power loss signal 250 indicating a power loss. Upon loss of power to the system 200, the backup power supply 210 may serve as a local finite power source to provide enough energy to continue to allow the CPU's memory controller 202 (including the DMA engine 212) to transfer the persistent data from the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, as described above … Method 300 includes moving, by the memory controller, the persistent data from the volatile portions of the plurality of memory modules to the non-volatile portions of the memory modules, in response to the interruption of primary power supply, using backup power provided by a backup power supply, at 330. For example, memory controller 202 can receive a power loss signal 250 indicating a power loss condition has occurred. In response to the power loss condition, memory controller can move the persistent data from any of the volatile portions of the memory modules 240 to the non-volatile portions of the memory modules 240, using backup power provided by the backup power supply 210 … (¶ 0021-0027);
Song -- Technologies for securing dynamic random access memory contents to nonvolatile memory in a persistent memory module are described. One persistent memory module includes an inline memory encryption (IME) circuit that receives a data stream from a host, encrypts the data stream into encrypted data, and stores the encrypted data in DRAM. A management processor transfers the encrypted data from the DRAM to persistent storage memory responsive to a signal associated with a power-loss or power-down event (abstract)].
As to claim 10, Nguyen in view of Song teaches The computing system of wherein the interface is a Compute Express Link (CXL) interface, wherein the computing system further comprises a normal storage cluster including one or more normal storage device, and wherein the normal storage devices in the normal storage cluster are connected to an interface different from the CXL interface [Song –CXL interface as shown in figure 2, 220 and 222; Aspects of the present disclosure and embodiments can be used in a memory module that supports a remote memory protocol, such as Compute Express Link (CXL) protocol … (¶ 0013-0014);
As to claim 11, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
In addition, Nguyen in view of Song teaches a host [Song -- as shown in figures 1-2, and 5]; a memory device that includes a memory controller [Nguyen – memory controller, figure 1, 102; figure 2, 202; Song – memory controller, figure 1, 110]; wherein the first storage controller is configured to transmit a request corresponding to the first data to the memory controller through the switch, based on power not being supplied at the first storage device [Nguyen – as shown in figures 1-2; figure 2 shows a plurality of storage devices (240a-240e), where each storage device includes, as shown in figure 1, a volatile portion (114), and a non-volatile portion (124); as shown in figure 2, where the corresponding “switch” is a “memory bus” (230) providing an interface between the storage devices in the storage cluster; Example implementations relate to partitioning memory modules into volatile and non-volatile portions. For example, a system includes a memory controller to partition a memory module into a non-volatile portion and a volatile portion and to identify persistent data to be backed up during a power loss condition. The memory controller is further to transfer the persistent data from the volatile portion of the memory module to the non-volatile portion of the memory module, in response to the power loss condition (abstract)].
Regarding claim 11, Nguyen does not expressively teach a host connected to the storage cluster through the switch.
However, a host connected to the storage cluster through the switch is well known and a common practice in the art.
For example, Song specifically teaches a host connected to the storage cluster through the switch [host as shown in figures 1-2 and 5; FIG. 2 is a block diagram of a memory system 200 with an NVM module 202 with an IME circuit 204 with two encryption functions according to at least one embodiment … The memory system 200 is similar to the memory system 100 as noted by similar reference numbers, except the memory expansion device 208 can encrypt the unencrypted data 201, received from a host 212, using the IME circuit 104 to obtain encrypted data 203 before storing the encrypted data 203 in DRAM 214, or pass the unencrypted data 201 to the memory controller 210 as-is for storing unencrypted data 205 in DRAM 214 … (¶ 0019); FIG. 5 is a block diagram of an integrated circuit 500 with a memory controller 510, an encryption circuit 504, and a management processor 505 according to at least one embodiment … The integrated circuit 500 includes a first interface 502 coupled to the one or more host systems, a second interface 508 coupled to one or more volatile memory devices (not illustrated in FIG. 5), and a third interface 512 coupled to one or more non-volatile memory devices (not illustrated in FIG. 5). The one or more volatile memory devices can be DRAM devices. The integrated circuit 500 can be part of a single-host memory expansion integrated circuit, a multi-host memory pooling integrated circuit coupled to multiple host systems over multiple cache-coherent interconnects, or the like (¶ 0038)], a host processor configured to communicate with the first storage controller [as shown in figure 2, where there is a host (212), and a memory controller (210), which is the corresponding “first storage controller”]; a baseboard management controller (BMC) [as shown in figure 2, the management processor (206)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of claimed invention to have a host connected to the storage cluster through the switch, as specifically demonstrated by Song, and to incorporate it into the existing scheme disclosed by Nguyen, in order to support a host system, which is well known and a common practice in the art.
As to claim 12, Nguyen in view of Song teaches The computing system of wherein the memory controller is configured to generate information indicative of transmitting the first data to the second storage device, based on telemetry information of storage devices included in the storage cluster, and wherein the memory controller is configured to periodically update the telemetry information from the storage devices included in the storage cluster through the switch [Nguyen -- Memory controller 102 can identify persistent data to be backed up during a power loss condition or an interruption of primary power supply. Memory controller 102 can use metadata information such as characteristics, address, location, etc. to identify persistent data 134 to be backed up … In alternate examples, the memory controller 102 may periodically check for any updates to what data is to be considered persistent, and its corresponding locations (¶ 0016)].
As to claim 13, Nguyen in view of Song teaches The computing system of claim 12, wherein the telemetry information includes at least one of an execution status, a capacity, an input/output (I/O) bandwidth, a storage processor usage, or a data buffer usage of each of the storage devices included in the storage cluster [Nguyen -- Memory controller 102 can identify persistent data to be backed up during a power loss condition or an interruption of primary power supply. Memory controller 102 can use metadata information such as characteristics, address, location, etc. to identify persistent data 134 to be backed up … In alternate examples, the memory controller 102 may periodically check for any updates to what data is to be considered persistent, and its corresponding locations (¶ 0016); The system of claim 2, wherein identification of the persistent data is based in part on a capacity of the backup power supply to successfully provide backup power to enable the transfer of the persistent data (claim 4)].
As to claim 15, it recites substantially the same limitations as in claim 2, and is rejected for the same reasons set forth in the analysis of claim 2. Refer to “As to claim 2” presented earlier in this Office Action for details.
As to claim 16, it recites substantially the same limitations as in claim 11, and is rejected for the same reasons set forth in the analysis of claim 11. Refer to “As to claim 11” presented earlier in this Office Action for details.
As to claim 17, Nguyen in view of Song teaches The method for operating the computing system of The method for operating the computing system of wherein the first storage device includes: a first non-volatile memory configured to be controlled by the first storage controller [Nguyen -- as shown in figures 1-2; figure 2 shows a plurality of storage devices (240a-240e), where each storage device includes, as shown in figure 1, a volatile portion (114), and a non-volatile portion (124)]; and a first volatile memory configured to store the first data [Nguyen -- as shown in figures 1-2; figure 2 shows a plurality of storage devices (240a-240e), where each storage device includes, as shown in figure 1, a volatile portion (114), and a non-volatile portion (124)], wherein the first volatile memory includes a first memory region configured to store the first data, and a second memory region configured to store second data different from the first data [Nguyen -- as shown in figures 1-2; figure 2 shows a plurality of storage devices (240a-240e), where each storage device includes, as shown in figure 1, a volatile portion with a plurality of regions (114a-114d)].
As to claim 18, it recites substantially the same limitations as in claim 2, and is rejected for the same reasons set forth in the analysis of claim 2. Refer to “As to claim 2” presented earlier in this Office Action for details.
As to claim 19, it recites substantially the same limitations as in claim 4, and is rejected for the same reasons set forth in the analysis of claim 4. Refer to “As to claim 4” presented earlier in this Office Action for details.
As to claim 20, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 7. Refer to “As to claim 7” presented earlier in this Office Action for details.
6. Claims 3, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Song, and further in view of Khmelnistky et al. (US Patent Application Publication 2013/0073897, hereinafter Khmelnistky).
Regarding claim 3, Nguyen in view of Song does not teach the second memory region is configured to store mapping data of the user data.
However, Khmelnistky specifically teaches storing mapping data of the user data in a volatile memory [A NVM can include multiple index pages to provide mappings between logical addresses and physical addresses. In some cases, mapping information corresponding to the most recently written user data is stored in the volatile memory of the device in order to provide faster readout. Periodically, this mapping information can be flushed out from the volatile memory to the index pages of the NVM to provide for longer-term storage of the information (¶ 0002)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of claimed invention to store mapping data of the user data in a volatile memory, as specifically demonstrated by Khmelnistky, and to incorporate it into the existing scheme disclosed by Nguyen in view of Song because Khmelnistky teaches doing so provides fast readout of the mapping information [A NVM can include multiple index pages to provide mappings between logical addresses and physical addresses. In some cases, mapping information corresponding to the most recently written user data is stored in the volatile memory of the device in order to provide faster readout. Periodically, this mapping information can be flushed out from the volatile memory to the index pages of the NVM to provide for longer-term storage of the information (¶ 0002)].
As to claim 14, it recites substantially the same limitations as in claim 3, and is rejected for the same reasons set forth in the analysis of claim 3. Refer to “As to claim 3” presented earlier in this Office Action for details.
Conclusion
7. Claims 1-20 are rejected as explained above.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG JEN TSAI whose telephone number is 571-272-4244. The examiner can normally be reached on Monday-Friday, 9-6.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on 571-272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG JEN TSAI/Primary Examiner, Art Unit 2139
January 28, 2026