CTNF 18/974,396 CTNF 89549 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims Claims 1-19 are previously or currently cancelled. Claims 21-39 are pending, of which all pending claims are rejected. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/ process/file/efs/guidance/eTD-info-I.jsp. . Claims 20-39 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-19 U. S. Patent No. 12,164,371 B2. Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application and the patent both claimed providing protection against data corruption in a link. The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as in the following table (note that only exemplary independent claims are compared for illustration purposes, underlining is used to indicate conflicting limitations). Instant application US Patent # 12,164,371 20. An apparatus comprising: interface circuitry to receive data from multiple interconnect protocols; a multi-protocol multiplexer coupled to the interface circuitry, configured to direct data to physical layer circuitry; physical layer circuitry coupled to the multiplexer, configured to transmit data on a link; the apparatus is configurable to: aggregate a plurality of flits, each comprising a header and slots, into aggregated data of a message authentication code (MAC) epoch; generate a plaintext cyclic redundancy checksum (pCRC) based on the aggregated data; encrypt the aggregated data and the pCRC; compute a MAC using header information of the plurality of flits and encrypted data; transmit the header information, encrypted aggregated data, and the MAC on the link. 1. An apparatus comprising: link layer circuitry to receive data comprising at least one of first information of a first interconnect protocol or second information of a second interconnect protocol; a multi-protocol multiplexer coupled to the link layer circuitry, the multi-protocol multiplexer to receive the data from the link layer circuitry and direct the data to physical layer circuitry; and the physical layer circuitry coupled to the multi-protocol multiplexer, wherein the physical layer circuitry is to receive the data from the multi-protocol multiplexer and transmit at least one packet on a link, wherein the apparatus is configurable to: aggregate a plurality of flits of the data into aggregated data of a message authentication code (MAC) epoch, each of the plurality of flits comprising a header and a plurality of slots; generate a plaintext cyclic redundancy checksum (pCRC) based on the aggregated data of the MAC epoch ; encrypt plaintext comprising the aggregated data and the pCRC into encrypted plaintext, the encrypted plaintext comprising encrypted aggregated data and an encrypted pCRC; compute a MAC using header information of the plurality of flits and the encrypted plaintext; and transmit the header information, the encrypted aggregated data, and the MAC , and not the encrypted pCRC via the physical layer circuitry on the link. 33. A method comprising: aggregating a plurality of flits, each comprising a header and slots, into aggregated data of a message authentication code (MAC) epoch; generating a plaintext cyclic redundancy checksum (pCRC) based on the aggregated data; encrypting the aggregated data and the pCRC; computing a MAC using header information of the plurality of flits and encrypted data; transmitting the header information, encrypted aggregated data, and the MAC on a link. 14. A method comprising: aggregating, in integrity and data encryption (IDE) circuitry of an interface, a plurality of flits of data into aggregated data of a message authentication code (MAC) epoch, each of the plurality of flits comprising a header and a plurality of slots; generating, in the IDE circuitry, a plaintext cyclic redundancy checksum (pCRC) based at least in part on the aggregated data; encrypting, in the IDE circuitry, plaintext comprising the aggregated data and the pCRC into encrypted plaintext, the encrypted plaintext comprising encrypted aggregated data and an encrypted pCRC; computing, in the IDE circuitry, a MAC using header information of the plurality of flits and the encrypted plaintext; and transmitting, via a physical layer circuit, the header information, the encrypted aggregated data, and the MAC, and not the encrypted pCRC on a link. 36. A system comprising: a processor with interface circuitry, including: interface circuitry to receive data from multiple interconnect protocols; a multi-protocol multiplexer coupled to the interface circuitry, configured to direct data to physical layer circuitry; physical layer circuitry coupled to the multiplexer, configured to transmit data on a link; the interface circuitry is configurable to: aggregate a plurality of flits, each comprising a header and slots, into aggregated data of a message authentication code (MAC) epoch; generate a plaintext cyclic redundancy checksum (pCRC) based on the aggregated data; encrypt the aggregated data and the pCRC; compute a MAC using header information of the plurality of flits and encrypted data; and transmit the header information, encrypted aggregated data, and the MAC to an external device. 17. A system comprising: a host processor having at least one core and an interface circuit, the interface circuit comprising: link layer circuitry to receive data comprising at least one of first information of a first interconnect protocol or second information of a second interconnect protocol; a multi-protocol multiplexer coupled to the link layer circuitry , the multi-protocol multiplexer to receive the data from the link layer circuitry and direct the data to physical layer circuitry ; and the physical layer circuitry coupled to the multi-protocol multiplexer, wherein the physical layer circuitry is to receive the data from the link layer circuitry and transmit at least one packet on a link, wherein the interface circuit is configurable to: aggregate a plurality of flits of the data into aggregated data of a message authentication code (MAC) epoch, each of the plurality of flits comprising a header and a plurality of slots; generate a plaintext cyclic redundancy checksum (pCRC) based at least in part on the aggregated data; encrypt plaintext comprising the aggregated data and the pCRC into encrypted plaintext, the encrypted plaintext comprising encrypted aggregated data and an encrypted pCRC; compute a MAC using header information of the plurality of flits and the encrypted plaintext; and transmit the header information, the encrypted aggregated data, and the MAC , and not the encrypted pCRC to an accelerator; and the accelerator coupled to the host processor. The non-underlined limitations are merely differing in form that does not change the scope of the invention. Therefore, it is obvious that the ordinary skilled artisan would have been motivated to modify the claims of the instant application by omitting or adding the non-underlined limitation. Omitting or adding the non-underlined elements would not interface with the functionality of the steps claimed of the patent and would perform the same function (see In re Karlson, 136 USPQ 184 (CCPA 1963). Dependent claims 21-32, 34-35 and 37-39 are also rejected under obviousness type double patenting over claims 1-19 of the patent for having obvious variations. Allowable Subject Matter Claims 21-39 would be allowable if the pending obviousness double patenting rejection and all remaining pending objections and rejections (if any) are overcome. Conclusion When amending the claims, Applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to ENAMUL MD KABIR whose telephone number is (571)270-7256. The examiner can normally be reached on 10:00-6:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached on 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ENAMUL M KABIR/ Examiner, Art Unit 2112 /ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112 Application/Control Number: 18/974,396 Page 2 Art Unit: 2112 Application/Control Number: 18/974,396 Page 3 Art Unit: 2112 Application/Control Number: 18/974,396 Page 4 Art Unit: 2112 Application/Control Number: 18/974,396 Page 5 Art Unit: 2112 Application/Control Number: 18/974,396 Page 6 Art Unit: 2112 Application/Control Number: 18/974,396 Page 7 Art Unit: 2112 Application/Control Number: 18/974,396 Page 8 Art Unit: 2112 Application/Control Number: 18/974,396 Page 9 Art Unit: 2112 Application/Control Number: 18/974,396 Page 10 Art Unit: 2112 Application/Control Number: 18/974,396 Page 11 Art Unit: 2112 Application/Control Number: 18/974,396 Page 12 Art Unit: 2112 Application/Control Number: 18/974,396 Page 13 Art Unit: 2112 Application/Control Number: 18/974,396 Page 14 Art Unit: 2112
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