DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miscuglio (pub # US 20230207008 A1) in view of Syed (pub #US 20230176606 A1, hereinafter Syed).
Regarding claim 1, Miscuglio discloses a data processing apparatus comprising (photonic memory system shown in figure 1, details shown in subsequent figures, such as figure 8): a first processor node comprising: a first processor circuit (controller 50, figure 8); a first memory switch in electrical communication with the first processor circuit (switch 684, figure 8); and a first on-chip memory in electrical communication with the first memory switch (PCM cells 620); a first photonic transceiver (first waveguide 610, paragraph 109) in electrical communication with the first memory switch in parallel with the first processor circuit and in photonic communication with a photonic link (data and write line, figure 8, paragraph 109);
Miscuglio discloses the system may interface with other photonic devices including multiple devices systems such as vector multipliers (paragraph 30), but does not disclose explicitly a second processing node with similar circuitry as the first processor node. However, Syed discloses using multiple scalable cores with photonic transmission interfaces to execute parallel instructions (paragraph 46). Furthermore, teachings of Miscuglio and Syed are from the same field of optical memory and processing systems.
Therefore, it would have been obvious before the effective filing date of the invention for a person of ordinary skill in the art to combine teachings of Miscuglio with Syed by using multiple processor cores discloses by Miscuglio in the system of Miscuglio for the benefit of parallel computation (paragraph 46, Syed).
Regarding claim 2, the above combination discloses the data processing apparatus of claim 1, wherein the photonic link is a bidirectional photonic link (figure 8, read/write beams are delivered through the same waveguide, input and output, paragraph 29, Miscuglio).
Regarding claim 3, the above combination discloses the data processing apparatus of claim 1, wherein the photonic link comprises an optical waveguide (waveguide for optical link, paragraph 29, Miscuglio)
Regarding claim 4, the above combination discloses the data processing apparatus of claim 1, further comprising: a first electronic integrated circuit comprising the first processor node (logic circuitry uses electrical signals, paragraph 109); a second electronic integrated circuit comprising the second processor node; a first photonic integrated circuit comprising the first photonic transceiver (optical assembly 600, figure 8, paragraph 108); and a second photonic integrated circuit comprising the second photonic transceiver (note the second circuits would be obvious in view of Syed’s teachings, using the same rationale as in rejection of claim 1).
Regarding claim 5, the above combination discloses the data processing apparatus of claim 4, wherein the photonic link is optically coupled to the first photonic integrated circuit and the second photonic integrated circuit (circuits are interconnected through a fabric, paragraph 46, Syed).
Regarding claim 6, the above combination discloses the data processing apparatus of claim 1, further comprising a non-transitory computer storage medium encoded with a computer program (software, paragraph 97), the computer program comprising instructions that when executed by data processing apparatus cause the data processing apparatus to perform operations comprising: receiving, by the first photonic transceiver, data from the first on-chip memory; transmitting, by the first photonic transceiver over the photonic link, the data to the second photonic transceiver; receiving, by the second photonic transceiver from the photonic link, the data; and storing, the data in the second on-chip memory (the reading/writing of the PCM memory cells can be performed by software installed on a memory controller 50, paragraph 97, Miscuglio).
Regarding claim 7, the above combination discloses the data processing apparatus of claim 1, wherein at least one of the first on-chip memory and the second on-chip memory comprise static random-access memory (SRAM) circuitry (SRAM, or any other RAM known in the art, Syed, paragraph 45).
Regarding claim 8, the above combination discloses the data processing apparatus of claim 1, wherein the first on-chip memory and the second on-chip memory are level 1 (L1) processor cache memories (examiner takes official notice that L1 cache for processors were well-known in the art, and would have been an obvious part of the processor systems for the benefit of providing fast on-chip memory to the processors).
Regarding claims 9-21, examiner notes that these claims comprise of similar limitations as those of claims 1-8 above. The same grounds of rejection are applied.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT C SUN whose telephone number is (571)272-2675. The examiner can normally be reached Monday - Friday, 12-8:30 PM.
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/SCOTT C SUN/Primary Examiner, Art Unit 2181