DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gola et al. (USPN 5,528,184).
With respect to claim 13, a method of operating a power-on reset (POR) circuit (method of operating Fig. 1), the method comprising:
generating, via a resistor, a current based at least in part on a power supply voltage that exceeds a threshold voltage defined by two transistors that are connected in series (current through the branch consisting of M1, M2, and R1. The current is generated via R1 and is based on the power supply voltage VDD that exceeds the threshold voltage of the two diode connected transistors of M1 and M2);
mirroring the generated current across one or more current mirrors (M1 with M5 mirrors the generated current to node A); and
tripping an inverter based at least in part on the generated current and the power supply voltage (the inverter I is tripped based on the generated current via the mirroring of M1 to M5 to node A and the gate voltage of M4 being controlled by Vx which is power supply dependent, wherein M4 also trips the inverter by pulling A load).
With respect to claim 14, the method of claim 13, wherein tripping the inverter includes:
as the power supply voltage is rising, tripping the inverter when a voltage at an input of the inverter reaches a trigger voltage of the inverter (as the power supply increases M4 becomes active such that the inverter is triggered, i.e., reaches a threshold, such that the inverter generates a high voltage level responsive to M4 pulling A low, i.e., reaches the threshold of the inverter) ; or as the power supply voltage is falling, tripping the inverter when the voltage at the input of the inverter drops to the trigger voltage of the inverter (the above “or” clause is stated in the alternative and not explicitly required).
Claim(s) 9-10 and 13-14 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Coffman et al. (USPN 5,396,115).
With respect to claim 9, a power-on reset (POR) circuit (Fig. 2), comprising:
a bias generation stage (CBC with VRC and CSC) configured to generate, via a resistor (MP04 is a PMOS resistor, since it is connected as a PMOS resistor having a gate shorted to ground and providing a resistance across its channel), a bias current (current through the VRC branch) based at least in part on a power supply voltage (Vcc) that exceeds a sum of two threshold voltages that each correspond to one of two transistors of the bias generation stage (threshold drop of diode connected transistor MP03 and threshold drop of diode connected MN04. For the branch to be active, i.e., conducting a current Vcc provided by MP02 must be larger than the threshold of MP03 and MN04);
a trip point generation stage coupled to the bias generation stage (RDC) and configured to generate a voltage at a node (voltage on the N06 node) based at least in part on the bias current (due the current mirroring of MP03 with MP08, Mn04 with MN05 and MN05 with MN08); and
an output stage coupled to the trip point generation stage (PSC) and configured to generate a power-on reset bar signal (OUT inverted version of the N06 voltage) based at least in part on the voltage at the node (N06 voltage controlling the transistors of PSC).
With respect claim 10, the POR circuit of claim 9, wherein the bias generation stage comprises: a first current mirror configured to generate the bias current (MP01 with MP02, MP02 generating the current through VRC); and
a second current mirror coupled to the first current mirror (at least one of MN04 with MN06 and MN05 with MN08) and configured to mirror the bias current to the trip point generation stage (current mirrored by the above mirroring circuit to the N06 node via MN08).
With respect to claim 13, Coffman et al. discloses, in Fig. 2 a method of operating a power-on reset (POR) circuit, the method comprising:
generating, via a resistor (MP04 is a PMOS resistor, since it is connected as a PMOS resistor having a gate shorted to ground and providing a resistance across its channel), a current based (current through the VRC branch) at least in part on a power supply voltage (the current is generated, at least in part based on Vcc) that exceeds a threshold voltage defined by two transistors that are connected in series (threshold drop of diode connected transistor MP03 and threshold drop of diode connected MN04. For the branch to be active, i.e., conducting a current Vcc provided by MP02 must be larger than the threshold of MP03 and MN04);
mirroring the generated current across one or more current mirrors (current mirrored by MP03 with MP08 and current mirrored through MN04 with MN06); and
tripping an inverter based at least in part on the generated current and the power supply voltage (MN08 and MP08 trips the pulse stretching inverter of MP09 with N08 according to the voltage at N06 provided by MP08 and MN08 under control of the above current mirrors).
With respect to claim 14, the method of claim 13, wherein tripping the inverter includes: as the power supply voltage is rising, tripping the inverter when a voltage at an input of the inverter reaches a trigger voltage of the inverter; or as the power supply voltage is falling, tripping the inverter when the voltage at the input of the inverter drops to the trigger voltage of the inverter (the inverter is tripped according to the rise and fall of the N06 voltage which is responsive to the rise and/or fall of the power supply voltage Vcc under the control of CBC).
With respect to claim 20, the method of claim 13, wherein mirroring the generated current includes (a) mirroring the generated current across a first current mirror (MN04 with MN06 mirroring the current of the branch of VRC) to produce an intermediate current (current at the drain of MN06) and (b) mirroring the intermediate current across a second current mirror different from the first current mirror to produce mirrored current (the intermediate current mirrored from MN5 and MN08 to the N06 node), and wherein tripping the inverter based at least in part on the generated current includes tripping the inverter based at least in part on the mirrored current (MN08 controls, at least in part, the tipping of MP09 with N08).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-6, 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gola et al. (USPN 5,528,184) in view of Ouyang et al. (USPN 4,717,840).
With respect to claim 1, Gola et al. discloses, in Fig. 1, a power-on reset (POR) circuit (Fig. 1), comprising:
at least one current mirror (M1 with M5);
a diode-connected P-channel Metal-Oxide-Semiconductor (PMOS) transistor (M2) with its source coupled to the at least one current mirror (M1 of the current mirror) and its drain coupled to a resistor (R1) that is coupled between the diode-connected PMOS transistor (drain of M2) and ground (GND); and
an inverter having an input coupled to the at least one current mirror (I generating OUT having an input connected to the drain of M5), wherein:
a voltage at the input of the inverter is based at least in part on (i) a current produced by the at least one current mirror (drain current of M5 provided to A), the diode-connected PMOS transistor, and the resistor (M2 and R1, set in part, input current of current mirror/M1 and thus the output/voltage at A) and (ii) a power supply voltage (the voltage at A is controlled by M4 responsive to Vx, wherein Vx is dependent upon the power supply voltage of VDD, see Col. 1 line 55 to Col. 2 line 9).
Gola et al. fails to disclose “the POR circuit is configured to generate a power-on reset bar signal based at least in part on an output of the inverter”.
However, it is old and well-known to connect an additional inverter to the power-on reset signal output for the purpose of producing a complementary power on reset signal (i.e., power on reset bar signal). This is further evidenced in Fig. 1 of Ouyang et al., see inverter 14 of Fig. which provides a complementary power on reset signal (pur bar) of the power on reset signal (pur) “when desired”, see Col. 2 line 66 to Col. 3 line 2.
It would have been obvious to add an additional inverter cascaded to the OUT of Gola et al., such as the inverter 14 of Ouyang et al., for the purpose of generating a complementary power on reset signal when such a signal is desired. One would have been motivated to do so according to the logic level required by the circuitry receiving the power on reset signal (e.g., if the circuit is active high instead of active low, or vice versa).
With respect to claim 2, the POR circuit of claim 1, wherein the at least one current mirror includes a PFET current mirror (M1 with M5 is a PFET current mirror).
With respect to claim 4, the POR circuit of claim 1, wherein:
the at least one current mirror includes a current mirror having a first transistor (M1) and a second transistor (M5);
the first transistor is a diode-connected transistor (M1 is diode connected) that is coupled between the power supply voltage (VDD at the source of M1) and ground (GND via M2 and R1); and
the POR circuit further comprises the diode-connected PMOS transistor (M2 is included within the POR circuit).
With respect to claim 5, the POR circuit of claim 1, wherein:
the at least one current mirror includes a current mirror having a first transistor (M1) and a second transistor (M2);
the first transistor is a diode-connected transistor (M1 is diode connected) that is coupled between the power supply voltage (VDD) and ground (GND via M2 and R1); and
the POR circuit further comprises the resistor that is coupled between the first transistor and ground (R1 is included with the POR circuit)
With respect to claim 6, Gola et al. fails to disclose “wherein the resistor includes a variable resistor”. However, it would have been obvious to construct the circuit such that R1 is a variable resistors, since it has been held the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954). One would have been motivated to do so to be able to fine tune to a desired value the resistance of R1 and thus the level/value of the trip point/Vx which is dependent upon the value of R1.
With respect to claim 9, a power-on reset (POR) circuit (Fig. 9), comprising:
a bias generation stage (M1, M2 and R1) configured to generate, via a resistor (R1), a bias current based at least in part on a power supply voltage (bias current through the M1, M2 and R1 branch based on VDD) that exceeds a sum of two threshold voltages that each correspond to one of two transistors of the bias generation stage (threshold drop of diode connected transistor M1 plus the voltage drop of diode connected transistor M2);
a trip point generation stage (M3, M4 and inverter I for generating OUT) coupled to the bias generation stage (M5 at A and to R1/M1 at Vx) and configured to generate a voltage at a node (voltage on node A generated, at least in part, based on the output of M4) based at least in part on the bias current (gate of M4 controlled by Vx which is controlled, at least in part, on the bias current in the branch. Thus, the signal at A connected to the drain of M4 is based on the current through the branch).
Gola et al. fails to disclose “an output stage coupled to the trip point generation stage and configured to generate a power-on reset bar signal based at least in part on the voltage at the node.”
However, it is old and well-known to connect an additional inverter to the power-on reset signal output for the purpose of producing a complementary power on reset signal (i.e., power on reset bar signal). This is further evidenced in Fig. 1 of Ouyang et al., see inverter 14 of Fig. which provides a complementary power on reset signal (pur bar) of the power on reset signal (pur) “when desired”, see Col. 2 line 66 to Col. 3 line 2.
It would have been obvious to add an additional inverter cascaded to the OUT of Gola et al., such as the inverter 14 of Ouyang et al., for the purpose of generating a complementary power on reset signal when such a signal is desired. One would have been motivated to do so according to the logic level required by the circuitry receiving the power on reset signal (e.g., if the circuit is active high instead of active low, or vice versa).
As combined above the power reset bar signal is based on the signal on node A of Gola.
With respect to claim 11, the POR circuit of claim 9, wherein the trip point generation stage comprises an inverter (inverter I that generates OUT), and wherein the voltage at the node is applied to an input of the inverter (voltage at A applied to the input of inverter I).
Claim(s) 8 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gola et al. (USPN 5,528,184) in view of Ouyang et al. (USPN 4,717,840) and in further view of Woods (USPN 6,529,285)
With respect to claim 8, the above combination of Gola et al. and Ouyang et al. fails to disclose that the output inverters are hysteresis/Schmitt-trigger inverting buffers. Thus, the above combination fails to disclose “a Schmitt-trigger buffer coupled to the output of the inverter and configured to provide hysteresis to the power-on reset bar signal.” However, it is old well-known to use inverters having hysteresis (i.e., Schmitt-trigger inverting buffers) for the output generating inverters of a power on reset circuit. Such inverters having hysteresis reduce false outputs due to noise/transients within the circuit due to the switching hysteresis of the buffers.
Such inverters having hysteresis (i.e., Schmitt-trigger inverting buffers) for the output generating inverters of a power on reset circuit is further evidenced in Fig. 1 of Woods (see 142 and 144).
It would have been obvious to replace the generic inverters of the combination of Gola et al. and Ouyang et al. with hysteresis inverters (i.e., Schmitt-trigger inverting buffers) of 142 and 144 of Woods for the purpose of reducing false outputs of the reset signals due to the switching hysteresis of the buffers.
With respect to claim 12, the above combination of Gola et al. and Ouyang et al. merely discloses generic inverters for providing the power on reset signals. The above combination fails to disclose, “wherein the output stage comprises a Schmitt trigger buffer, and wherein the Schmitt trigger buffer is configured to: assert the power-on reset bar signal when the power supply voltage rises above a first threshold; and de-assert the power-on reset bar signal when the power supply voltage falls below a second threshold that is lower than the first threshold”.
However, However, it is old well-known to use inverters having hysteresis (i.e., Schmitt-trigger inverting buffers) for the output generating inverters of a power on reset circuit. Such inverters having hysteresis reduce false outputs due to noise/transients within the circuit due to the switching hysteresis of the buffers. Additionally the “hysteresis” of such an inverter is providing by having a trip point (e.g., first output voltage generating trip point) that is above a first threshold (i.e., upper trip point of hysteresis) and having a second trip point (e.g., second output voltage generating trip point having a complementary output value to the first trip point) that is at a second threshold below the first. The first and second trip points provide for the hysteresis of the inverters.
Such inverters having hysteresis (i.e., Schmitt-trigger inverting buffers) for the output generating inverters of a power on reset circuit is further evidenced in Fig. 1 of Woods (see 142 and 144).
It would have been obvious to replace the generic inverters of the combination of Gola et al. and Ouyang et al. with hysteresis inverters (i.e., Schmitt-trigger inverting buffers) of 142 and 144 of Woods for the purpose of reducing false outputs of the reset signals due to the switching hysteresis of the buffers.
As combined above the hysteresis inverters will provide for the claimed first and second threshold for the assertion and/or de-assertion of the reset signals.
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gola et al. (USPN 5,528,184) in view of Woods (USPN 6,529,285).
With respect to claim 15, Gola et al. fails to disclose the tripping of the inverter including a hysteresis component. Thus, Gola et al. fails to disclose “asserting, based at least in part on the tripping of the inverter, a power-on reset bar signal after accounting for hysteresis.”
However, it is old well-known to use inverters having hysteresis for the output generating inverters of a power on reset circuit. Such inverters having hysteresis reduce false outputs due to noise/transients within the circuit due to the switching hysteresis of the buffers.
Such inverters having hysteresis for the output generating inverters of a power on reset circuit is further evidenced in Fig. 1 of Woods (see 142 and 144).
It would have been obvious to replace the generic inverter of Gola et al. with hysteresis inverter of at least one of 142 and 144 of Woods for the purpose of reducing false outputs of the reset signals due to the switching hysteresis of the buffers.
As combined above the hysteresis inverters will provide for the claimed first and second threshold for the assertion and/or de-assertion of the reset signals.
With respect to claim 16, Gola et al. fails to disclose the tripping of the inverter including a hysteresis component. Thus, Gola et al. fails to disclose “de-asserting, based at least in part on the tripping of the inverter, a power-on reset bar signal after accounting for hysteresis.”
However, it is old well-known to use inverters having hysteresis for the output generating inverters of a power on reset circuit. Such inverters having hysteresis reduce false outputs due to noise/transients within the circuit due to the switching hysteresis of the buffers.
Such inverters having hysteresis for the output generating inverters of a power on reset circuit is further evidenced in Fig. 1 of Woods (see 142 and 144).
It would have been obvious to replace the generic inverter of Gola et al. with hysteresis inverter of at least one of 142 and 144 of Woods for the purpose of reducing false outputs of the reset signals due to the switching hysteresis of the buffers.
As combined above the hysteresis inverters will provide for the claimed first and second threshold for the assertion and/or de-assertion of the reset signals.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gola et al. (USPN 5,528,184).
With respect to claim 17, Gola fails to provide an explicit value of the power supply voltage at which point Vx causes a tripping of the inverter. Thus, Gola et al. fails to disclose “wherein tripping the inverter as the power supply voltage is rising comprises tripping the inverter when the power supply voltage reaches approximately half of a full-scale power supply voltage”.
With respect to claim 18, Gola et al. fails to disclose the specific value of the current generated within the circuitry of Fig. 1. Thus Gola et al. fails to disclose “wherein generating the current comprises generating a current of approximately 100 nanoamperes”. However, it would have been obvious to size the devices of Fig. 1 such that the current is generated at a value of approximately 100 nanoamperes, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to reduce current consumption/generate a current at a desired/required level.
Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Coffman et al. (USPN 5,396,115) in view of Ouyang et al. (USPN 4,717,840).
With respect to claim 1, a power-on reset (POR) circuit (Fig. 2), comprising:
at least one current mirror (MP01 with MP02 and MP07 and/or MN04 with MN06, MN05 and MN08);
a diode-connected P-channel Metal-Oxide-Semiconductor (PMOS) transistor (MP03) with its source coupled to the at least one current mirror (source of MP03 connected to drain of MP02) and its drain coupled to a resistor (drain connected to MP04 which is a PMOS resistor due to the grounding of the gate of MP04) that is coupled between the diode-connected PMOS transistor and ground (ground via MN04); and
an inverter (PSC which is a pulse stretching inverter) having an input (gates of MP09 and N08) coupled to the at least one current mirror (at node N06 directly connected to MN08 and connected to MP07 via MP08), wherein:
a voltage at the input of the inverter is based at least in part on (i) a current produced by the at least one current mirror (based on the current mirroring provided by MP03 with MP08 and/or MN04, MN06, MN05 and MN08), the diode-connected PMOS transistor (MP03 sets the current mirroring and current through branch), and the resistor and (the resistor sets the current through the branch) (ii) a power supply voltage (responsive to the control of CBC).
Coffman et al. fails to disclose “the POR circuit is configured to generate a power-on reset bar signal based at least in part on an output of the inverter”
However, it is old and well-known to connect an additional inverter to the power-on reset signal output for the purpose of producing a complementary power on reset signal (i.e., power on reset bar signal). This is further evidenced in Fig. 1 of Ouyang et al., see inverter 14 of Fig. which provides a complementary power on reset signal (pur bar) of the power on reset signal (pur) “when desired”, see Col. 2 line 66 to Col. 3 line 2.
It would have been obvious to add an additional inverter cascaded to the OUT of Coffman et al., such as the inverter 14 of Ouyang et al., for the purpose of generating a complementary power on reset signal when such a signal is desired. One would have been motivated to do so according to the logic level required by the circuitry receiving the power on reset signal (e.g., if the circuit is active high instead of active low, or vice versa).
With respect to claim 2, the POR circuit of claim 1, wherein the at least one current mirror includes a PFET current mirror (MP01 with MP02 constitutes a PMOS current mirror).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Coffman et al. (USPN 5,396,115).
With respect to claim 18, Coffman et al. fails to disclose the specific value of the current generated within the circuitry of Fig. 2. Thus Coffman et al. fails to disclose “wherein generating the current comprises generating a current of approximately 100 nanoamperes”. However, it would have been obvious to size the devices of Fig. 2 such that the current is generated at a value of approximately 100 nanoamperes, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to reduce current consumption/generate a current at a desired/required level.
Allowable Subject Matter
Claim 4 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 4-18 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Cited Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Krasin (USPN 7,154,719) discloses that a PMOS transistor having its gate connected ground constitutes a PMOS resistor (i.e., is an art recognized equivalent to a resistor), see R of Fig. 1 and Col. 2 lines 40-42.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
Prosecution Insights