DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-15 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 01/08/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7, 9-11 and 15 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Studtmann (US 5216352 A).
Regarding claim 1, Studtmann teaches an arrangement (abstract, A solid state circuit interruption arrangement) comprising:
a semiconductor switch (i.e. solid state switch 10, fig.3);
a measuring circuit (e.g. circuit comprising current sensor 16, fig.3); and
a control device (e.g. driver 24, fig.3),
wherein the semiconductor switch comprises a load path input (e.g. point A, fig.3) and a load path output (i.e. point B, fig.3) for connection to a load path (e.g. path from source 11 to load 12, fig.3) and a switching signal input (e.g. input to 10 from 20, fig.3) for receiving a switching signal for opening or closing the semiconductor switch (column 3 lines 47-48, a driver circuit 24. the latter of which controls the switch 10), the load path input and the load path output are connected to each other in a closed state of the semiconductor switch and separated from each other in an open state of the semiconductor switch (column 3 lines 31-35, The control circuit 20 … periodically instructing the switch 10 to interrupt the current path),
wherein the measuring circuit comprises a load path input (e.g. input at current sensor 16, fig.3) with which the measuring circuit is connectable to the load path (e.g. 16 is connected to the path between 11 and 12, fig.3), a shunt connected in series downstream of the load path input (e.g. resistor R1, fig.5), a load path output connected in series downstream of the shunt (e.g. output from 20a and 20b, figs.3 and 5), which is routed to the load path input of the semiconductor switch (e.g. output of 20a and 20b is routed to 10 via 23 and 24, figs.3 and 5), a voltage tap for the voltage dropping across the shunt (e.g. tap at the output of R1 to 22a and 22b, figs.3 and 5) and an overload detector (i.e. long term control 20a, short term control 20b, figs.3 and 5) with an overload signal output connected in series downstream of the voltage tap (e.g. output of 23, fig.3), which is routed to the control device (e.g. signal from 23 is routed to driver 24, fig.3),
wherein the overload detector is set up to detect the presence of an overload on the load path and to output an overload signal to the control device via the overload signal output in an event of an overload (column 3 lines 37-48, control the switch 10 for long-term type overloads … operating the switch once overloads have exceeded a predetermined value),
wherein the control device is connected to the switching signal input of the semiconductor switch via a switching signal line (e.g. Line connecting 24 and 10, fig.3),
wherein the control device is configured to supply the semiconductor switch with a switching signal for opening the semiconductor switch via the switching signal line if the control device has received an overload signal from the overload detector via the overload signal output (columns 3-4 lines 66-6, The short-term control circuit 20b responds to the sensor 16 by instructing the switch 10 to open and close periodically so that the current supplied to the load is controlled between prescribed maximum and minimum current levels), and
wherein the control device is configured to supply the semiconductor switch with a switching signal for closing the semiconductor switch via the switching signal line after the overload signal has disappeared (columns 3-4 lines 66-6, The short-term control circuit 20b responds to the sensor 16 by instructing the switch 10 to open and close periodically so that the current supplied to the load is controlled between prescribed maximum and minimum current levels), provided that the overload has not amounted to more than a predetermined maximum overload (column 3 lines, 63-64, If the sensed current exceeds the predetermined value), and in a case where the overload has exceeded the predetermined maximum overload, to no longer generate a switching signal for closing the semiconductor switch even after the overload signal has disappeared (column 5 lines 25-29, If at the end of the time period the current has not decreased to a normal or acceptable value, then the transient is presumed to be due to a short circuit and the control circuit 20 turns off the switch 10 and latches it off).
Regarding claim 2, Studtmann teaches the arrangement according to claim 1, wherein the control device is designed to supply to the semiconductor switch with the switching signal for closing the semiconductor switch via the switching signal line at a time, which, after the time the overload has disappeared, is delayed by such a delay period that is a function of the overload and increases with it (column 3 lines 54-61, the long-term control circuit 20a would turn off the switch 10 to interrupt the current path after 60 seconds of a sensed overload which is twice the rated current, after 10 seconds of a sensed overload which is four times the rated current, and after 3 seconds of a sensed overload which is eight times the rated current, etc).
Regarding claim 3, Studtmann teaches the arrangement according to claim 2, wherein:
the overload detector has an integrator which is configured to integrate the current on the load path into a load (column 4 lines 22-26, The long-term control circuit 20a may also be implemented using a microcomputer, which integrates the square of the current passing through the switch 10) and, in the event that the load has reached a predetermined first overload threshold, to output an overload signal to the control device via the overload signal output until the load has fallen below a second overload threshold (column 4 lines 31-36, If the computed average of I.sup.2 finally exceeds the predetermined maximum, then the switch is opened at the zero crossing of the current of the next half cycle),
the control device is set up to measure the duration of receiving the overload signal (column 4 lines 29-31, The average is computed over enough half cycles to give the required time-current characteristic),
the control device is designed to generate a switching signal for closing the semiconductor switch provided that the duration of receiving the overload signal has not exceeded a predetermined maximum duration (columns 3-4 lines 66-6, The short-term control circuit 20b responds to the sensor 16 by instructing the switch 10 to open and close periodically so that the current supplied to the load is controlled between prescribed maximum and minimum current levels), and in a case where the duration of receiving the overload signal has exceeded the predetermined maximum duration, to no longer to generate a switching signal for closing the semiconductor switch (column 5 lines 25-29, If at the end of the time period the current has not decreased to a normal or acceptable value, then the transient is presumed to be due to a short circuit and the control circuit 20 turns off the switch 10 and latches it off), and
the control device is set up to supply the switching signal for closing the semiconductor switch to the semiconductor switch via the switching signal line at a time when, after the overload signal has disappeared, a delay period has elapsed which is a function of the duration of receiving the overload signal and increases with it (column 3 lines 54-61, the long-term control circuit 20a would turn off the switch 10 to interrupt the current path after 60 seconds of a sensed overload which is twice the rated current, after 10 seconds of a sensed overload which is four times the rated current, and after 3 seconds of a sensed overload which is eight times the rated current, etc).
Regarding claim 7, Studtmann teaches the arrangement according to claim 3, wherein a preamplifier with a signal rectifier is connected upstream of the integrator (e.g. Lag 20a2 and comparator 20a3, fig.5).
Regarding claim 9, Studutmann teaches the arrangement according to claim 1, wherein the control device has an FPGA or a microcontroller (column 5 lines 64-67, The control circuit 20 of FIG. 3 may be implemented by programming a microcomputer, such as an MC68HC11-type integrated circuit).
Regarding claim 10, the method is rejected for the same reasons as stated above for claim 1.
Regarding claim 11, the method is rejected for the same reasons as stated above for claim 2.
Regarding claim 15, Studtmann teaches the arrangement according to claim 1, wherein the arrangement is for a Failure Insertion Unit (abstract, provide protection to both a load and a solid state switch).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Studtmann (US 5216352 A), and further in view of Maares (EP 4178057 A1).
Regarding claim 6, Studtmann teaches the arrangement according to claim 3.
Studtmann does not teach, wherein the overload detector has a capacitor as integrator.
Maares teaches in a similar field of endeavor of protection circuit, an overload detector (i.e. overcurrent cut-off unit 51, fig.6) has a capacitor (i.e. integrator capacitor 64, fig.6) as integrator (i.e. integrator circuit 63, fig.6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the overload detector has a capacitor as integrator in Studtmann, as taught by Maares, as it provides the advantage of designing an integrator circuit in a conventional and optimal design.
Allowable Subject Matter
Claims 4-5, 8 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, Studtmann (US 5216352 A) teaches the arrangement according to claim 3.
Studtmann does not teach, wherein the control device is designed to repeatedly supply a switching signal for closing the semiconductor switch via the switching signal line to the semiconductor switch in the event the semiconductor switch has failed to close, with a time interval between the successive switching signals which is a function of the duration of receiving the overload signal and increases with it.
Prior art Duan (US 9042068 B2), Graf (US 20180191147 A1), Li (US 20060221528 A1) and Bohm (US 20190372333 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the control device is designed to repeatedly supply a switching signal for closing the semiconductor switch via the switching signal line to the semiconductor switch in the event the semiconductor switch has failed to close, with a time interval between the successive switching signals which is a function of the duration of receiving the overload signal and increases with it.”
Regarding claim 5, Studtmann (US 5216352 A) teaches the arrangement according to claim 3.
Studtmann does not teach, wherein the control device is set up to repeatedly supply a switching signal for closing the semiconductor switch via the switching signal line to the semiconductor switch in the event the semiconductor switch has failed to close, and at a maximum in a number that is a function of the duration of receiving the overload signal and coincides with it.
Prior art Duan (US 9042068 B2), Graf (US 20180191147 A1), Li (US 20060221528 A1) and Bohm (US 20190372333 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the control device is set up to repeatedly supply a switching signal for closing the semiconductor switch via the switching signal line to the semiconductor switch in the event the semiconductor switch has failed to close, and at a maximum in a number that is a function of the duration of receiving the overload signal and coincides with it.”
Regarding claim 8, Studtmann (US 5216352 A) and Maares (EP 4178057 A1) teach the arrangement according to claim 6.
Studtmann and Maares do not teach, wherein the integrator is followed by a threshold comparator and subsequently a signal isolator.
Prior art Duan (US 9042068 B2), Graf (US 20180191147 A1), Li (US 20060221528 A1) and Bohm (US 20190372333 A1) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the integrator is followed by a threshold comparator and subsequently a signal isolator.”
Regarding claim 13, the method is indicated as allowable for the same reasons as stated above for claim 4.
Regarding claim 14, the method is indicated as allowable for the same reasons as stated above for claim 5.
Conclusion
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/SREEYA SREEVATSA/ Primary Examiner, Art Unit 2838 06/29/2026
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