DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 8-9, 11-12 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“input module is configured to…” in claim 1 (Figures 2 and 4, 110);
“reset module is configured to…” in claim 1 (Figures 2 and 4, 120);
“node mutual control module is configured to…” in claim 1 (Figures 2 and 4, 130);
“output module… is configured to…” in claim 1 (Figures 2 and 4, 140); and
“setting module is configured to…” in claim 16 (Figure 20, 190).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 8-9, 11-12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (CN 105702294 A) in view of Feng et al. (CN 113160738 A).
Regarding claim 1, Wu et al. disclose a display panel, comprising a driver circuit (Figure 5), wherein the driver circuit comprises a plurality of cascaded shift register units (Figure 5); wherein
a shift register unit (Figure 2) of the plurality of cascaded shift register units comprises an input module (Figure 2, 600), a reset module (Figure 2, 500), a node mutual control module (Figure 2, 300/400), and N output modules (Figure 2, 100/200), wherein N is a positive integer (N=1);
in a same shift register unit among the plurality of cascaded shift register units (Figure 2), the input module (Figure 2, 600) is configured to receive at least an input signal (Figure 2, OUT_N-1) and a scan control signal (Figure 2, CN) and control a signal of a first node (Figure 2, 600 controls PU [first node].); the reset module (Figure 2, 400/500) is configured to receive at least a reset clock signal (Figure 2, CNB) and the scan control signal (Figure 2, CN) and control a signal of a second node (Figure 2, 400/500 controls PD [second node].); the node mutual control module (Figure 2, 300) is configured to receive at least the signal of the first node (Figure 2, 300 receives the signal of PU) and the signal of the second node (Figure 2, 300/400 receives the signal of PD), control the signal of the second node according to the signal of the first node (Figure 2, 300 controls the signal of PD according to PU using T8 and T9), and control the signal of the first node according to the signal of the second node (Figure 2, 400 controls the signal of PU according to PD using T3.); and an output module of the N output modules (Figure 2, 100/200) is configured to receive at least the signal of the first node (Figure 2, 100 receives PU), the signal of the second node (Figure 2, 200 receives PD), a first level signal (Figure 2, VSS) and an output control signal (Figure 2, CK) and control a gate drive signal (Figure 2, 100/200 controls OUT);
at least one gate drive signal of an i-th-stage shift register unit among the plurality of cascaded shift register units is an input signal of a j-th-stage shift register unit among the plurality of cascaded shift register units, wherein i
≠
j, and i and j are each a positive integer (Figure 2 shows that an input to 600 is OUT_N-1, which is an output of a previous stage of the cascaded shift register units, where i=1 and j=2);
in each display frame of the display panel, each of the reset clock signal and the output control signal comprises a plurality of effective pulses (Figure 6); and
a working mode of the display panel comprises a first mode (Figure 6); the first mode comprises at least one first display frame (Figure 6, Display1, Touch1, Display2, Touch2), and the driver circuit comprises a first shift register unit (Figure 5, there is a first shift register unit); in the first display frame, each of at least part of the output control signal received by the first shift register unit is a first-type output control signal (Figure 6 shows CK is a first-type output control signal); in the first shift register unit, a time interval between two adjacent effective pulses of the first-type output control signal is a first time interval (Figure 6 shows there is a first time interval between effective pulses of CK during Display1 and Display 2.), and a time interval between two adjacent effective pulses of the reset clock signal is a second time interval (Figure 6 shows there is a second time interval between effective pulses of CNB between Display1 and Display2.); and the second time interval falls within the first time interval (Figure 6), and the first time interval is greater than the second time interval (Figure 6, he first time interval is greater than the second time interval [see marked-up Figure 6 below].).
Wu et al. fail to teach wherein the second time interval falls within the first time interval during a display stage of the first display frame.
Feng et al. disclose a display panel (Figure 1), comprising a driver circuit (Figure 1, 130a), wherein the driver circuit comprises a plurality of cascaded shift register units (Figure 2, 131), wherein a time interval between two adjacent effective pulses of a first-type output control signal is a first time interval (Figures 3 and 4, ELCK is a first-type output control signal in the output module, wherein t1-t4 are repeated so as to create a first time interval between two effective pulses of ECLK.) and a time interval between two adjacent effective pulses of a reset clock signal is a second time interval (Figures 3 and 4, ERST is a reset clock signal, which shows numerous effective pulses, one per period of t1, t2, t3 and t4, with the time between two of the pulses being a second time interval.), wherein the second time interval falls within the first time interval during a display stage of the first display frame (Figure 4 shows that during the display stage, the time between the effective pulses of ERST is numerous and falls within a time between ECLK.).
Therefore, it would have been obvious to “one of ordinary skill” in the art between the effective filing date of the claimed invention to use the frequency of the reset signal teachings of Feng et al. in the display period taught by Wu et al. such that each of the reset clock signal and the output control signal comprises a plurality of effective pulses in each display frame of the display panel, and wherein the second time interval falls within the first time interval during a display stage of the first display frame. The motivation to combine would have been in order to improve light emission by holding the emission signal in a high state until the next display frame, which in combination would be particularly useful during the touch intervals so as to prevent a reduction in display brightness, thus improving display quality (See, for example, page 49 of the provided document of Feng et al., third paragraph: “when the voltage of the EQ node becomes high state under the action of gating high voltage VGH…As a result, even if the light emitting control reset signal ERST changes from high state to low state, the light emitting control pull-up switch element EPUT can be kept on. That is, the light emitting control signal EM can be held in a high state until the first time period t1 after the fourth time period t4 and the fourth time period t4.”).
Regarding claim 8, Wu et al. and Feng et al. disclose the display panel of claim 1, wherein in a case where N is greater than or equal to 2 (Wu: Figure 2, 100 and 200, N=2), in a same shift register unit among the plurality of cascaded shift register units, the N output modules receive different output control signals respectively (Wu: Figure 2, 100 receives PU and 200 receives PD), and effective pulse time of output control signals received by the plurality of cascaded shift register units is shifted sequentially (Wu: Figure 6).
Regarding claim 9, Wu et al. and Feng et al. disclose the display panel of claim 8, wherein in a same shift register unit among the plurality of cascaded shift register units (Wu: Figure 2), an output control signal received by a k-th output module is a k-th output control signal, and effective pulse time of the k-th output control signal is before effective pulse time of a (k + 1)-th output control signal, wherein k is a positive integer, and k is less than N (Wu: K=1, K is less than 2 [N], and the effective pulse time if the 1st output control signal will be before the time of the 2nd output control signal, see Figure 6); and a gate drive signal output by a first output module of the i-th-stage shift register unit or an N-th output module of the i-th-stage shift register unit is the input signal received by the input module of the j-th-stage shift register unit (Wu: Figure 2, OUT_N-1 is received by the input module of the 2nd [j] stage shift register unit, where OUT_N-1 of the 2nd stage is the output of the 1st stage, i.e. i-th stage. [i=1].).
Regarding claim 11, Wu et al. and Feng et al. disclose the display panel of claim 9, wherein at least one of following is satisfied:
a reset clock signal of the j-th-stage shift register unit also serves as a reset clock signal of a (j+2)-th-stage shift register unit (Wu: Figures 5-6 show CNB is the reset clock for every stage.); or
a k-th output control signal of the j-th-stage shift register unit also serves as a k-th output control signal of a (j+2)-th-stage shift register unit.
Regarding claim 12, Wu et al. and Feng et al. disclose the display panel of claim 1, wherein in a case where N is equal to 1, at least one of following is satisfied:
a gate drive signal of the j-th-stage shift register unit is an input signal of a (j+1)-th-stage shift register unit, wherein j is a positive integer (Wu: Figure 2, the inputs are OUT_N-1 and OUT_N+1.),
a reset clock signal of the j-th-stage shift register unit also serves as a reset clock signal of a (j + 4)-th-stage shift register unit; or
an output control signal of the j-th-stage shift register unit also serves as an output control signal of a (j + 4)-th-stage shift register unit.
Regarding claim 20, please refer to the rejection of claim 1, and furthermore Wu et al. also disclose of a display device (Wu: See the title of the invention, for example.).
Allowable Subject Matter
Claims 2-7, 10 and 13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reasons for indicating allowable subject matter in claim 2 is the inclusion of the limitations reciting “wherein in the first display frame and in the first shift register unit, an input signal comprises an effective pulse, the reset clock signal comprises one first reset effective pulse, and the first-type output control signal comprises one first output effective pulse; in the effective pulses of the reset clock signal, a first effective pulse after the effective pulse of the input signal is the first reset effective pulse; in effective pulses of the first-type output control signal, a first effective pulse after the effective pulse of the input signal is the first output effective pulse; and time of the first reset effective pulse is before time of the first output effective pulse” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
Claims 3-7 are objected to due to their dependency from claim 2.
The primary reasons for indicating allowable subject matter in claim 10 is the inclusion of the limitations reciting “wherein a reset clock signal of the j-th-stage shift register unit also serves as a first output control signal of a (j+1)-th-stage shift register unit among the plurality of cascaded shift register units” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
The primary reasons for indicating allowable subject matter in claim 13 is the inclusion of the limitations reciting “wherein in the first display frame, the scan control signal received by the first shift register unit comprises one scan ineffective pulse” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
Claims 14-15 are objected to due to their dependency from claim 13.
The primary reasons for indicating allowable subject matter in claim 16 is the inclusion of the limitations reciting “in the first display frame, the setting signal comprises at least one setting effective pulse, and an input signal received by the first shift register unit comprises one input effective pulse; and time of the at least one setting effective pulse is after time of the input effective pulse” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
The primary reasons for indicating allowable subject matter in claim 17 is the inclusion of the limitations reciting “in the first mode, the display region comprises a first sub-display region and a second sub-display region; and in the first display frame, gate drive lines located in the first sub-display region are first gate drive lines, and gate drive lines located in the second sub-display region are second gate drive lines; and effective pulse time of gate drive signals transmitted by the first gate drive lines is shifted sequentially, and gate drive signals transmitted by the second gate drive lines are at an ineffective level” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
The primary reasons for indicating allowable subject matter in claim 18 is the inclusion of the limitations reciting “wherein the display panel further comprises a second mode; and in one display frame in the second mode, in a same shift register unit among the plurality of cascaded shift register units, a time interval between two adjacent effective pulses of the output control signal is equal to the time interval between the two adjacent effective pulses of the reset clock signal” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
The primary reasons for indicating allowable subject matter in claim 19 is the inclusion of the limitations reciting “wherein the node mutual control module comprises a first mutual control transistor and a second mutual control transistor; wherein in a same shift register unit among the plurality of cascaded shift register units, a gate of the first mutual control transistor is electrically connected to the second node, a first electrode of the first mutual control transistor is configured to receive the first level signal, and a second electrode of the first mutual control transistor is electrically connected to the first node; and a gate of the second mutual control transistor is electrically connected to the first node, a first electrode of the second mutual control transistor is configured to receive the first level signal, and a second electrode of the second mutual control transistor is electrically connected to the second node” which, in combination with the other recited features, is not taught and/or suggested either singularly or in combination within the prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/STEPHEN G SHERMAN/Primary Examiner, Art Unit 2621
11 February 2026