DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 9 are objected to because of the following formalities :
Claim 1 recites the “ransom number”, this appears to be a typo and should be “random number instead.
Claim 9 recites “an encryption circuit suppled with power” should be “the encryption circuit supplied with” instead since
Appropriate correction is required.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6, and 8-10 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Vaidya 20190007223.
Regarding Claim 1. Vaidya a semiconductor device that supplies power to an encryption circuit [Fig. 1-3, par. 15-17, on die power circuits 104/106 on die and include buck converter and/or a boost converter supplying power to encryption circuit 108], the semiconductor device comprising:
a voltage generator [Fig. 1-3] including a series regulator [converter 106, connecting in series to 108] and a shunt regulator [capacitor 104, par. 20-23, capacitor dissipates leftover power to ground, i.e. shunt regulator]
a controller configured to randomly switch the shunt regulator between an ON state and OFF state. [par. 18. 20, power converter 106 operates switches 206 to conductively couple the capacitor to either the power source 104 or the encryption circuitry 108 based on randomizer 208. See also par. 11, 26-27]
Claim 2. Vaidya teaches the semiconductor device according to claim 1, wherein the controller operates the shunt regulator in each of:
a first operation mode in which the shunt regulator is maintained in the ON state; [par. 20, FIG. 2B a state of power converter 106 in which capacitor 204 is being used to power encryption circuitry 108] and a second operation mode in which the shunt regulator is maintained in the OFF state [ par. 20 FIG. 2 A a state of power converter 106 in which capacitor 204 is being charged and not supplying power to the encryption circuitry, see also par. 24].
Claim 4. Vaidya teaches the semiconductor device according to claim 1, further comprising: a random number generating circuit configured to generate a random number [par. 20, 27-29, digital power signature]; and a random pattern generating circuit configured to generate a random pattern corresponding to the random number [par. 20, 27-29, randomizer 208 provide a power signature varied with the encryption circuitry and includes a voltage regulator digitally controlled] wherein the controller switches the shunt regulator between the ON state and the OFF state in accordance with the random pattern [par. 20, randomizer 208 may be utilized by power converter 106 to vary the voltage output to encryption circuitry 108.
Claim 5. Vaidya teaches the semiconductor device according to claim 4, wherein operation timing of the random pattern generating circuit is synchronous to operation timing of the encryption circuit [par. 27, the voltage level provided to encryption circuitry 108 may be varied with randomizer 208 and further randomize the power signature of encryption circuitry]
Claim 6. Vaidya teaches the semiconductor device according to claim 1, wherein the voltage generator includes a current feedback circuit configured to supply the shunt regulator with a current when the shunt regulator is in the ON state, the current corresponding to a current output from the series regulator [par. 25, Power converter 106 may charge or recharge capacitor 204 with power source 104 such that current passes from power source 104 into inductor 202 and then into capacitor 204]
Claim 8. Vaidya teaches the semiconductor device according to claim 1, wherein the shunt regulator is connected to an output end of the series regulator [Fig. 2, switches 206-2 and 206-3 provide connection to capacitor 104].
Claim 9. Vaidya teaches an encryption device [Fig. 1, item 102], comprising: the semiconductor device according to claim 1; and an encryption circuit supplied with power by the semiconductor device [Fig. 1-3, par .15-17] .
Claim 10. Vaidya teaches an electronic appliance including the encryption device according to claim 9. [Fig. 1 and 6, par. 59].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vaidya in view of Seok, 20130191652 A1.
Claim 7. Vaidya teaches the semiconductor device according to claim 1 but does not teach wherein the shunt regulator includes a shunt resistor a resistance value. Seok teaches an encryption circuit having a random generator [Fig. 6, noise generator 602] to superimpose on the current consumed by the encryption circuit [206] having an active shunt [abstract] wherein the shunt regulator [Fig. 4 and 6, par. 16-18, 20 and 22] includes a shunt resistor a resistance value of which is variable the shunt resistor [Fig. 4, par. 20-21, variable resistor R4]] being connected to a terminal that receives a voltage to be input to the voltage generator [ Vin to bus 404, 406]. It would have been obvious to one having ordinary skill in the art before the effective filing date to incorporate the active shunt circuit of Seok in order to help to maintain the current drawn at a substantially constant value to make it more difficult to crack encryption algorithm using differential power analysis and therefore provide a more secure information from the AES circuit [Seok, par. 2 and 22]
Conclusion
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/KIM HUYNH/Primary Patent Examiner, Art Unit 2176
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