Prosecution Insights
Last updated: August 30, 2026
Application No. 18/975,073

AC-TO-DC CONVERTER WITHOUT VOLTAGE MEASUREMENT OF AC POWER SOURCE

Non-Final OA §102§103
Filed
Dec 10, 2024
Priority
Dec 20, 2023 — EU 23307279.2
Examiner
CHAI, RAYMOND REI-YANG
Art Unit
Tech Center
Assignee
NXP Semiconductors N.V.
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
422 granted / 566 resolved
+14.6% vs TC avg
Strong +16% interview lift
Without
With
+16.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
38 currently pending
Career history
595
Total Applications
across all art units

Statute-Specific Performance

§101
3.7%
-36.3% vs TC avg
§103
49.1%
+9.1% vs TC avg
§102
17.4%
-22.6% vs TC avg
§112
22.6%
-17.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 566 resolved cases

Office Action

§102 §103
DETAILED ACTION Acknowledgement is made of the preliminary amendment submitted on 12/10/2024. In virtue of this amendments: Claims 16-20 are newly added; Claims 1, 5, 8 and 13-14 are currently amended; and thus, Claims 1-20 are pending; Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy of EP23307279.2 filed on 12/20/2023 has been received/retrieved by the office. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/10/2024 has been considered by the examiner. Claim Objections Claim 1 is objected to because of the following informalities: Regarding claim 1, the term “econd” on line 6 appears to be a typographical error and should read -second-. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-7, 9-15 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US2018/0301992A1 hereinafter “Yeh” Regarding claim 1, Yeh discloses an AC-to-DC converter system (¶3L9-10: convert AC into DC) comprising: a transistor network (¶19L8: a rectifying unit) operable to be connected to an alternating current (AC) power source (¶20L29: a three-phase AC current; as shown in Fig.5 for example), the transistor network including at least a first transistor (¶34L3-4: the rectifying unit includes a plurality of switching component M1-M6; as shown in Fig.5 M1, M3 and M5) connected in series (as shown in Fig.5, M1 is in series with M2, M3 is in series with M4 and M5 is in series with M6) with a second transistor (¶34L3-4: the rectifying unit includes a plurality of switching component M1-M6; as shown in Fig.5 M2, M4 and M6) that is connected to a low voltage terminal (as shown in Fig.5, M2, M4 and M6 are connected to ground); a plurality of transistor drivers connected to at least the first and second transistors to drive the first and second transistors (¶35L1-3: the control unit includes a switching control unit; as shown in Fig.5, control unit has multiple output for each transistor); and a controller unit (¶33L7: a control unit) connected to the transistor drivers to control the first and second transistors (¶39L1-5: the switching control module is used for controlling a switching signal of at least one of plurality of switching component M1-M6) , the controller unit being operable to detect negative-to-positive and positive- to-negative transitions of a voltage of the AC power source using detected voltages across the first and second transistors. (¶20L15-39: the voltage across the drain and the source terminals (VDS) of the switching component M1 is compared to obtain a voltage VAH. VAH can then obtain frequency information of the VAH by zero cross detection) Regarding claim 2, Yeh discloses the AC-to-DC converter system of claim 1, wherein the controller unit is operable to apply a stimuli signal to the second transistor to measure a voltage across the first transistor to detect a negative-to-positive transition of the voltage of the AC power source. (¶21-32) Regarding claim 3, Yeh discloses the AC-to-DC converter system of claim 2, wherein the controller unit is operable to apply the stimuli signal to a control terminal of the second transistor and wherein the voltage across the first transistor is a voltage across current-path terminals of the first transistor. (¶21-32) Regarding claim 4, Yeh discloses the AC-to-DC converter system of claim 3, wherein the first and second transistors are field-effect transistors, wherein the controller unit is operable to apply the stimuli signal to a gate of the second transistor, and wherein the voltage across current-path terminals of the first transistor is a drain-to-source voltage of the first transistor. (¶21-32) Regarding claim 5, Yeh discloses the AC-to-DC converter system of any of claim 2, wherein the controller unit is operable to generate the stimuli signal, wherein the stimuli signal is a pulse width modulation (PWM) signal. (s shown in Fig.7B for example, Vg1 is a PWM signal) Regarding claim 6, Yeh discloses the AC-to-DC converter system of any of claim 1, wherein the controller unit is operable to apply a stimuli signal to the first transistor to measure a voltage across the second transistor to detect a positive-to-negative transition of the voltage of the AC power source. (¶21-32) Regarding claim 7, Yeh discloses the AC-to-DC converter system of claim 6, wherein the controller unit is operable to apply the stimuli signal to a control terminal of the first transistor and wherein the voltage across the second transistor is a voltage across current-path terminals of the first transistor. (¶21-32) Regarding claims 9-15, the claims are similar in scope with claims 1-7, respectively, with the expectation of being recited in method form, and therefore rejected in the same manner. Regarding claim 17, the claim is similar in scope with claim 1, with the expectation of limitation “a transistor network connected to the inductor” which is also disclosed by Yeh as shown in Fig.5 for example, and therefore is also rejected in the same manner as claim 1 above. Regarding claims 18-20, the claims are similar in scope with claims 2, 5 and 6, respectively, with the expectation of being recited in method form, and therefore rejected in the same manner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yeh in view of US2015/0333637A1 hereinafter “Izumi” Regarding claim 16, Yeh discloses the method of claim 9, Yeh does not disclose: detecting an error related to measurements of the voltage of the AC power source. Izumi discloses a AC/DC converter wherein a power supply fault is detected. (¶97) It would have been obvious to one ordinarily skilled in the art prior to the effective filing date of the application to incorporate the power supply fault detection disclosed by Izumi into the system disclosed by Yeh. One of ordinary skill in the art would’ve been motivated because this allows the system to be shut off to prevent damage when fault is detected. Allowable Subject Matter Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 8, Yeh does not disclose the operation of detecting the zero-cross using the voltages across the transistors when an error is detected with the measurement of the AC voltage. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAYMOND R CHAI whose telephone number is (571)270-0576. The examiner can normally be reached M-F 9:30AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 571-242-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Raymond R Chai/Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

Dec 10, 2024
Application Filed
Jun 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
91%
With Interview (+16.4%)
1y 10m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 566 resolved cases by this examiner. Grant probability derived from career allowance rate.

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