DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
Examiner states for the record that no Information Disclosure Statement is presently filed in this application.
Claim Interpretation
“Logic” has been limited to hardware implementations in accordance with the definition in the specification [par. 0061].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Irish et al. (Pub. No. US 2007/0180156) in view of Steely, JR et al. (Pub. No. US 2013/0339621).
Claim 10:
Irish et al. disclose a system comprising:
an interface bus [fig. 1; par. 0029 – “While one 10 device 120 is illustrated in FIG. 1, one skilled in the art will recognize that any number of IO devices 130 may be coupled to the CPU on the same or multiple busses.”];
a memory device [fig. 1 – cache 114]; and
at least one processor electrically coupled to the memory device [fig. 1 – central processing unit 110 or command processor 111], the at least one processor configured to:
receive an address translation request comprising a virtual memory address [figs. 1-2; pars. 0031, 0043 – “CPU 110 may include a command processor 111, translate logic 112, an embedded processor 113 and cache 114. Command processor 111 may receive one or more commands 131 from IO device 120 and process the command. Each of commands 131 may be broadly classified as commands requiring address translation and commands without addresses. Therefore, processing the command may include determining whether the command requires address translation. If the command requires address translation, the command processor may dispatch the command to translate logic 112 for address translation. After those of commands 131 requiring translation have been translated, command processor may place ordered commands 133 on the on-chip bus 117 to be processed by the embedded processor 113 on the memory controller 118.” … “Referring back to FIG. 2, the translate logic 112 may process address translation requests from the TIIC. Address translation may involve looking up segment and page tables to convert a virtual address to an actual physical address in memory 140.”];
read a memory address from a translation table stored in the memory device based on the virtual memory address from a client device over the interface bus [figs. 1-2; pars. 0029, 0034-0036, 0043 – “Address translation may involve looking up segment and page tables to convert a virtual address to an actual physical address in memory 140. In some embodiments, the translate logic may allow pipelined access to the page and segment table caches.”]; and
transmit the memory address in response to the address translation request to the client device over the interface bus [fig. 2; pars. 0029, 0043 – “If no miss occurs during address translation, the translate logic may provide translation results to the Translate Interface Output Control (TIOC) 203, as illustrated in FIG. 2.”].
However, Irish et al. do not specifically disclose,
the system comprised within a die [fig. 2; par. 0031 – Irish et al. disclose a command processor, but does not specifically disclose that the command processor is embodied within a single die.];
In the same field of endeavor, Steely, JR. et al. disclose,
the system comprised within a die [par. 0002 – “A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, or logical processors. The ever increasing number of processing elements--cores, hardware threads, and logical processors--on integrated circuits enables more tasks to be accomplished in parallel.”];
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Irish et al. to include a single die, as taught by Steely, JR et al. in order to improve performance by lowering latency between components.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Irish et al. (Pub. No. SU 2007/0180156) in view of Steely, JR et al. (Pub. No. US 2013/0339621) as applied to claim 10 above, and further in view of Isloorkar (Pub. No. US 2014/0156930).
Claim 11 (as applied to claim 10 above):
Irish et al. and Steely, JR et al. disclose all the limitations above but do not specifically disclose, wherein the at least one processor is configured to:
receive an invalidation command; and
invalidate a cache of the memory device based on receiving the invalidation command, wherein the translation table is stored in the cache.
In the same field of endeavor, Isloorkar discloses,
receive an invalidation command [par. 0089 – “It should be noted that an invalidate request may come from software on the processor that detects a change in context on one of the masters and as the page tables used by that context are no longer required they should be invalidated such that pages tables that are to be used can be stored in the caches. Similarly, update requests will just be dropped and no update will be performed. This avoids the caches being accessed unnecessarily and saves power.”]; and
invalidate a cache of the memory device based on receiving the invalidation command, wherein the translation table is stored in the cache [par. 0089 – “It should be noted that an invalidate request may come from software on the processor that detects a change in context on one of the masters and as the page tables used by that context are no longer required they should be invalidated such that pages tables that are to be used can be stored in the caches. Similarly, update requests will just be dropped and no update will be performed. This avoids the caches being accessed unnecessarily and saves power.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Irish et al. and Steely, JR et al. to include invalidating page tables, as taught by Isloorkar, in order to improve performance and save power.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Irish et al. (Pub. No. SU 2007/0180156) in view of Steely, JR et al. (Pub. No. US 2013/0339621) as applied to claim 10 above, and further in view of Raindel (Pub. No. US 2014/0089450).
Claim 12 (as applied to claim 10 above):
Irish et al. and Steely, JR et al. disclose all the limitations above but do not specifically disclose,
wherein the memory address is a first memory address, and wherein the at least one processor is configured to: read a second memory address from a second translation table based on the first memory address; and transmit the second memory address in response to the address translation request.
In the same field of endeavor, Raindel et al. disclose,
wherein the memory address is a first memory address, and wherein the at least one processor is configured to: read a second memory address from a second translation table based on the first memory address; and transmit the second memory address in response to the address translation request [par. 0034 – “First, translation from virtual to "physical" addresses using respective page tables for each guest domain, and then translation from these "physical" addresses to actual machine memory addresses. (The "physical" addresses in this context are regarded by the guest operating systems as real, physical memory addresses, but they are, in fact, virtual addresses at the intermediate stage of address translation. The term "physical address," in the context of the present patent application and in the claims, should thus be understood as including this sort of intermediate virtual address, as well as actual machine addresses.) Page faults may occur at either stage of the address translation process, and the techniques for handling and avoiding page faults that are described herein may be applied at either or both of these stages.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Irish et al. and Steely, JR et al. to include virtualization, as taught by Raindel et al., in order to increase security.
Allowable Subject Matter
Claims 1, 3, 5-9, 13-15, 17-20 allowed.
Response to Arguments
Applicant’s arguments with respect to claim(s) 10-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. More specifically, the limitations of claim 15 had not previously been considered with respect to claim 10, as claim 15 depends form claim 13.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
11 June 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139
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