Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to application filed on 12/10/2024. Claims 1-11 are pending for examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/10/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ochiai., US 2022/0270655 A1.
Regarding claims 1 and 10-11, Ochiai teaches a memory controller that is connectable to a memory that includes a plurality of bank groups that each includes a plurality of banks (see abstract and section 0005; a memory control circuit is configured to access a memory including a plurality of banks), the memory controller comprising:
a holding circuit configured to hold a plurality of access requests to the memory (Fig.1 and section 0024; An access holding circuit 110 holds a plurality of access requests received from the external circuit);
a read and write control circuit (Fig.1; a read/write control circuit 130) configured to generate read or write commands from each of the plurality of access requests (section 0027; The read/write control circuit 132 determines, from accesses held in the access holding circuit 110, an access (read or write) corresponding to the access type indicated by the prioritized command, and issues a read (RD) command or a write (WR) command) such that banks of different bank groups are set as destinations of adjacent read or write commands (section 0025 and section 0034 and Fig.9; each adjacent command will be the access command to the different banks); and
a page control circuit configured to issue a page control command for an access request that is selected from the plurality of access requests (sections 0032-0041; it is taught as page being already open), wherein
the page control circuit preferentially issues a page control command for an access request for which open or close states of pages of a plurality of banks that are set as destinations satisfy a predetermined condition (sections 0031-0041; the access holding circuit 110 holds three accesses, respectively expressed as access 0, access 1 and access 2. Each access includes “bank, page, read/write, number of times” as its content. Each bank state includes “open/close, page (in the case of open)” as its content).
Regarding claim 2, Ochiai teaches the page control circuit preferentially issues a page control command for an access request that includes, as destinations, a bank in a state where the page control command can be issued and a bank in a state where the page control command does not need to be issued (sections 0031-0036; the number of banks is two, and the bank state managed by the bank state management circuit 123 is expressed as bank state 0 and bank state 1. Each bank state includes “open/close, page (in the case of open)” as its content).
Regarding claim 4, Ochiai teaches the page control circuit preferentially issues a page control command for an access request that includes, as destinations, a bank in a state where the page control command needs to be issued and a bank in a state where the page control command does not need to be issued (sections 0031-0036; the number of banks is two, and the bank state managed by the bank state management circuit 123 is expressed as bank state 0 and bank state 1. Each bank state includes “open/close, page (in the case of open)” as its content).
Regarding claim 6, Ochiai teaches in a case where there is a plurality of page control commands generated from one access request for which states of a plurality of destination banks satisfy the predetermined condition, the page control circuit preferentially issues a page control command to a bank that is accessed first from among the plurality of banks (section 0035-0036; it is assumed that the access holding circuit 110 holds three accesses, respectively expressed as access 0, access 1 and access 2. Each access includes “bank, page, read/write, number of times” as its content. Here, the number of times is assumed to be decremented each time a read or a write command is issued).
Regarding claim 7, Ochiai teaches in a case where there are two or more access requests in which states of a plurality of destination banks satisfy the predetermined condition, the page control circuit preferentially issues a page control command that is generated from an access request that was held in the holding circuit first, from among the plurality of access requests (section 0035-0036; it is assumed that the access holding circuit 110 holds three accesses, respectively expressed as access 0, access 1 and access 2. Each access includes “bank, page, read/write, number of times” as its content. Here, the number of times is assumed to be decremented each time a read or a write command is issued).
Regarding claim 8, Ochiai teaches the read and write control circuit generates a read or write command for an access request that is selected from remaining access requests obtained by removing an access request that includes, as a destination, a bank group in which a prefetch is being executed, from the plurality of access requests (section 0026-0027; the prioritized command management circuit 131 uses the bank state managed by the bank state management circuit 123 to determine which access type of command issuance that is read or write is to be prioritized. In the following, the access type of command issuance to be prioritized is referred to as a prioritized command. The read/write control circuit 132 determines, from accesses held in the access holding circuit 110, an access (read or write) corresponding to the access type indicated by the prioritized command, and issues a read (RD) command or a write (WR) command).
Regarding claim 9, Ochiai teaches the read and write control circuit determines whether a read command or a write command is preferentially issued, based on access types of the plurality of access requests and states of destination banks of the plurality of access requests (sections 0026-0027; the prioritized command management circuit 131 uses the bank state managed by the bank state management circuit 123 to determine which access type of command issuance that is read or write is to be prioritized. In the following, the access type of command issuance to be prioritized is referred to as a prioritized command. Details will be described below, referring to FIG. 2. The read/write control circuit 132 determines, from accesses held in the access holding circuit 110, an access (read or write) corresponding to the access type indicated by the prioritized command, and issues a read (RD) command or a write (WR) command).
Allowable Subject Matter
Claims 3 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The limitations not found in the prior art of record include the page control command is an active command, the bank in a state where the page control command can be issued is a bank in which all pages are closed, and the bank in a state where the page control command does not need to be issued is a bank in which a target page of a read or write command that is generated from an access request is open in combination with the other claimed limitations as described in the claim 3.
The limitations not found in the prior art of record include the page control command is a precharge command, the bank in a state where the page control command needs to be issued is a bank in which a page different from a target page of a read or write command that is generated from an access request is open, and the bank in a state where the page control command does not need to be issued is a bank in which a page different from a target page is not open in combination with the other claimed limitations as described in the claim 5.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shiraishi., US 2022/0246187 A1 teaches a memory controller for accessing a memory, comprises a holding circuit which holds a plurality of read or write access requests from a bus master, a read/write control circuit which selects one of the access requests in the holding circuit and issues a read command or a write command; and an active control circuit which selects the access request held in the holding circuit and issues an active command, wherein the active control circuit includes a generation circuit that generates number of activated read commands and number of activated write commands, and a selection circuit that, when the number of activated read commands is not less a threshold, issues the active command of an read access, and when the number of activated write commands is not less than the threshold, issues the active command of a write access.
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUA JASMINE SONG whose telephone number is (571)272-4213. The examiner can normally be reached on 9:00am to 5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http:/Wwww.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ROCIO DEL MAR PEREZ-VELEZ can be reached on 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer
Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUA J SONG/Primary Examiner, Art Unit 2133