DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/14/25 has been considered by the examiner.
Drawings
The drawings received on 12/10/24 are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 8-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lev (US 2009/0034299 A1).
Lev discloses an apparatus and method for high efficiency isolated power converter in Figures 1-8.
Regarding claim 1, Lev discloses a voltage converter system (two-way converter 10) (abstract, Fig. 1, 3, para. [0027], [0031]: FIG. 1B depicts converter 4 with a two-stage structure coupled by a transformer TR, where the power flows through the first stage (primary stage) and then through the second stage (secondary stage) Secondary stage may be electrically isolated from the primary stage by transformer TR which may also provide a step-down or step-up function of DC and AC output voltages. Both primary and secondary stages of converter 4 may comprise dual switching topology with switching means Q10 a-Q10 b and Q20 a-Q20 b respectively FIG. 3A (and may be applicable to converters presented in other drawings as well, with the required changes) converter 10 may comprise a first stage comprising capacitors C2, C3 and C4 and switching means SW1 and Sw2, all connected between two poles of Vin, denoted Vin+ and Vin- respectively) comprising: two or more Active Half Bridge AHB converter circuits (first stage w/ SW1, SW2, C3, C4 & second stage w/ SW9, SW10, C9, C10), each
of the two or more AHB converter circuits (first & second stages) connected to one or more windings of a transformer (coupling transformer TR1), with each AHB converter circuit (first & second stages) including one or more switches (switching assemblies SW1, SW2, SW3, SW4) and one or more energy storage devices (capacitors C3, C, 4) (Fig. 1, 3, para. [0028]-[0032]: Secondary stage may substantially be a mirror picture of the primary stage: switching transistor T3, T4, diodes D3 and D4, parasitic or implemented capacitors C7 and C8; auxiliary capacitors C9, C10 and filtering capacitor C11. The two stages may be coupled through transformer TR1 which may
comprise magnetizing inductance represented by inductor M and leakage inductances represented by inductors Ls1, Ls2; resonant inductance L1 and resonant capacitor C1 FIG. 3A converter 10 may comprise a first stage comprising capacitors C2, C3 and C4 and switching means SW1 and Sw2, all connected between two poles of Vin, denoted Vin+ and Vin- respectively. Switching means SW1 and Sw2 may be connected in a totem-pole arrangement with a central tap denoted "1". Converter 10 may comprise a second stage comprising switching means SW3 and SW4 and capacitors C9, C10 and C111, all connected between two poles of Vout, denoted Vout+ and Vout- respectively. Switching means SW3 and SW4 may be connected in a totem-pole arrangement with a central tap denoted "2" Converter 10 may comprise a return path between said first and said second stages connected between point "3", being a third central tap between capacitor C3 and capacitor C4 and point "4" being a fourth central tap between capacitor C9 and capacitor C10. The return path of resonance circuit may be connected directly between points "3" and "4" or via a coupling transformer TR1. When switching
assemblies SW1 and SW3 are conducting (that is are switched ON), switching assemblies SW2 and SW4 are gated OFF; capacitor CSW1 of switching assembly SW1 is charged to 0 volts, capacitor CSW2 of switching assembly SW2 is charged to Vin, capacitor CSW3 of switching assembly SW3 is charged to 0 volts, and capacitor C10 to Vout. Resonant inductor L1 and leakage inductances Ls1, Ls2, magnetized by currents Isw1,2 and Isw3,4 are flowing from Vin to Vout (the description of currents Isw1,2 and Isw3,4 as flowing 'through' transformer TR1 is a common way of describing a simplified transformer coupled circuitry, specifically if the transformation ratio is 1:1)); and one or more controllers (controller 36) to control electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages, via gating control signals VGSW of switching means SW1-SW4) according to normalized switching functions (switching timing schemes/gating) representing switching states of switches (ON, OFF via
gates of SW1-SW4) of the two or more AHB converter circuits (first & second stages) (Fig. 1, 3, para. [0030]-[0033], [0041], [0042]: Assembly SWx may be any other appropriate device and circuitry. The control terminal denoted VgSWx is the control terminal through which switching assembly SWx may be turned (or gated) ON or OFF by a control circuitry 36 (FIG. 2B). FIGS. 3A-3F are shown without a control unit, such as controller 36 of FIG. 2. Controller 36, may be used to control the operation of converter 10 by means of gating its switching devices SW1-SW4 ON or OFF at the desired timing when switching assemblies SW1 and SW3 are conducting (that is are
switched ON), switching assemblies SW2 and SW4 are gated OFF; capacitor CSW1 of switching assembly SW1 is charged to 0 volts, capacitor CSW2 of switching assembly SW2 is charged to Vin, capacitor CSW3 of switching assembly SW3 is charged to 0 volts, and capacitor C10 to Vout, FIG. 3B shows the next step in the sequence of four steps After the switching assembly SW1 is gated OFF by control signal VGSW1, current ISW1,2 begins to charge capacitors CSW1 and CSW2. Because the initial voltage on capacitor CSW1 is substantially zero, the mode of the switching is substantially ZVS, because the switching of switching assembly SW1 is done when the voltage across its terminals is substantially zero).
Regarding claim 2, Lev discloses the voltage converter system of claim 1, wherein the two or more AHB converter circuits (first & second stages) implement a dual active half bridge DAHB converter circuit (two-way converter 10 with first & second stages) with a primary side (first stage w/ SW1, SW2, C3, C4) and a secondary side (second stage w/ SW9, SW10, C9, C10) separated from the primary side by the transformer (coupling transformer TR1), the primary side (first stage) comprising two primary side capacitors (capacitors C3, C4), two primary side controllable switching devices (switching assemblies SW1, SW2), and the secondary side (second stage) comprising two
secondary side capacitors (capacitors C9, C10), and two secondary side switching devices (switching assemblies SW3, SW4) (Fig. 1, 3, para. [0028]-[0032]: Secondary stage may substantially be a mirror picture of the primary stage: switching transistor T3, T4, diodes D3 and D4, parasitic or implemented capacitors C7 and C8; auxiliary capacitors C9, C10 and filtering capacitor C11. The two stages may be coupled through transformer TR1 which may comprise magnetizing inductance represented by inductor M and leakage inductances represented by inductors Ls1, Ls2; resonant inductance L1 and resonant capacitor C1 FIG. 3A converter 10 may comprise a first stage comprising capacitors C2, C3 and C4 and switching means SW1 and Sw2, all connected between two poles of Vin, denoted Vin+ and Vin-respectively. Switching means SW1 and Sw2 may be connected in a totem-pole arrangement with a central tap denoted "1". Converter 10 may comprise a second stage comprising switching means SW3 and SW4 and capacitors C9, C10 and C111, all connected between two poles of Vout, denoted Vout+ and Vout- respectively. Switching means SW3 and SW4 may be connected in a totem-pole arrangement with a central tap denoted "2" Converter 10 may comprise a return path between said first and said second stages connected between point "3", being a third central tap between capacitor C3 and capacitor C4 and point "4" being a fourth central tap between capacitor C9 and capacitor C10. the return path of resonance circuit may be connected directly between points "3" and "4" or via a coupling transformer TR1. When switching assemblies SW1 and SW3 are conducting (that is are switched ON), switching assemblies SW2 and SW4 are gated OFF; capacitor CSW1 of switching assembly SW1 is charged to 0 volts, capacitor CSW2 of switching assembly SW2 is charged to Vin, capacitor CSW3 of switching assembly SW3 is charged to 0 volts, and capacitor C10 to Vout. Resonant inductor L1 and leakage inductances Ls1, Ls2, magnetized by currents Isw1,2 and Isw3,4 are flowing from Vin to Vout (the description of currents Isw1,2 and Isw3,4 as flowing 'through' transformer TR1 is a common way of describing a simplified transformer coupled circuitry, specifically if the
transformation ratio is 1:1)).
Regarding claim 3, Lev discloses the voltage converter system of claim 2, wherein the electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the DAHB converter circuit (10) includes voltages and currents behavior (voltages: input Vref-AC, output Vref-DC, VSW1-2, VGSW3-4 & currents ISW1-2 ISW3-4) for the two primary side capacitors (C3, C4) and the two secondary side capacitors (C9, C10), wherein the voltages and currents behavior (voltages: VSW1-2, VGSW3-4 & currents ISW1-2 ISW3-4), and control signals (control signals V-GSW) to control behavior of the DAHB converter circuit (10), are computed as functions of values
(switching frequency) of the normalized switching functions (switching timing schemes/gating) (Fig. 1, 3-8, para. [0029]-[0032], [0041]-[0053]: Controller 36 may further receive VREF AC representing actual voltage on the input terminals of converter 20; VREF DC to provide reference for the desired DC voltage and VFB OUT to provide feedback for the operation of converter 20 by providing voltage from the output terminals of converter 20 Converter 10 may comprise a first stage comprising capacitors C2, C3 and C4 and switching means SW1 and Sw2, all connected between two poles of Vin, denoted Vin+ and Vin- respectively. When switching assemblies SW1 and SW3
are conducting (that is are switched ON), switching assemblies SW2 and SW4 are gated OFF; capacitor CSW1 of switching assembly SW1 is charged to 0 volts, capacitor CSW2 of switching assembly SW2 is charged to Vin, capacitor CSW3 of switching assembly SW3 is charged to 0 volts, and capacitor C10 to Vout. Resonant inductor L1 and leakage inductances Lst, Ls2, magnetized by currents Isw1,2 and Isw3,4 are flowing from Vin to Vout (the description of currents Isw1,2 and Isw3,4 as flowing 'through' transformer TR1 is a common way of describing a simplified transformer coupled circuitry, specifically if the transformation ratio is 1:1) FIGS. 4A-4D and 5A-5D which are wave forms in the time-domain of current through and voltage adross switching devices at both sides of a converter and simplified illustrations of switching timing diagrams of control signals at the gate terminals of switching devices of a converter. Substantially when transistors SW1 and SW3 are conducting (that is are switched ON), transistors SW2 and SW4 are gated OFF. Capacitor Csw1 of transistor SW1 is then charged to 0 volts, and capacitor Csw2 to Vin. Capacitor Csw3 is charged to 0 volts, and capacitor Csw4 to Vout. FIGS. 4B and 4D present the voltages VSW1,2 at point 1 and VSW3,4 at point Switching is done in roll-off mode signals and not
in roll-on mode signals. With respect to the momentarily values of ISW1,2 and ISW3,4 (FIGS. 4A and 4C respectively) the switching schemes of FIGS. 5A to 5D present the switching ON or OFF of VGSW1-VGSW4 in each step of the various steps described above with respect to FIGS. 3A-3F).
Regarding claim 4, Lev discloses the voltage converter system of claim 1, wherein the normalized switching functions (switching timing schemes/gating) define switching sequences (switching timing/gating) for the two or more AHB converter circuits (first & second stages), and wherein the one or more controllers (36) are configured to actuate the switches (SW1-SW4) of the two or more AHB converter circuits (first & second stages) according to the switching sequences (switching timing/gating) (Fig. 1, 3-8, para. [0033]-[0035], [0041]-[0053]: When switching assemblies SW1 and SW3 are conducting (that is are switched ON), switching assemblies SW2 and SW4 are gated
OFF After the switching assembly SW1 is gated OFF by control signal VGSW1, current ISW1,2 begins to charge capacitors CSW1 and CSW2. Because the initial voltage on capacitor CSW1 is substantially zero, the mode of the switching is substantially ZVS, because the switching of switching assembly SW1 is done when the voltage across its terminals is substantially zero. Because the shape of the current ISW1,2 is sine, and the value of the current is minimum (efficient for recharge of capacitors CSW1, CSW2), the implemented mode might be named ZVS Switching timing schemes of VGSW1-VGSW4 are presented in FIGS. 5A to 5D. The switching is done in roll-off mode
signals and not in roll-on mode signals. With respect to the momentarily values of ISW1,2 and ISW3,4 (FIGS. 4A and 4C respectively) the switching schemes of FIGS. 5A to 5D present the switching ON or OFF of VGSW1-VGSW4 in each step of the various steps described above with respect to FIGS. 3A-3F).
Regarding claim 5, Lev discloses the voltage converter system of claim 4, wherein the switching sequences (switching timing/gating) are represented in permutation matrices (with respect to switching times T1-T15) (Fig. 1, 3-8, para. [0037], [0041]-[0053]: At time t13 SW4 is switched off and in accordance with the direction of current ISW3,4, recharges Csw3 and Csw4 until Vsw 3-4 reaches, during transition time, maximum voltage between t13 to t14. The switching conditions are ZVS and ZCS, similarly to the previous stages. Substantially with the conditions satisfying ZVC and ZCS at SW4. The recharge time of the capacitors Is a transition time and it finishes when diode DSW3 is
turned ON (see t14, FIGS. 4A-5D). After it, by means of control signal VGSW3 switching assembly SW3 Is turned ON, at time t15. at the end of this stage the circuit is ready to arrive at the initial state, as described above, at the end of the cycle Switching scheme described above begins at time t2 in FIGS. 4A-4D and 5A-5D Switching schemes of FIGS. 5A to 5D present the switching ON or OFF of VGSW1- VGSW4 in each step of the various steps described above with respect to FIGS. 3A-3F...t1-switching assembly SW1 is turned ON (FIG.3B). The transition time must be completed first t2-switching assembly SW1 is gated OFF t3-switching assembly SW1 and SW2 is turned OFF. The transition time is t2-t3 must be completed ..t4-switching assembly SW2 is gated ON...t5-switching assembly SW2 is turned ON. The current Isw3-4 changes polarity /..t6-switching assembly SW3 is gated OFF...t7-switching assembly SW3 is turned OFF t8-SW4 is turned ON .t9-switching assembly SW2 is turned FF..t10-switching assembly SW2 is turned ON).
Regarding claim 6, Lev discloses the voltage converter system of claim 4, wherein the one or more switching sequences (switching timing/gating) for the two or more AHB converter circuits (first & second stages) are defined by duty cycles for switches (ON times of SW1-SW4) of the two or more AHB converter circuits (first & second stages), and by adjustable phase shifts (phase shift between switching events for the switches (SW1-SW4) (Fig. 1, 3, para. [0053], [0054]: FIG. 4A to FIG. 5D, the amplitudes of the resonant tank comprising inductance L1 and capacitance C1, currents ISW1,2,3,4 and the value of output voltage Vout may vary according to the variation of frequency/time of the cycle period. This is one of the embodiments for regulation of the values of the currents ISW1,2,3,4 and the voltage Vout. It should be noted that graphs of FIGS. 4A-5D reflect the values related to the chosen phase difference between the voltages of the
input (primary) stage, i.e. VSW1,2 and the output (secondary) stage, i.e., VSW3,4. The time between t2 to t6. is the phase shift Related to the period (T). the phase is Dynamic range of change of phase from zero to may be divided to three main sub-regions, denoted I, Il and III in FIG. 6. From a phase value of substantially zero to phase of approximately 0.2 (sub-region I) no control of Pout by means of phase shift changes is done).
Regarding claim 8, Lev discloses the voltage converter system of claim 1, further comprising one or more sensors (function of controller 36,VREF-AC, VREF-DC, V-OUT-Feedback, ) deployed in the two or more AHB converter circuits (first & second stages) to measure electrical characteristics of components (voltages at points 1-4, currents I-SW-1,2, I-SW-3,4) of the two or more AHB converter circuits (first &second stages) (Fig. 1, 3-8, para. [0029]-[0036]: Controller 36 may further receive VREF AC representing actual voltage on the input terminals of converter 20; VREF DC to provide reference for the desired DC voltage and VFB OUT to provide feedback for the operation of converter 20 by providing voltage from the output terminals of converter 20. FIGS. 3A-3F which are partial schematic illustrations of a converter 10 according to embodiments of the present invention with indications of the current flow in branches of the converter in various steps of the working cycle. Attention is also made to FIG. 3A1 which depicts in more details optional topology and components comprised in switching assembly 11 Recharge process forms the roil-off of voltage in point 1, as shown in FIG. 3E. When diode DSW1 is turned ON it indicates the end of the recharge stage of CSW1. Only after that signal VGSW1 is applied to switching assembly SW1 to turn it ON);
wherein the one or more controllers (36) to control electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) are configured to: determine a switching mode (ZCS or ZVS switching mode), from a plurality of switching modes (ZCS, ZVS) under which the two or more AHB converter circuits (first & second stages) operate, based, at least in part, on feedback data (V-ref-DC, V-ref-AC, V-out, I-SW1,2, I-SW3,4) measured by the one or more sensors (via functionality of controller 36), the feedback data (V-ref-DC, V-ref-AC, V-out, I-SW1,2, I-SW3,4) representative of electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) (Fig. 1, 3-8, para. [0033]-[0037], [0042]-[0052]: After the switching assembly SW1 is gated OFF by control signal VGSW1,
current ISW1,2 begins to charge capacitors CSW1 and CSW2. Because the initial voltage on capacitor CSW1 is substantially zero, the mode of the switching is substantially ZVS, because the switching of switching assembly SW1 is done when the voltage across its terminals is substantially zero. Because the shape of the current ISW1,2 is sine, and the value of the current is minimum (efficient for recharge of capacitors CSW1, CSW2), the implemented mode might be named ZVS The switching timing schemes of VGSW1-VGSW4 are presented in FIGS. 5A to 5D. The switching is done in roll-off mode signals and not in roll-on mode signals. With respect to the
momentarily values of ISW1,2 and ISW3,4 (FIGS. 4A and 4C respectively) the switching schemes of FIGS. 5A to 5D present the switching ON or OFF of VGSW1-VGSW4 in each step of the various steps described above with respect to FIGS. 3A-3F).
Regarding claim 9, Lev discloses the voltage converter system of claim 8, wherein the one or more controllers (36) to control electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) are further configured to: derive expected electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) for a next period of operation (working cycle) of the two or more AHB converter circuits (first & second stages) based, at least in part, on the determined switching mode (ZCS or ZVS switching mode) for the two or more AHB converter circuits (first & second stages) and at least some of the feedback data (V-ref-DC, V-ref-AC, V-out, I-SW1,2, I-SW3,4) (Fig. 1, 3-8, para. [0030], [0035], [0037], [0042]-[0052]: Because the initial voltage on capacitor CSW3 is now
substantially zero, the switching mode is substantially purely ZVS. Because the value of current ISW3,4 is minimum (enough for efficient recharging of capacitors CSW3, CSW4), the implemented mode is substantially ZCS Implemented mode of this switching is substantially ZVS. Because the shape of the current as function of time is substantially a sine and is approaching crossing zero but not exactly zero-which is important to support charging of the capacitors, the mode of switching is substantially ZCS At time t13 SW4 is switched off and in accordance with the direction of current ISW3,4, recharges Csw3 and Csw4 until Vsw 3-4 reaches, during transition time, maximum voltage between t13 to t14. The switching conditions are ZVS and ZCS, similarly to the previous stages. Substantially with the conditions satisfying ZVC and ZCS at SW4).
Regarding claim 10, Lev discloses the voltage converter system of claim 9, wherein the one or more controllers (36) to control electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) are further configured to: determine duty cycle behavior (switch timing) and/or phase shift behavior (phase shift) for the switches (SW1-SW4) during the next period of operation (working cycle) of the two or more AHB converter circuits (first & second stages) based on the derived expected electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) (Fig. 1, 3, para. [0053], [0054], [0058]: Time between t2 to t6. is the phase shift Related to the period (T). the phase is /T. Variation of the phase may impose variations of the output voltage Vout, of the output power Pout and the currents ISW1,2 and ISW3,4. The dynamic range of change of phase from zero to may be divided to three main sub-regions, denoted I, II and III in FIG. 6. From a phase value of substantially zero to phase of approximately 0.2 (sub-region I) no control of Pout by means of phase shift changes is done Control of the phase of the converter of the present invention may be achieved by changing the switching timing scheme of switching assemblies 26 and 28 of the secondary stage of the converter 20 with respect to the timing of switching assemblies 22 and 24 of the primary stage of the converter. As much as the switching scheme of the secondary stage is delayed with respect to that of the primary stage the phase angle grows).
Regarding claim 11, Lev discloses the voltage converter system of claim 8, wherein the feedback data (V-ref-DC, V-ref-AC, V-out, I-SW1,2, I-SW3,4) representative of the electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) comprises one or more of: voltage levels (voltage at point 3 & point 4) at one or more capacitors (capacitors C3, C4, C0, C10) included in a circuit (L1, C1) comprising the two or more AHB converter circuits (first & second stages), or current (I-SW1,2) passing through an inductor (inductor L1) included in the circuit (L1, C1) comprising the two or more AHB
converter circuits (first & second stages) (Fig. 1, 3, para. [0028]-[0032]: The two stages may be coupled through transformer TR1 which may comprise magnetizing inductance represented by inductor M and leakage inductances represented by inductors Ls1, Ls2; resonant inductance L1 and resonant capacitor C1 Additionally converter 10 may comprise a return path between said first and said second stages connected between point "3", being a third central tap between capacitor C3 and capacitor C4 and point "4" being a fourth central tap between capacitor C9 and capacitor C10. the return path of resonance circuit may be connected directly between points "3" and "4" (not shown in FIG. 3A but exemplified in other drawings) or via a coupling transformer TR1 Resonant inductor L1 and leakage inductances Ls1, Ls2, magnetized by currents Isw1,2 and Isw3,4 are flowing from Vin to Vout (the description of currents Isw1,2 and Isw3,4 as flowing 'through' transformer TR1 is a common way of describing a simplified transformer coupled circuitry, specifically if the transformation ratio is 1:1)).
Regarding claim 12, Lev discloses a voltage conversion method (via two-way converter 10) (abstract, Fig. 1, 3, para. [0027], [0031]: FIG. 1B depicts converter 4 with a two-stage structure coupled by a transformer TR, where the power flows through the first stage (primary stage) and then through the second stage (secondary stage) Secondary stage may be electrically isolated from the primary stage by transformer TR which may also provide a step-down or step-up function of DC and AC output voltages. Both primary and secondary stages of converter 4 may comprise dual switching topology with switching means Q10 a-Q10 b and Q20 a-Q20 b respectively. FIG. 3A (and maybe applicable to converters presented in other drawings as well, with the required changes) converter 10 may comprise a first stage comprising capacitors C2, C3 and C4 and switching means SW1 and Sw2, all connected between two poles of Vin, denoted Vin+ and Vin- respectively) comprising: measuring (via controller 36) electrical characteristics of a voltage conversion system (two-way converter 10) comprising: two or more Active Half Bridge (AHB) converter circuits (first stage w/ SW1, SW2, C3, C4 & second stage w/ SW9, SW10, C9, C10), each of the two or more AHB converter circuits (first & second stages) connected to one or more windings of a transformer (coupling transformer TR1), with each AHB converter circuit (first & second stages) including one or more switches switching assemblies SW1, SW2, SW3, SW4) and one or more energy storage devices (capacitors C3, C4, C0, C10) (Fig. 1, 3, para. [0028]-[0032], [0042]: Secondary stage may substantially be a mirror picture of the primary stage: switching transistor T3, T4, diodes D3 and D4, parasitic or implemented capacitors C7 and C8; auxiliary capacitors C9, C10 and filtering capacitor C11. The two stages may be coupled through transformer TR1 which may comprise magnetizing inductance represented by inductor M and leakage inductances represented by inductors Ls1, Ls2; resonant inductance L1 and resonant capacitor C1 FIG. 3A converter 10 may comprise a first stage comprising capacitors C2, C3 and C4 and switching means SW1 and Sw2, all connected between two poles of Vin, denoted Vin+ and Vin- respectively. Switching means SW1 and Sw2 may be connected in a totem-pole arrangement with a central tap denoted "1". Converter 10 may comprise a second stage comprising switching
means SW3 and SW4 and capacitors C9, C10 and C111, all connected between two poles of Vout, denoted Vout+ and Vout- respectively. Switching means SW3 and SW4 may be connected in a totem-pole arrangement with a central tap denoted "2". Converter 10 may comprise a return path between said first and said second stages connected between point "3", being a third central tap between capacitor C3 and capacitor C4 and point "4" being a fourth central tap between capacitor C9 and capacitor C10. the return path of resonance circuit may be connected directly between points "3" and "4" or via a coupling transformer TR1. When switching assemblies
SW1 and SW3 are conducting (that is are switched ON), switching assemblies SW2 and SW4 are gated OFF; capacitor CSW1 of switching assembly SW1 is charged to 0 volts, capacitor CSW2 of switching assembly SW2 is charged to Vin, capacitor CSW3 of
switching assembly SW3 is charged to 0 volts, and capacitor C10 to Vout. Resonant inductor L1 and leakage inductances Ls1, Ls2, magnetized by currents Isw1,2 and Isw3,4 are flowing from Vin to Vout (the description of currents Isw1,2 and Isw3,4 as flowing 'through' transformer TR1 is a common way of describing a simplified transformer coupled circuitry, specifically if the transformation ratio is 1:1) FIGS. 4B and 4D present the voltages VSW1,2 at point 1 and VSW3,4 at point 2. Switching is done in roll-off mode signals and not in roll-on mode signals. With respect to the momentarily values of ISW1,2 and ISW3,4 (FIGS. 4A and 4C respectively) the switching schemes of FIGS. 5A to 5D present the switching ON or OFF of VGSW1-VGSW4 in each step of the various steps described above with respect to FIGS. 3A-3F); and one or more controllers (controller 36) coupled to the two or more AHB converter circuits (first & second stages) (Fig.1, 3, para. [0030]-[0033], [0041], [0042]: Assembly SWx may be any other appropriate device and circuitry. The control terminal denoted VgSWx is the control terminal through which switching assembly SWx may be turned (or gated) ON or OFF by a control circuitry 36 (FIG. 2B). FIGS. 3A-3F are shown without a control unit, such as controller 36 of FIG. 2 Controller 36, may be used to control the operation of
converter 10 by means of gating its switching devices SW1-SW4 ON or OFF at the desired timing When switching assemblies SW1 and SW3 are conducting (that is are switched ON), switching assemblies SW2 and SW4 are gated OFF; capacitor CSW1 of switching assembly SW1 is charged to 0 volts, capacitor CSW2 of switching assembly SW2 is charged to Vin, capacitor CSW3 of switching assembly SW3 is charged to 0 volts, and capacitor C10 to Vout FIG. 3B shows the next step in the sequence of four steps. After the switching assembly SW1 is gated OFF by control signal VGSW1, current ISW1,2 begins to charge capacitors CSW1 and CSW2. Because the initial voltage on capacitor CSW1 is substantially zero, the mode of the switching is substantially ZVS, because the switching of switching assembly SW1 is done when the voltage across its terminals is substantially zero); and controlling, using the one or more controllers (36), electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) according to normalized switching functions (switching timing schemes/gating) representing switching states of switches (ON, OFF via gates of SW1-SW4) of the two or more AHB converter circuits (first & second stages) (Fig. 1, 3, para. [0030]-[0033], [0041], [0042]: Assembly SWx may be any other appropriate device and circuitry.
The control terminal denoted VgSWx is the control terminal through which switching assembly SWx may be turned (or gated) ON or OFF by a control circuitry 36 (FIG. 2B). FIGS. 3A-3F are shown without a control unit, such as controller 36 of FIG. 2.. Controller 36, may be used to control the operation of converter 10 by means of gating its switching devices SW1-SW4 ON or OFF at the desired timing. When switching assemblies SW1 and SW3 are conducting (that is are switched ON), switching assemblies SW2 and SW4 are gated OFF; capacitor CSW1 of switching assembly SW1 is charged to 0 volts, capacitor CSW2 of switching assembly SW2 is charged to Vin,
capacitor CSW3 of switching assembly SW3 is charged to 0 volts, and capacitor C10 to Vout, FIG. 3B shows the next step in the sequence of four steps. After the switching assembly SW1 is gated OFF by control signal VGSW1, current ISW1,2 begins to charge capacitors CSW1 and CSW2. Because the initial voltage on capacitor CSW1 is substantially zero, the mode of the switching is substantially ZVS, because the switching of switching assembly SW1 is done when the voltage across its terminals is substantially zero).
Regarding claim 13, Lev discloses the method of claim 12, wherein controlling the electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) comprises: determining a switching mode (ZCS or ZVS switching mode), from a plurality of switching modes (ZCS or ZVS switching mode) under which the two or more AHB
converter circuits (first & second stages) operate, based, at least in part, on feedback data (V-ref-DC, V-ref-AC, V-out, I-SW1,2, I-SW3,4) measured by one or more sensors (functionality of controller 36), the feedback data (V-ref-DC, V-ref-AC, V-out, I-SW1,2, I-SW3,4) representative of the measured electrical characteristics behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) Fig. 1, 3-8, para. [0033]-[0037], [0042]-[0052]: After the switching assembly SW1 is gated OFF by control signal VGSW1, current ISW1,2 begins to charge capacitors CSW1 and CSW2. Because the initial
voltage on capacitor CSW1 is substantially zero, the mode of the switching is substantially ZVS, because the switching of switching assembly SW1 is done when the voltage across its terminals is substantially zero. Because the shape of the current ISW1,2 is sine, and the value of the current is minimum (efficient for recharge of capacitors CSW1, CSW2), the implemented mode might be named ZVS Switching timing schemes of VGSW1-VGSW4 are presented in FIGS. 5A to 5D. The switching is done in roll-off mode signals and not in roll-on mode signals. With respect to the momentarily values of ISW1,2 and ISW3,4 (FIGS. 4A and 4C respectively) the switching
schemes of FIGS. 5A to 5D present the switching ON or OFF of VGSW1-VGSW4 in each step of the various steps described above with respect to FIGS. 3A-3F).
Regarding claim 14, Lev discloses the method of claim 13, wherein controlling the electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) further comprises: deriving expected electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) for a next period of operation (working cycle) of the two or more AHB converter circuits (first & second stages) based, at least in part, on the determined switching mode (ZCS or ZVS switching mode) for the two or more AHB converter
circuits (first & second stages) and at least some of the feedback data (V-ref-DC, V-ref-AC, V-out, I-SW1,2, I-SW3,4) Fig. 1, 3-8, para. [0030], [0035], [0037], [0042]-[0052]: Because the Initial voltage on capacitor CSW3 is now substantially zero, the switching mode is substantially purely ZVS. Because the value of current ISW3,4 is minimum (enough for efficient recharging of capacitors CSW3, CSW4), the implemented mode is substantially ZCS Implemented mode of this switching is substantially ZVS. Because the shape of the current as function of time is substantially a sine and is approaching crossing zero but not exactly zero-which is important to support charging of the capacitors, the mode of switching is substantially ZCS, At time t13 SW4 is switched off and in accordance with the direction of current ISW3,4, recharges Csw3 and Csw4 until Vsw 3-4 reaches, during transition time, maximum voltage between t13 to t14: The switching conditions are ZVS and ZCS, similarly to the previous stages, Substantially with the conditions satisfying ZVC and ZCS at SW4).
Regarding claim 15, Lev discloses the method of claim 14, wherein controlling the electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) further comprises: determining duty cycle behavior (switch timing) and/or phase shift behavior (phase shift) for the switches (SW1-SW4) during the next period of operation (working cycle) of the two or more AHB converter circuits (first & second stages) based on the derived expected electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) (Fig. 1, 3, para. [0053], [0054], [0058]: Time between t2 to t6. is the phase shift Related to the period (T). the phase is /T. Variation of the phase may impose variations of the output voltage Vout, of the output power Pout and the currents ISW1,2 and
ISW3,4. The dynamic range of change of phase from zero to may be divided to three main sub-regions, denoted I, Il and III in FIG. 6. From a phase value of substantially zero to phase of approximately 0.2 (sub-region I) no control of Pout by means of phase shift changes is done Control of the phase of the converter of the present invention may be achieved by changing the switching timing scheme of switching assemblies 26 and 28 of the secondary stage of the converter 20 with respect to the timing of switching assemblies 22 and 24 of the primary stage of the converter. As much as the switching scheme of the secondary stage is delayed with respect to that of the primary stage the phase angle grows).
Regarding claim 16, Lev discloses the method of claim 13, wherein the feedback data (V-ref-DC, V-ref-AC, V-out, I-SW1,2, I-SW3,4) representative of the electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) comprises one or more of: voltage levels (voltage at point 3 & point 4) at one or more capacitors (capacitors C3, C4, C0, C10) included in a circuit (L1,C1) comprising the two or more AHB converter circuits (first & second stages), or current (current Isw1,2) passing through an inductor (inductor L1) included in the circuit (L1, C1) comprising the two or more AHB converter circuits (first & second stages) (Fig. 1, 3, para. [0028]-[0032]: The two stages may be coupled through transformer TR1 which may comprise magnetizing inductance represented by inductor M and leakage inductances represented by inductors Ls1, Ls2; resonant inductance L1 and resonant capacitor C1 Additionally converter 10 may comprise a return path between said first and said second stages connected between point "3", being a third central tap between capacitor C3 and capacitor C4 and point "4" being a fourth central tap between capacitor C9 and capacitor C10. the return path of resonance circuit may be connected directly between points "3" and "4" (not shown In FIG. 3A but exemplified in other drawings) or via a coupling transformer TR1.. Resonant inductor L1 and leakage inductances Ls1, Ls2, magnetized by currents Isw1,2 and Isw3,4 are flowing from Vin to Vout (the description of currents Isw1,2 and Isw3,4 as flowing 'through' transformer TR1 is a common way of describing a simplified transformer coupled circuitry, specifically if the transformation ratio is 1:1)).
Regarding claim 17, Lev discloses the method of claim 12, wherein the two or more AHB converter circuits (first & second stages) implement a dual active half bridge DAHB converter circuit (two-way converter 10 with first & second stages) with a primary side (first stage w/ SW1, SW2, C3, C4) and a secondary side (second stage w/ SW9, SW10, C9, C10) separated from the primary side (first stage) by the transformer (coupling transformer TR1), the primary side (left/first stage side) comprising two primary side capacitors (capacitors C3, C4), two primary side controllable switching devices (switching assemblies SW1, SW2), and the secondary side (second stage) comprising two secondary side capacitors (capacitors C9, C10), and two secondary side switching devices (switching assemblies SW3, SW4) (Fig. 1, 3, para. [0028]-[0032]: Secondary stage may substantially be a mirror picture of the primary stage: switching transistor T3, T4, diodes D3 and D4, parasitic or implemented capacitors C7 and C8; auxiliary capacitors C9, C10 and filtering capacitor C11. The two stages may be coupled through transformer TR1 which may comprise magnetizing inductance represented by inductor M and leakage inductances represented by inductors Ls1, Ls2; resonant inductance L1 and resonant capacitor C1 FIG. 3A converter 10 may comprise a first stage comprising capacitors C2, C3 and C4 and switching means SW1 and Sw2, all connected between two poles of Vin, denoted Vin+ and Vin- respectively. Switching means SW1 and Sw2 may be connected in a totem-pole arrangement with a central tap denoted "1". Converter 10 may comprise a second stage comprising switching means SW3 and SW4 and capacitors C9, C10 and C111, all connected between two poles of Vout, denoted Vout+ and Vout- respectively. Switching means SW3 and SW4 may be connected in a totem-pole arrangement with a central tap denoted "2" Converter 10 may comprise a return path between said first and said second stages connected between point "3", being a third central tap between capacitor C3 and capacitor C4 and point "4" being a fourth central tap between capacitor C9 and capacitor C10. the return path of resonance circuit may be connected directly between points "3" and "4" or via a coupling transformer TR1 When switching assemblies SW1 and SW3 are conducting (that is are switched ON), switching assemblies SW2 and SW4 are gated OFF; capacitor CSW1 of switching assembly SW1 is charged to 0 volts, capacitor CSW2 of switching assembly SW2 is charged to Vin, capacitor CSW3 of switching assembly SW3 is charged to 0 volts, and capacitor C10 to Vout. Resonant inductor L1 and leakage inductances Ls1, Ls2, magnetized by currents Isw1,2 and Isw3,4 are flowing from Vin to Vout (the description of currents Isw1,2 and Isw3,4 as flowing 'through' transformer TR1 is a common way of describing a simplified transformer coupled circuitry, specifically if the
transformation ratio is 1:1)).
Regarding claim 18, Lev discloses the method of claim 12, wherein the normalized switching functions (switching timing schemes/gating) define switching sequences (switching timing/gating) for the two or more AHB converter circuits (first & second stages), and wherein controlling the electrical behavior (current flow Isw1,2, Isw3,4 & output voltage V-OUT, via gating SW1-SW4) of the two or more AHB converter circuits (first & second stages) further comprises: actuating the switches (SW1-SW4) of the two or more AHB converter circuits (first.& second stages) according to the switching sequences (switching timing/gating) (Fig. 1, 3-8, para. [0033]-[0035], [0041]-[0053]:
When switching assemblies SW1 and SW3 are conducting (that is are switched ON), switching assemblies SW2 and SW4 are gated OFF After the switching assembly SW1 is gated OFF by control signal VGSW1, current ISW1,2 begins to charge capacitors CSW1 and CSW2. Because the initial voltage on capacitor CSW1 is substantially zero, the mode of the switching is substantially ZVS, because the switching of switching assembly SW1 is done when the voltage across its terminals is substantially zero. Because the shape of the current ISW1,2 is sine, and the value of the current is minimum (efficient for recharge of capacitors CSW1, CSW2), the implemented mode might be named ZVS The switching timing schemes of VGSW1-VGSW4 are presented in FIGS. 5A to 5D. The switching is done in roll-off mode signals and not in roll-on mode signals. With respect to the momentarily values of ISW1,2 and ISW3,4 (FIGS. 4A and 4C respectively) the switching schemes of FIGS. 5A to 5D present the switching ON or OFF of VGSW1-VGSW4 in each step of the various steps described above with respect to FIGS. 3A-3F).
Regarding claim 19, Lev discloses the method of claim 18, wherein the switching sequences (switching timing/gating) are represented in permutation matrices (with respect to switching times T1-T15) (Fig. 1, 3-8, para. [0033]-[0037], [0041]-[0053]: At time t13 SW4 is switched off and in accordance with the direction of current ISW3,4, recharges Csw3 and Csw4 until Vsw 3-4 reaches, during transition time, maximum voltage between t13 to t14. The switching conditions are ZVS and ZCS, similarly to the previous stages. Substantially with the conditions satisfying ZVC and ZCS at SW4. The recharge time of the capacitors is a transition time and it finishes when diode DSW3 is
turned ON (see t14, FIGS. 4A-5D). After it, by means of control signal VGSW3 switching assembly SW3 is turned ON, at time t15. at the end of this stage the circuit is ready to arrive at the initial state, as described above, at the end of the cycle Switching scheme described above begins at time t2 in FIGS. 4A-4D and 5A-5D Switching schemes of FIGS. 5A to 5D present the switching ON or OFF of VGSW1-VGSW4 in each step of the various steps described above with respect to FIGS. 3A-3F...t1-switching assembly SW1 is turned ON (FIG.3B). The transition time must be completed first. t2-switching assembly SW1 is gated ...t3-switching assembly SW1 and SW2 is
turned OFF. The transition time is t2-t3 must be completed t4-switching assembly SW2 is gated ON t5-switching assembly SW2 is turned ON. The current Isw3-4 changes polarity t6-switching assembly SW3 is gated OFF t7-switching assembly SW3 is turned
OFF...t8-SW4 is turned ON...t9-switching assembly SW2 is turned OFF..t10-switching assembly SW2 is turned ON).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lev (US 2009/0034299 A1) in view of Rodriguez et al. (US 2018/0241322 A1) (hereinafter Rodriguez).
Regarding claim 7, Lev discloses the voltage converter system of claim 1. Lev fails to disclose wherein each of the two or more AHB converter circuits (first & second stages) is represented as two half bridge converter circuits (first stage w/ SW1, SW2, C3, C4 & second stage w/ SW9, SW10, C9, C10) and a central dual active half bridge separating the two half bridge converter circuits (first & second stages), with the central dual active half bridge configured to transfer power across a transformer of the central dual active half bridge. However, Rodriguez discloses wherein each of the two or more AHB converter circuits (300, 304) is represented as two half bridge converter circuits
(half bridge inverter 300, half bridge cylindered 304) and a central dual active half bridge (active filter 306 includes half-bridge converter) separating the two half bridge converter circuits (300, 304), with the central dual active half bridge (306) configured to transfer power across a transformer (302) of the central dual active half bridge (306) (Fig. 8-13, para. [0070], [0078], [0091], [0092]: FIG. 8, the DC-AC inverter 300 of the three-port inverter 800 illustratively includes a full-bridge converter, and each of the cycloconverter 304 and the active filter 306 includes a half-bridge converter FIG. 10, the DC-AC inverter 300 of the three-port inverter 1000 illustratively includes a full-
bridge converter, and each of the cycloconverter 304 and the active filter 306 includes a half-bridge converter. FIG. 13, the DC-AC inverter 300 of the inverter 1300 is decoupled from the cycloconverter 304 by virtue of the active filter 306 DC-AC inverter 300 is electrically coupled to the first winding 414 of the transformer 302 (at terminals 750, 752) and the active filter 306 is electrically coupled to the second winding 416 of the transformer 302 (at terminals 754, 756)). Since both references are directed toward power converters, it would have been obvious to one of having ordinary skill in the art at the time of filing to incorporate wherein each of the two or more AHB converter circuits (300, 304) is represented as two half bridge converter circuits (half bridge inverter 300, half bridge cylindered 304) and a central dual active half bridge (active filter 306 includes half-bridge converter) separating the two half bridge converter circuits (300, 304), with the central dual active half bridge (306) configured to transfer power across a transformer (302) of the central dual active half bridge (306) of Rodriguez with the system of Lev, since such a modification would result in a system with improved harmonic regulation for reduction/eliminate of voltage ripple. (See Rodriguez: para. [0099]).
Regarding claim 20, Lev discloses the method of claim 12. Lev fails to disclose wherein each of the two or more AHB converter circuits (first & second stages) is represented as two half bridge converter circuits (first stage w/ SW1, SW2, C3, C4 & second stage w/ SW9, SW10, C9, C10) and a central dual active half bridge separating the two half bridge converter circuits (first & second stages), with the central dual active half bridge configured to transfer power across a transformer of the central dual active half bridge. However, Rodriguez discloses wherein each of the two or more AHB converter circuits (300, 304) is represented as two half bridge converter circuits (half bridge inverter
300, half bridge cylindered 304) and a central dual active half bridge (active filter 306 includes half-bridge converter) separating the two half bridge converter circuits (300, 304), with the central dual active half bridge (306) configured to transfer power across a transformer (302) of the central dual active half bridge (306) (Fig. 8-13, para. [0070], [0078], [0091], [0092]: FIG. 8, the DC-AC inverter 300 of the three-port inverter 800 illustratively includes a full-bridge converter, and each of the cycloconverter 304 and the active filter 306 includes a half-bridge converter. FIG. 10, the DC-AC inverter 300 of the three-port inverter 1000 illustratively includes a full-bridge converter, and each of
the cycloconverter 304 and the active filter 306 includes a half-bridge converter, FIG. 13, the DC-AC inverter 300 of the inverter 1300 is decoupled from the cycloconverter 304 by virtue of the active filter 306, DC-AC inverter 300 is electrically coupled to the first winding 414 of the transformer 302 (at terminals 750, 752) and the active filter 306 is electrically coupled to the second winding 416 of the transformer 302 (at terminals 754, 756)). Since both references are directed toward power converters, it would have been obvious to one of ordinary skill in the art at the time of filing to incorporate wherein each of the two or more AHB converter circuits (300, 304) is represented as two half bridge converter circuits (half bridge inverter 300, half bridge cylindered 304) and a central dual active half bridge (active filter 306 includes half-bridge converter) separating the two half bridge converter circuits (300, 304), with the central dual active half bridge (306) configured to transfer power across a transformer (302) of the central dual active half bridge (306) of Rodriguez with the system of Lev, since such a modification would result in a system with improved harmonic regulation for reduction/eliminate of voltage ripple. (See Rodriguez: para. [0099]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jahns et al. (US 2025/0385618 A1) disclose a systems and methods for a three phase partial power processing inverter.
Examiner has cited particular columns, line numbers and/or paragraphs in the
references applied to the claims above for the convenience of the applicant. Although
the specified citations are representative of the teachings of the art and are applied to
specific limitations within the individual claim(s), other passages and figures may apply
as well.
Additionally, in the event that other prior art is provided and made of record by the
Examiner, as being relevant or pertinent to applicant's disclosure but not relied upon.
The references are provided for the convenience of the applicant.
The Examiner request that the references be considered in any subsequent amendments, as they are also representative of the art and may apply to the specific limitations of any newly amended claim(s).
It is respectfully requested from the applicant in preparing amendments or responses, to
fully consider the references in their entirety as potentially teaching all or part of the
claimed invention, as well as the context of the passage as taught by the prior art and/or
disclosed by the Examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7 AM - 10 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838
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