DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim(s) 2, 8, 14, 16, 18, 19 objected to because of the following informalities:
Claim 2 recites “the bridge generates a first interrupt that it transmits with the first and second characteristics to the management unit”. The examiner believes this is a typo. A suggested amendment to the claim is “the bridge generates a first interrupt that it transmits with the first characteristics and second characteristics to the management unit”. For examination purposes, the claim will be interpreted as suggested.
Claim 8 recites “the first interrupt transaction”. The examiner believes this is a typo. A suggested amendment to the claim is “the first interrupt
Claim 14 recites “the first interrupt transaction”. The examiner believes this is a typo. A suggested amendment to the claim is “the first interrupt
Claim 16 recites “the first write access transaction”. The examiner believes this is a typo. A suggested amendment to the claim is “the first write
Claim 18 recites “the second interrupt transaction”. The examiner believes this is a typo. A suggested amendment to the claim is “the second interrupt
Claim 19 recites “as a result of the transmission of the second interrupt transaction, the processing unit having received the second interrupt transaction”. The examiner believes this is a typo. A suggested amendment to the claim is “as a result of the transmission of the second interrupt .
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites “a resetting of the first or of the second transaction, a resetting of the microcontroller”. There is insufficient antecedent basis for this claim. A suggested amendment to the claim is “a resetting of the first write transaction, a resetting of a microcontroller”. For examination purposes, the claim will be interpreted as suggested.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, 13, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 20080016405 (“Kitahara”) in view of US Patent Application Publication No. 20070097871 (“Boyd”) and US Patent No. 6523140 (“Arndt”).
Regarding claim 1, Kitahara teaches
A bus error management method, comprising ([0042]: bus failure management)
storing one or a plurality of first characteristics of a first write transaction intended for a functional unit and transiting through a bridge; and (Fig. 1, [0032], [0039], [0065]: storing a function number for a write transaction intended for an IO card and transiting through a bridge)
in the presence of a bus error…: ([0042]: bus failure)
…one or a plurality of second characteristics linked to the error; ([0042]: the bridge generate an error message transaction ID in response to the bus failure)
generating, by the bridge, a first interrupt that it transmits with the first and second characteristics to a management unit; and ([0042]: the bridge adds the function number to the transaction ID and sends the error message to the IO control circuit)
generating, by the management unit, at least one second interrupt intended for a processing unit as a function of at least one of the first or second characteristics. ([0042], [0044], [0045]: based on the function number extracted from the transaction ID, signal a bus failure to the processor for the transaction)
Kitahara does not teach a bus error sent by the functional unit or storing one or a plurality of second characteristics linked to the error;
Boyd teaches
a bus error sent by the functional unit: ([0028]: bus error reported by an adapter)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine Boyd’s error reporting with Kitahara’s error detection.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination to allow for proper routing of error messages in multi-host systems with shared adapters (Boyd, [0006]).
Kitahara in view of Boyd does not teach storing one or a plurality of second characteristics linked to the error;
Arndt teaches
storing one or a plurality of second characteristics linked to the error; (Col. 4, Lines 25-35: store the tag number for a failed transaction on a bus)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine Arndt’s error storage with Kitahara in view of Boyd’s error detection.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination to help identify the specific device associated with the error (Arndt, Col. 3, Lines 35-55)
Regarding claim 3, Kitahara in view of Boyd and Arndst further teaches
wherein the processing unit executes a plurality of operating systems (Boyd, [0022], [0030]: CPU set executing multiple operating systems in a root node) and the second interrupt is intended for one of the plurality of operating systems as a function of at least one of the first or second characteristics. (Boyd, [0037], [0038]: error messages are routed to an operating system affected by the error based on the requestor ID in the error message)
Regarding claim 4, Kitahara in view of Boyd and Arndst further teaches
wherein the second interrupt is intended for one among a plurality of processing units as a function of at least one of the first or second characteristics. (Boyd, [0030], [0034]: error messages are routed to the CPU set of a root node affected by the error based on the requestor ID in the error message. There are multiple root nodes, each with a CPU set)
Regarding claim 5, Kitahara in view of Boyd and Arndst further teaches
wherein the first characteristics are stored in the bridge. (Kitahara, Fig. 1, [0032]: function number stored in the bridge)
Regarding claim 13, Kitahara in view of Boyd and Arndst further teaches
wherein the second characteristics comprise an identifier. (Kitahara, [0042]: transaction ID)
Regarding claim 19, Kitahara in view of Boyd and Arndst further teaches
wherein, as a result of the transmission of the second interrupt transaction, the processing unit having received the second interrupt transaction performs an action including at least one of a reconfiguring of the functional unit, a resetting of the first or of the second transaction (Kitahara, [0055]: the processor retries the transaction after recovering from the failure), a resetting of the microcontroller, or a writing of an error report.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 20080016405 (“Kitahara”) in view of US Patent Application Publication No. 20070097871 (“Boyd”) and Non-Patent Literature Microcontroller (“Wikipedia”)
Regarding claim 2, Kitahara teaches
…comprising at least one control unit (Fig. 1, [0032]: bus control), a bridge (Fig. 1, [0032]: bridge), a functional unit (Fig. 1, [0039]: IO card), and a management unit (Fig. 1, [0039]: IO control circuit)… being configured to:
store one or a plurality of first characteristics of a first write transaction intended for a functional unit and transiting through a bridge; and (Fig. 1, [0032], [0039], [0065]: storing a function number for a write transaction intended for an IO card and transiting through a bridge)
in the presence of a bus error…: ([0042]: bus failure)
the bridge generates a first interrupt that it transmits with the first and second characteristics to a management unit; and ([0042]: the bridge adds the function number to the transaction ID and sends the error message to the IO control circuit)
the management unit generates at least one second interrupt intended for a processing unit as a function of at least one of the first or second characteristics. ([0042], [0044], [0045]: based on the function number extracted from the transaction ID, signal a bus failure to the processor for the transaction)
Kitahara does not teach a bus error sent by the functional unit or A microcontroller
Boyd teaches
a bus error sent by the functional unit: ([0028]: bus error reported by an adapter)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine Boyd’s error reporting with Kitahara’s error detection.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination to allow for proper routing of error messages in multi-host systems with shared adapters (Boyd, [0006]).
Kitahara in view of Boyd does not teach A microcontroller
Wikipedia teaches
A microcontroller (Pg. 7: microcontroller)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to integrate Kitahara in view of Boyd’s system into Wikipedia’s microcontroller.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination to drastically reduce the number of chips and the amount of wiring and circuit board space that would be needed to produce equivalent systems using separate chips (Wikipedia, Pg. 7).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 20080016405 (“Kitahara”) in view of US Patent Application Publication No. 20070097871 (“Boyd”), US Patent No. 6523140 (“Arndt”) and US Patent No. 10915389 (“BeSerra”).
Regarding claim 6, Kitahara in view of Boyd and Arndst does not further teach the remaining limitations.
BeSerra teaches
wherein the second characteristics are stored in the bridge. (Col. 10, Lines 10-25: the root complex stores an error message header from an error message into a register in the root complex)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine BeSerra’s error storage with Kitahara in view of Boyd and Arndst’s error detection.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination to enable identify of a device that requires error remediation (BeSerra, Col. 2, Lines 30-55).
Claim(s) 7, 9, 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 20080016405 (“Kitahara”) in view of US Patent Application Publication No. 20070097871 (“Boyd”), US Patent No. 6523140 (“Arndt”) and US Patent No. 6311296 (“Congdon”).
Regarding claim 7, Kitahara in view of Boyd and Arndst further teaches
wherein the management unit stores the first…characteristics (Kitahara, [0039]: function number stored in the IO control circuit)
Kitahara in view of Boyd and Arndst does not further teach wherein the management unit stores the…second characteristics
Congdon teaches
wherein the management unit stores the…second characteristics (Col. 6, Lines 35-60, Col. 7, Lines 55-65: store error conditions in the PCI management card)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine Congdon’s error storage with Kitahara’s error detection.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination to assist in diagnosing errors (Congdon, Col. 8, Lines 10-55).
Regarding claim 9, Kitahara in view of Boyd, Arndst, and Congdon further teaches
wherein the first and second characteristics are stored in one or a plurality of registers of the management unit. (Kitahara, [0039]: function number stored in a register of the IO control circuit; Congdon, Col. 6, Lines 35-60, Col. 7, Lines 55-65: store error conditions in registers of the PCI management card that also store configuration information)
Regarding claim 14, Kitahara in view of Boyd, Arndst, and Congdon further teaches
wherein one of the registers is configured to store a value representative of the presence of a transmission of the first interrupt transaction. (Kitahara, [0042]: in response to the error message, the corresponding flag is set in the closing circuit)
Regarding claim 15, Kitahara in view of Boyd, Arndst, and Congdon further teaches
wherein one of the registers is configured to store the first characteristics and the second characteristics. (Congdon, Col. 6, Lines 35-60, Col. 7, Lines 55-65: store error conditions in registers of the PCI management card that also store configuration information)
Regarding claim 16, Kitahara in view of Boyd, Arndst, and Congdon further teaches
wherein one of the registers is configured to store an address linked to the first write access transaction. (Kitahara, [0039], [0065]: the function number is an address linked to the write transaction and is stored in a register of the IO control circuit)
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 20080016405 (“Kitahara”) in view of US Patent Application Publication No. 20070097871 (“Boyd”), US Patent No. 6523140 (“Arndt”) and US Patent No. 6453429 (“Sadana”).
Regarding claim 10, Kitahara in view of Boyd and Arndst does not further teach the remaining limitations.
Sadana teaches
wherein the first characteristics comprise an access restriction level. (Col. 3, Lines 35-45, Col. 5, Lines 40-65: protected memory definition registers indicate whether a transaction can be performed on an address based on the master id)
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine Sadana’s protection-based error detection with Kitahara in view of Boyd and Arndst’s error detection.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination because unprotected memory accesses by errant adapters can lead to propagation of errors (Sadana, Col. 2, Lines 1-15).
Regarding claim 11, Kitahara in view of Boyd, Arndst, and Sadana further teaches
wherein the second characteristics comprise an addressing mode restriction level (Sadana, Col. 5, Lines 40-65, Col. 6, Lines 1-15: store an indicator of unauthorized access of an address)
Regarding claim 12, Kitahara in view of Boyd, Arndst, and Sadana further teaches
wherein the second characteristics comprise an address. (Sadana, Col. 6, Lines 1-15: store the address of the unauthorized access)
Allowable Subject Matter
Claim(s) 8, 17, 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art of record, either alone or when combined, teaches or suggests wherein the management unit stores the first and second characteristics after the transmission of the first interrupt transaction and of the first and second characteristics by the bridge as recited in claim(s) 8.
None of the prior art of record, either alone or when combined, teaches or suggests wherein the management unit stores the first and second characteristics in registers having an access restriction level similar to an access restriction level associated with the first characteristics as recited in claim(s) 17.
None of the prior art of record, either alone or when combined, teaches or suggests wherein the management unit transmits the second interrupt transaction to the processing unit having an access restriction level similar to the access restriction level associated with the first characteristics as recited in claim(s) 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication No. 20170091013: a root complex has error registers for counting errors to determine when to send interrupts
US Patent Application Publication No. 20070011500: a bridge detects a bus error and sends a system management interrupt, which triggers a system management interrupt handler. The system management interrupt handler then triggers an interrupt of a PCI error handler.
US Patent Application Publication No. 20130332925: a bridge detects a bus error and notifies an interrupt controller, which interrupts the processor
US Patent Application Publication No. 20080148104: a bridge stores transaction information for a pending transaction. In response to a bus error, the transaction information is used to determine the device responsible for the transaction, and an interrupt is sent to the OS.
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/A.L./Examiner, Art Unit 2113
/MARC DUNCAN/Primary Examiner, Art Unit 2113