DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,6-11,13-16 and 19-20 are rejected under 35 U.S.C. 102(a)(1)as being by Oi et al. (Oi) (Patent NO. US 6,198,384)
Regarding Claim 1 Oi discloses: an electronic device, [Fig.3] comprising: a data port [Fig.3, item 17 and 18] for coupling the electronic device to an external device; [Fig.3, as shown, 1st connector connects to a digital VTR and the second connector connects to a color page printer] a data interface circuit coupled to the data port,[Fig.3, item 19, an interface circuit 19 having an interface (I/F) controller 13, two regulators 14, 15, a diode 16, and a switch SW. col.4,lines 5-10] the data interface circuit configured to receive a first power signal provided based on an interface power control signal and exchange data with the external device coupled via the data port; [col.4, lines 35-50, Fig.7 col.6 lines 49-56, FIG. 7 is a flowchart illustrating the operation of the I/F controller 13. The I/F controller 13 repeats step 41 until, for example, a high first trigger signal SGl is received. If the I/F controller 13 determines that the first trigger signal SGl is high, the I/F controller 13 proceeds to step 42 and checks whether isochronous transmission is being performed. Steps 41 and 42 are repeated as long as isochronous transmission is being performed. That is, steps 41 and 42 are repeated until the mode detection signal SG5 goes low.] and a power controller coupled to the data interface circuit, the power controller configured to receive a second power signal, monitor an interface operation state of the data interface circuit, and generate the interface power control signal based on the interface operation state, wherein the second power signal is distinct from the first power signal. [col.4, lines 35-50, Fig.7, col.6, line 55-col.6, line 7, When the mode detection signal SG5 falls, the I/F controller 13 proceeds to step 43 and checks whether the bus is in an idle state. Steps 41 to 43 are repeated as long as the bus is in a busy state. That is, steps 41 to 43 are repeated until the state detection signal SG4 falls. When the state detection signal SG4 falls, the I/F controller 13 proceeds to step 44 and provides a high control signal SG3 to the switch SW to close the switch SW. If the power switch of the personal computer 1 is turned on during the isochronous transmission mode, the I/F controller 13 keeps the control signal SG3 low until the isochronous transmission mode is finished and causes the control signal SG3 to rise when the idle state begins. The switch SW is closed when the control signal SG3 becomes high. This supplies the regulator 15 with the system power VDD sys from the system power circuit 11 via the regulator 14 and the switch SW. Thus, the I/F controller 13 closes the switch SW when data transmission cannot be affected.]
Regarding Claim 6 Oi discloses: the interface operation state includes one of: a first low power state in which no communication bus is mechanically coupled to the data port or a communication bus is mechanically coupled to the data port without being connecting to the external device; and a second low power state in which the communication bus is mechanically coupled to the data port with the external device and no data has been exchanged via the data port for at least a predefined time duration. [col.4, lines 34-49, When the power switch of the personal computer 1 is turned on, the host controller 12 provides the I/F controller 13 with a high first trigger signal SG1 (FIG. 6). If an OFF command of the power switch of the personal computer 1 is issued (when a disconnection process, or off sequence, is commenced), the host controller 12 provides the I/F controller 13 with a high second trigger signal SG2. The high trigger signals SG1, SG2 fall when the supply of the system power VDDsys to the host controller 12 is stopped. The I/F controller 13 provides a control signal SG3 to the switch SW in accordance with the first and second trigger signals SG1, SG2. When the control signal SG3 is high, the switch SW is closed. This supplies the regulator 15 with the system power VDDsys via the regulator 14, the switch SW, and the diode 16. The operation power VDDif from the regulator 15 is further supplied to the I/F controller 13. When computer is powered off and when computer is powered on the bus is idle]
Regarding Claim 7 Oi discloses: the power controller is configured to generate the interface power control signal based on the interface operation state by: in accordance with a determination that the data interface circuit has the first low power state or the second low power state, setting the interface power control signal to disable the first power signal from powering the data interface circuit. [col.4, lines 34-49, The I/F controller 13 provides a control signal SG3 to the switch SW in accordance with the first and second trigger signals SG1, SG2. When the control signal SG3 is high, the switch SW is closed. This supplies the regulator 15 with the system power VDDsys via the regulator 14, the switch SW, and the diode 16. The operation power VDDif from the regulator 15 is further supplied to the I/F controller 13. When computer is powered off and when computer is powered on the bus is idle]
Regarding Claim 8 Oi discloses: the interface operation state includes an active operation state in which the communication bus is mechanically coupled to the data port with the external device and data has been exchanged via the data port within a predefined time duration. [Fig.7, item 42 and 43, Isochronous period, col. 6, lines 6-15, data transmission mode, which include an isochronous transmission mode and an asynchronous transmission mode. The isochronous transmission mode is used for the transmission of image data formed by a large amount of data that requires continuity, such as dynamic images. Data is transmitted at predetermined time periods in the isochronous transmission. In the asynchronous transmission mode, data is transmitted during periods other than the isochronous transmission mode.]
Regarding Claim 9 Oi discloses: the power controller is configured to generate the interface power control signal based on the interface operation state by: in accordance with a determination that the data interface circuit has the active operation state, setting the interface power control signal to enable the first power signal to power the data interface circuit. [col.4, lines 34-49, The I/F controller 13 provides a control signal SG3 to the switch SW in accordance with the first and second trigger signals SG1, SG2. When the control signal SG3 is high, the switch SW is closed. This supplies the regulator 15 with the system power VDDsys via the regulator 14, the switch SW, and the diode 16. The operation power VDDif from the regulator 15 is further supplied to the I/F controller 13. When computer is powered off and when computer is powered on the bus is idle]
Regarding Claim 10 Oi discloses: the data port includes a first data port for receiving a first external device, the electronic device further comprising: one or more alternative ports coupled to the data interface circuit; [Fig.2 item 3-6 and Fig.3, items 17 and 18, Ports can utilized to connected external device, therefore can used as alternate port ] wherein the interface operation state is associated with the data interface circuit, the first data port, and the one or more alternative ports, and applied to generate the interface power control signal for controlling the first power signal provided to power the data interface circuit. [col.4, lines 34-49, The I/F controller 13 provides a control signal SG3 to the switch SW in accordance with the first and second trigger signals SG1, SG2. When the control signal SG3 is high, the switch SW is closed. This supplies the regulator 15 with the system power VDDsys via the regulator 14, the switch SW, and the diode 16. The operation power VDDif from the regulator 15 is further supplied to the I/F controller 13. When computer is powered off and when computer is powered on the bus is idle]
Regarding Claim 11 Oi discloses: the first data port and the one or more alternative ports have the same type of data port configured to communicate data in compliance with a first data communication protocol. [IEEE1394 standard interface ]
Regarding Claim 13 Oi discloses: when the electronic device is electrically coupled to mains electricity, the second power signal is enabled to power the power controller. [Fig.3, VDsys, system voltage/power]
Regarding Claim 14 Oi discloses: a switch component electrically coupled to a power source and the data interface circuit, [Fig.3, VDsys, system voltage/power] and the power controller is configured to control the switch component using the interface power control signal to provide the first power signal. [Fig.3, SW, col.2, lines 26-39, In a further aspect of the present invention, the method includes generating a first trigger signal indicating that the system power supply has gone on, closing the switch at a timing that does not affect the data transmission in accordance with the first trigger signal, generating a second trigger signal indicating that the system power supply has gone off, and opening the switch at a timing that does not affect the data transmission in accordance with the second trigger signal The present invention also provides an interface circuit for performing data transmission. The interface circuit includes an interface controller operated by at least a system power supply or an external power supply, and a switch connected between an interface controller and a system power circuit for conducting system power.]
Regarding Claim 15 Oi discloses: the power controller is configured to: disable the power source from powering the data interface circuit when no data has been exchanged via the data port for at least a predefined time duration, independently of whether a communication bus or the external device is coupled to the data port; and enable the power source to power the data interface circuit when data has been exchanged via the data port within the predefined time duration. . [col.4, lines 34-49, When the power switch of the personal computer 1 is turned on, the host controller 12 provides the I/F controller 13 with a high first trigger signal SG1 (FIG. 6). If an OFF command of the power switch of the personal computer 1 is issued (when a disconnection process, or off sequence, is commenced), the host controller 12 provides the I/F controller 13 with a high second trigger signal SG2. The high trigger signals SG1, SG2 fall when the supply of the system power VDDsys to the host controller 12 is stopped. The I/F controller 13 provides a control signal SG3 to the switch SW in accordance with the first and second trigger signals SG1, SG2. When the control signal SG3 is high, the switch SW is closed. This supplies the regulator 15 with the system power VDDsys via the regulator 14, the switch SW, and the diode 16. The operation power VDDif from the regulator 15 is further supplied to the I/F controller 13. When computer is powered off and when computer is powered on the bus is idle]
Claims 16 and 20 are is having similar limitations to that of the apparatus of claim 1. Accordingly, claims 16 and 20 are rejected under a similar rational as that of claim 1 above.
Claim 19 is having similar limitations to that of the apparatus of claim 14.Accordingly, claim 19 is rejected under a similar rational as that of claim 14 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Oi et al. (Oi) (Patent NO. US 6,198,384) in view of Nguyen (Pub No. US 2006/0265614) .
Regarding Claim 2 Oi does not teach the power controller includes a plurality of latches configured to hold one or more state signals corresponding to the interface operation state, before and while the first power signal is disabled based on the interface power control signal.
However, Nguyen teaches: the power controller includes a plurality of latches configured to hold one or more state signals corresponding to the interface operation state, before and while the first power signal is disabled based on the interface power control signal.[[0033], torage element, such as a latch, to store one or more bits indicating power state statuses of associated components of the computer system. For another embodiment of the present invention, the circuit of FIG. 3 may be redesigned to accept additional power state status signals associated with other components, the power to which is supplied by voltage regulator]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to store the power state in latches as taught by Nguyen in Oi’s system . Doing so would have resulted in reduced power consumption.
Claim 17 is having similar limitations to that of the apparatus of claim 2.Accordingly, claim 17 is rejected under a similar rational as that of claim 2 above.
Claim 4 rejected under 35 U.S.C. 103 as being unpatentable over Oi et al. (Oi) (Patent NO. US 6,198,384) in view of Wang et al. (Wang) (Pub NO. US 2025/0110913)
Regarding Claim 4 Oi does not teach the data port is configured to support data communication via a serial data bus, and the data interface circuit includes a redriver configured to amplify a data signal transmitted on the serial data bus or a retimer configured to compensate for an insertion loss of the serial data bus.
However, wang teaches: teach the data port is configured to support data communication via a serial data bus, and the data interface circuit includes a redriver configured to amplify a data signal transmitted on the serial data bus or a retimer configured to compensate for an insertion loss of the serial data bus.[[0002] interfaces in compliance with an industry bus standard, which specifies physical interfaces and protocols for connecting, data transferring and powering of hosts. This bus standard allows the application of retimers to extend the channel reach at a high data speed. A retimer is a mixed-signal device that is standard-aware and has an ability to fully recover the data, extract the embedded clock, and retransmit a fresh copy of the data using a clean clock. The redriver is an analog extension device designed to boost portions of a signal to counteract attenuation caused by signal propagation over a physical interconnect of a corresponding data link.]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use retimers and redriver as taught by Wang in Oi’s bus. A person with ordinary skill it the art would have been motivated to combine Wang and Oi to resets jitter, recover clocks (advantage of retimer) and reduce power consumption (advantage of redriver)
Claims 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Oi et al. (Oi) (Patent NO. US 6,198,384) in view of Lupon et al. (Lupon) (Pub No. US 2014/0281419)
Regarding Claim 5 Oi does not explicitly teach the data port is configured to support data communication via a serial data bus according to a peripheral component interconnect express (PCIe) protocol, a universal serial bus (USB) protocol, a high-definition multimedia interface (HMDI) protocol, a DisplayPort protocol, a Thunderbolt protocol, an inter-integrated circuit (I2C) protocol, or a serial advanced technology attachment (SATA) protocol.
However, subject matter if the claim is well known the art as taught by Lupon [Par. 30]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use different types of interface buses as taught by Lupon in Oi’s system to improve speed, device compatibility, and overall system efficiency.
Regarding Claim 12 Oi does not teach but Lupon teaches at least two of the first data port and the one or more alternative ports include different types of data ports configured to communicate data in compliance with two different data communication protocols. [Par. 30]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use different types of interface buses as taught by Lupon in Oi’s system to improve speed, device compatibility, and overall system efficiency.
Claims 3 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Oi et al. (Oi) (Patent NO. US 6,198,384) in view of Nguyen (Pub No. US 2006/0265614) further in view of Visanathan (Pub No. US 2014/0029700)
Regrading Claim 3 the combination of Oi and Nguyen does not teach the one or more state signals include one or more of: a plurality of filter coefficients applied in the data interface circuit; and a gain of an amplifier applied in the data interface circuit.
However, Visanathan teaches: the one or more state signals include one or more of: a plurality of filter coefficients applied in the data interface circuit; and a gain of an amplifier applied in the data interface circuit. [Abstract, phase mismatch estimates and the gain mismatch estimates to generate correction filter coefficients (h[N]) for a N tap correction filter (61). [0005] the output of mixer 5A is applied to the input of an adjustable gain amplifier]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use a filter coefficients and a adjustable gain amplifier of Visanathan in Oi’s system to improve flexibility of the data bus.
Claim 18 is having similar limitations to that of the apparatus of claim 3. Accordingly, claim 18 is rejected under a similar rational as that of claim 3 above.
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 6,487,175 B1 — "Control of power supply to subscribers in digital switch board with respect to data-communication calls"
a device for controlling power supply to subscribers in a digital subscriber-switch board, including a carrier-detection unit connected to a communication path to detect a carrier signal once a communication path is established, wherein the subscriber-line circuit is controlled to suspend power supply when the carrier-detection unit detects the carrier signal on the communication path. Power supply is later resumed based on monitoring for disconnection.
US 5,936,442 — "Power shut-off and recovery circuit for data communication devices":
the power control circuit de-asserts an ENABLE signal to turn off power when no ports are in operational mode, and re-asserts it when active ports are detected, based on repeatedly checking port status.
US 9,059,906 — "Data communication interface":
a controller module that monitors the status of a power line of a data port and issues different communication mode instructions depending on whether the power line has a first or second status (voltage threshold), routing either I2C or USB data lines accordingly.
Conclusion
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/ZAHID CHOUDHURY/Primary Examiner, Art Unit 2175
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