DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 is considered to be indefinite because the claim discloses a fourth wiring (line 6) without disclosing a third wiring. It is unclear what and where the third wiring is.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Degoirat (US Pat. Pub. No. US 2010/0227653 A1).
Regarding claim 1, Degoirat discloses a circuit 30 comprising: a current source I2 (or I1) electrically connected to a first voltage node Vss (or Vdd); a first metal-oxide semiconductor (MOS) transistor P1 (or N1) of a first type; a second MOS transistor N1 (or P1) of a second type electrically connected to a second voltage node Vdd (or Vss); a third MOS transistor P2 (or N2) of the first type; a first wiring connected to a gate of the first MOS transistor P1 (or N1) and a gate of the third MOS transistor P2 (or N2); and a wiring connected to a node between the gate of the first MOS transistor P1 (or N1) and the gate of the third MOS transistor P2 (or N2) and a node between the first MOS transistor P1 (or N1) and the current source I2 (or I1), wherein the current source I2 (or I1), the first MOS transistor P1 (or N1), and the second MOS transistor N1 (or P1) are arranged in sequence in an electrical path between the first voltage node Vss (or Vdd) and the second voltage node Vdd (or Vss), and wherein a current corresponding to a current which flows through the electrical path flows to the third MOS transistor P2 (or N2) (via the first wiring; Fig. 3).
Regarding claim 2, Degoirat discloses wherein a current value of the current which flows through the electrical path and a current value of the current which flows to the third MOS transistor P2 or N2 are approximately equal to each other (Fig. 3; inherently because of the wiring).
Regarding claim 3, Degoirat discloses wherein the first type is a P-type, the second type is an N-type, the second MOS transistor N1 is electrically connected to a source side of the first MOS transistor P1, and the current source I2 is electrically connected to a drain side of the first MOS transistor P1 (paragraphs [0028]-[0031] and [0035]-[0036]; Fig. 3).
Regarding claim 4, Degoirat discloses wherein the first voltage node Vss supplies a reference voltage to the current source I2, and the second voltage node Vdd supplies a power source voltage to the second MOS transistor N1 (Fig. 3).
Regarding claim 5, Degoirat discloses wherein the first type is an N-type, the second type is a P-type, the second MOS transistor P1 is electrically connected to a drain side of the first MOS transistor N1, and the current source I1 is electrically connected to a source side of the first MOS transistor N1 (Fig. 1).
Regarding claim 6, Degoirat discloses wherein the first voltage node Vdd supplies a power source voltage to the current source I1, and the second voltage node Vss supplies a reference voltage to the second MOS transistor P1 (Fig. 3).
Regarding claim 15, Degoirat discloses wherein the current source I2, the first MOS transistor P1, and the third MOS transistor P2 function as a current mirror circuit (paragraphs [0017], [0026], [0029] and [0036]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US Pat. Pub. No. US 2022/0329707 A1) in view of Degoirat.
Suzuki discloses a light-emitting device 28 comprising: a light-emitting region 38; and a circuit region 105 configured to drive the light-emitting region 38 (Figs. 8A and 9B), wherein the circuit region 105 includes a current mirror circuit (paragraphs [0026]-[0029] and [0039]).
Suzuki differs from the instant claimed invention in disclosing a detailed of the current mirror circuit.
Degoirat discloses a circuit 30 comprising: a current source I2 (or I1) electrically connected to a first voltage node Vss (or Vdd); a first metal-oxide semiconductor (MOS) transistor P1 (or N1) of a first type; a second MOS transistor N1 (or P1) of a second type electrically connected to a second voltage node Vdd (or Vss); a third MOS transistor P2 (or N2) of the first type; a first wiring connected to a gate of the first MOS transistor P1 (or N1) and a gate of the third MOS transistor P2 (or N2); and a wiring connected to a node between the gate of the first MOS transistor P1 (or N1) and the gate of the third MOS transistor P2 (or N2) and a node between the first MOS transistor P1 (or N1) and the current source I2 (or I1), wherein the current source I2 (or I1), the first MOS transistor P1 (or N1), and the second MOS transistor N1 (or P1) are arranged in sequence in an electrical path between the first voltage node Vss (or Vdd) and the second voltage node Vdd (or Vss), and wherein a current corresponding to a current which flows through the electrical path flows to the third MOS transistor P2 (or N2) (via the first wiring; Fig. 3).
Degoirat also discloses the current source I2, the first MOS transistor P1, and the third MOS transistor P2 functioning as a current mirror circuit (paragraphs [0017], [0026], [0029] and [0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the current mirror circuit as taught by Degoirat in place of the circuit of Suzuki to be capable of being powered with a low voltage and little sensitivity to the threshold variation of the MOS transistors forming it (Degoirat; paragraph [0015]).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki in view of Degoirat.
Suzuki discloses an image forming apparatus 36 comprising: a photosensitive member 27; a light-emitting device 28 arranged opposite the photosensitive member 27 and configured to expose the photosensitive member 27 to form a latent image on the photosensitive member 27 (paragraph [0053] and Fig. 9A); and a developing unit 31 configured to develop the latent image formed on the photosensitive member 27 with toner (paragraph [0053] and Fig. 9A), wherein the light-emitting device 28 comprises a light-emitting region 38, and a circuit region 105 configured to drive the light-emitting region 38 (Figs. 8A and 9B), and wherein the circuit region 105 includes a current mirror circuit (paragraphs [0026]-[0029] and [0039]).
Suzuki differs from the instant claimed invention in disclosing a detailed of the current mirror circuit.
Degoirat discloses a circuit 30 comprising: a current source I2 (or I1) electrically connected to a first voltage node Vss (or Vdd); a first metal-oxide semiconductor (MOS) transistor P1 (or N1) of a first type; a second MOS transistor N1 (or P1) of a second type electrically connected to a second voltage node Vdd (or Vss); a third MOS transistor P2 (or N2) of the first type; a first wiring connected to a gate of the first MOS transistor P1 (or N1) and a gate of the third MOS transistor P2 (or N2); and a wiring connected to a node between the gate of the first MOS transistor P1 (or N1) and the gate of the third MOS transistor P2 (or N2) and a node between the first MOS transistor P1 (or N1) and the current source I2 (or I1), wherein the current source I2 (or I1), the first MOS transistor P1 (or N1), and the second MOS transistor N1 (or P1) are arranged in sequence in an electrical path between the first voltage node Vss (or Vdd) and the second voltage node Vdd (or Vss), and wherein a current corresponding to a current which flows through the electrical path flows to the third MOS transistor P2 (or N2) (via the first wiring; Fig. 3).
Degoirat also discloses the current source I2, the first MOS transistor P1, and the third MOS transistor P2 functioning as a current mirror circuit (paragraphs [0017], [0026], [0029] and [0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the current mirror circuit as taught by Degoirat in place of the circuit of Suzuki to be capable of being powered with a low voltage and little sensitivity to the threshold variation of the MOS transistors forming it (Degoirat; paragraph [0015]).
Allowable Subject Matter
Claims 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: dependent claim 7 is allowable over the prior art of record because the prior art of record does not teach or suggest: “the third MOS transistor and the fourth MOS transistor are arranged in sequence in an electrical path between the load element and the second voltage node” as set forth in the claimed combination.
Other Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nishitoba et al. (US Pat. Pub. No. US 2002/0196212 A1) discloses in a current drive circuit that is applicable to organic EL image display device, the current drive circuit is provided for reducing the influence of variation between transistors that constitute a current mirror circuit while using the current mirror circuit.
Odagiri et al. (US Pat. Pub. No. US 2018/0074430 A1) discloses an image forming apparatus comprising: a light-emitting device; a photosensitive member; a developing unit; and a driver to drive the light-emitting device.
Saito et al. (US Pat. Pub. No. US 2023/0155498 A1) discloses a circuit comprising: first voltage node; a second voltage node; a first MOS transistor of a first type; a second MOS transistor of a second type electrically connected to the second voltage node; a third MOS transistor of the first type; and the first MOS transistor and the second MOS transistor being arranged in sequence in an electrical path between the first voltage node and the second voltage node.
Contact Information
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/SOPHIA S CHEN/Primary Examiner, Art Unit 2852
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February 27, 2026