DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the amendments filed on 01/21/2026. Claims 1, 9 and 16 have been amended.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 8, 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. [US 2020/0401514 A1] in view of Cho et al. [US 2013/0028018 A1] and in further view of Joe [US 2019/0267107 A1].
Claim 1 is rejected over Liang, Cho and Joe.
Liang teaches “A method comprising: receiving a read command directed a portion of memory;” as “ An SSD can receive commands from a host in association with memory operations, such as read or write operations to transfer data” [¶0007]
“determining a metric representing wear on the portion of memory;” as “According to some examples described herein, an adaptive GC engine may initiate or tune GC aggressiveness according to an estimated device age or life expectancy indicated by a current device wear metric.” [¶0023] (Wear metric is determined)
“determining a group of a plurality of groups to which the portion of memory belongs;” as “Word lines coupled to the gates of the unselected memory cells of each group are driven at a specified pass voltage (e.g., Vpass) to operate the unselected memory cells of each group as pass transistors (e.g., to pass current in a manner unrestricted by their stored data values). ” [¶0004] (Memory is grouped into word lines)
Liang does not explicitly teach determine a plurality of bitline voltages using the group;
determining a bitline voltage of the plurality of bitline voltages using the metric representing wear on the portion of memory; and
executing the read command using the bitline voltage.
However, Cho teaches “determine a plurality of bitline voltages using the group;” as “a second program operation and/or a third program operation may be performed by applying different bitline voltages VSS, VF1, VF2 and VF3 to a plurality of groups by using cell group information generated during a first program operation.” [¶0160]
Liang and Cho are analogous arts because they teach storage system and wear leveling or solid state memory.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Liang and Cho before him/her, to modify the teachings of Liang to include the teachings of Cho with the motivation of multiple bits of data may be stored by using multiple threshold voltage distributions to represent different logic states of multi-bit data. [Cho, ¶0003]
The combination of Liang and Cho does not explicitly teach determining a bitline voltage of the plurality of bitline voltages using the metric representing wear on the portion of memory; and
executing the read command using the bitline voltage.
However, Joe teaches “determining a bitline voltage of the plurality of bitline voltages using the metric representing wear on the portion of memory; and” as “ In an embodiment, the verify manager 120 determines the adjacent word line voltage or the bit line voltage based on the program-erase cycle count of the memory cell array 110.” [¶0042] (Based on metric data, bitline voltage is adjusted.)
“executing the read command using the bitline voltage.” as “The nonvolatile memory system includes: a memory controller outputting a command and an address to the nonvolatile memory device to access data in the nonvolatile memory device; ” [¶0009] (Execution of I/O command is recited)
Liang, Cho and Joe are analogous arts because they teach storage system and wear leveling or solid state memory.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Liang, Cho and Joe before him/her, to modify the teachings of combination of Liang and Cho to include the teachings of Joe with the motivation of improving a retention characteristic by taking into account a program state of an adjacent word line in a verify operation. [Joe, ¶0006]
Claim 8 is rejected over Liang, Cho and Joe.
Liang teaches “wherein the portion of memory comprises a wordline, each of the plurality of groups comprises a wordline group, and the group is a wordline group including the wordline.” as “The memory cells of the memory array are typically arranged in a matrix. In an example, the gates of each floating gate memory cell in a row of the array are coupled to an access line (e.g., a word line).” [¶0002]
Claim 9 is rejected over Liang, Cho and Joe under the same rationale or rejection of claim 1.
Claim 16 is rejected over Liang, Cho and Joe under the same rationale or rejection of claim 1.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 recites determining a sensing time of a plurality of sensing times using the metric representing wear on the portion of memory and the group, wherein executing the read command further uses the sensing time. Closest prior art Meir et al. [US 2012/0320672 A1] appears to teach the memory cells in the group are coupled to respective bit lines, reading using the first readout operation includes charging the bit lines and measuring a discharge of the bit lines with the first sense time, and reading using the second readout operation includes measuring the discharge of the bit lines with the second sense time without re-charging the bit lines. In an embodiment, the memory cells in the group are associated with a single word line. However, the prior art does not appear to teach or fairly suggest determining a sensing time from a plurality of sending times. Therefore, claim 2 and its dependent claims 3-6 are considered allowable and objected as they are dependent on rejected claim.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 recites wherein a first bitline voltage of the plurality of bitline voltages is mapped to the group and a first metric representing wear on the portion of memory, a second bitline voltage of the plurality of bitline voltages is mapped to the group and a second metric representing wear on the portion of memory, the first metric representing wear on the portion of memory is larger than the metric representing wear on the portion of memory, and the first bitline voltage is smaller than the second bitline voltage. The closest prior arts of record do not appear to teach or fairly suggest mapping of bitline voltages to the group of wear metrics. Therefore claim 7 is considered to contain allowable subject matter and objected as it is dependent on rejected claim.
Under the same above rationale, claims 10-14, 15, 17-19 and 20 are also objected.
Response to Arguments
Applicant’s arguments with respect to amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner noted the terminal disclaimed approved on 02/13/2026. Therefore, the double patenting rejections are withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132