DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15-17, 19-21, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park U.S. Patent Application Publication US2024/0419531A1 in view of Nagata et al. U.S. Patent Application Publication US2004/0208070A1.
As per claim 15, Park teaches a controller, comprising: a fault analysis module configured to analyze an error log to generate a fault address and a mode information signal when a specific fault mode is detected (¶ 0027-0028); and a fault management module configured to: during a first operation, store the fault address in a first storage circuit. and during a second operation, output a selected repair address from the second storage circuit according to a result of comparing stored fault addresses in the first storage circuit with an input address (¶ 0027-0028, 0040, 0031, 0046, 0055- wherein a received address is compared to an error log address and, if there is a match a signal is went to a swap circuit to replace the address with a corresponding repair address; ¶ 0056 teaches various circuits that receive input addresses, compare to fault addresses, and repair with a repair address). Nagata teaches while masking one or more bits of the fault address, and mask one or more bits of a repair address corresponding to the masked bits of the fault address, among a plurality of repair addresses pre-stored in a second storage circuit, according to the mode information signal (¶ 0061, 0085). It would have been obvious to one of ordinary skill in the art to use the process of Nagata in the process of Park. One of ordinary skill in the art would have been motivated to use the process of Nagata in the process of Park because using the process of Nagata would yield the predictable of matching redundant, repair rows to requested, faulty row addresses.
As per claim 16, Park teaches the controller of claim 15, wherein the error log is generated based on data output from a memory device, wherein the fault analysis module generates the mode information signal by detecting faults in two or more sub-word lines among a plurality of sub-word lines arranged in the memory device (¶ 0040, 0046).
As per claim 17, Nagata teaches the controller of claim 15, wherein the fault management module is configured to: mask one or more bits related to two or more sub-word lines, among bits of the fault address, according to the mode information signal, during the first operation (¶ 0060-0061).
As per claim 19, Nagata teaches the controller of claim 15, wherein the fault management module is configured to: set masked bits of the selected repair address by using bits of the input address corresponding to the masked bits of the fault address, during the second operation (¶ 0060-0061).
As per claim 20, Park teaches a fault management method, comprising: storing a fault address of a memory device in a first storage circuit according to a mode information signal indicating faults in two or more sub-word lines among a plurality of sub-word lines arranged in the memory device; masking one or more bits of a repair address corresponding to the masked bits of the fault address, among a plurality of repair addresses pre-stored in a second storage circuit, according to the mode information signal; searching for an input address from the first storage circuit; and outputting a selected repair address from the second storage circuit according to the search result (¶ 0027-0028, 0040, 0046, 0031, 0055-0056, see claim 15). Nagata teaches masking one or more bits of the fault address, and masking one or more bits of a repair address corresponding to the masked bits of the fault address, among a plurality of repair addresses pre-stored in a second storage circuit, according to the mode information signal (¶ 0061, 0085, see claim 15). It would have been obvious to one of ordinary skill in the art to use the process of Nagata in the process of Park. One of ordinary skill in the art would have been motivated to use the process of Nagata in the process of Park because using the process of Nagata would yield the predictable of matching redundant, repair rows to requested, faulty row addresses.
As per claim 21, Nagata teaches the fault management method of claim 20, wherein the masking one or more bits of the fault address includes: masking the one or more bits related to the two or more sub-word lines, among bits of the fault address, according to the mode information signal (¶ 0060- 0061).
As per claim 23, Nagata teaches the fault management method of claim 20, further comprising: setting, when the selected repair address is output, masked bits of the selected repair address by using bits of the input address corresponding to the masked bits of the fault address (¶ 0060-0061).
Allowable Subject Matter
4. Claims 1-14 are allowed.
5. Claims 18, 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. The following is an examiner’s statement of reasons for allowance: When read as a whole, claims 1-14 are allowed with respect to the following:
With respect to claim 1, the primary reason for allowance is the limitation of a mapping control circuit configured to control the first storage circuit to mask one or more bits of the received fault address according to a mode information signal indicating faults in two or more sub-word lines, among a plurality of sub-word lines arranged in the memory device, and to control the second storage circuit to mask one or more bits of a repair address corresponding to the masked bits of the received fault address.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
7. Applicant's arguments filed 4/28/26 have been fully considered but they are not fully persuasive.
With respect to claim 1, the applicant has argued on page 14 of the Remarks, dated 4/28/26:
Thus, Nagata does not teach or suggest masking controlled by a mapping control
circuit because the repair search circuit 30 is not a mapping control circuit of Claim 1. Instead, the repair search circuit 30 is more closely analogized to the first or second storage circuits.
Upon further consideration, the examiner concurs that Nagata lacks the structure of mapping control circuit that controls the first and second storage circuits to perform the limitation as claimed in the allowable subject matter, as stated above. However, this argued structure is not disclosed in claims 15 and 20, so those claim rejections are maintained.
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Citations cited in prior Office Action.
9. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER S MCCARTHY whose telephone number is (571)272-3651. The examiner can normally be reached Monday-Friday 8:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571)272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER S MCCARTHY/Primary Examiner, Art Unit 2113
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