DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 11-12. 15-17, 19-21, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park U.S. Patent Application Publication US2024/0419531A1 in view of Nagata et al. U.S. Patent Application Publication US2004/0208070A1.
As per claim 1, Park teaches a fault management device, comprising: a first storage circuit configured to receive and sequentially store a fault address of a memory device and to output a selection signal by comparing stored fault addresses with an input address; a second storage circuit configured to store repair addresses corresponding to the stored fault addresses to output a selected repair address corresponding to the selection signal (¶ 0027-0030, wherein the input (RA) address is compared to the stored repair addresses); and a mapping control circuit configured to control the first storage circuit and a mode information signal indicating faults (¶ 0031) in two or more sub-word lines, among a plurality of sub-word lines arranged in the memory device (¶ 0040, 0046). While Park teaches a masking logic (¶ 0068), he does teach to mask one or more bits of the received fault address and to mask one or more bits of a repair address corresponding to the masked bits of the received fault address. Nagata does teach to mask one or more bits of the received fault address and to mask one or more bits of a repair address corresponding to the masked bits of the received fault address (¶ 0061, wherein the input address is set to be masked if faulty and is correlated to the masked repair row addresses - ¶ 0085). It would have been obvious to one of ordinary skill in the art to use the process of Nagata in the process of Park. One of ordinary skill in the art would have been motivated to use the process of Nagata in the process of Park because using the process of Nagata would yield the predictable of matching redundant, repair rows to requested, faulty row addresses.
As per claim 2, Nagata teaches the fault management device of claim 1, wherein the mapping control circuit is configured to: control the first storage circuit to mask one or more bits related to the two or more sub-word lines, from among bits of the received fault address, according to the mode information signal (¶ 0060-0061, sub-word lines in Park see claim 1 ).
As per claim 4, Nagata teaches the fault management device of claim 1, wherein the mapping control circuit is configured to: set, when the selected repair address is output, masked bits of the selected repair address by using bits of the input address corresponding to the masked bits of the received fault address (¶ 0060-0061).
As per claim 11, Park teaches the fault management device of claim 1, wherein the memory device includes a plurality of cell blocks, wherein the mode information signal includes information on where faults occur in sub-word lines coupled to one main word line among a plurality of shared by cell blocks adjacent to a row direction (¶ 0037-0038). Nagata teaches wherein the mapping control circuit controls the first storage circuit to mask one or more bits designating the sub-word lines, among bits of the received fault address, according to the mode information signal (¶ 0061).
As per claim 12, Nagata teaches the fault management device of claim 11, wherein the mapping control circuit is configured to: set, when the selected repair address is output, masked bits of the selected repair address by using bits designating the sub-word lines, among bits of the input address (¶ 0060-0061, see claim 4).
As per claim 15, Park teaches a controller, comprising: a fault analysis module configured to analyze an error log to generate a fault address and a mode information signal when a specific fault mode is detected; and a fault management module configured to: during a first operation, store the fault address in a first storage circuit. and during a second operation, output a selected repair address from the second storage circuit according to a result of comparing stored fault addresses in the first storage circuit with an input address (¶ 0027-0028, 0040, 0031, 0046, see claim 1). Nagata teaches while masking one or more bits of the fault address, and mask one or more bits of a repair address corresponding to the masked bits of the fault address, among a plurality of repair addresses pre-stored in a second storage circuit, according to the mode information signal (¶ 0061, 0085). It would have been obvious to one of ordinary skill in the art to use the process of Nagata in the process of Park. One of ordinary skill in the art would have been motivated to use the process of Nagata in the process of Park because using the process of Nagata would yield the predictable of matching redundant, repair rows to requested, faulty row addresses.
As per claim 16, Park teaches the controller of claim 15, wherein the error log is generated based on data output from a memory device, wherein the fault analysis module generates the mode information signal by detecting faults in two or more sub-word lines among a plurality of sub-word lines arranged in the memory device (¶ 0040, 0046, see claim 1).
As per claim 17, Nagata teaches the controller of claim 15, wherein the fault management module is configured to: mask one or more bits related to two or more sub-word lines, among bits of the fault address, according to the mode information signal, during the first operation (¶ 0060-0061, see claim 2).
As per claim 19, Nagata teaches the controller of claim 15, wherein the fault management module is configured to: set masked bits of the selected repair address by using bits of the input address corresponding to the masked bits of the fault address, during the second operation (¶ 0060-0061, see claim 4).
As per claim 20, Park teaches a fault management method, comprising: storing a fault address of a memory device in a first storage circuit according to a mode information signal indicating faults in two or more sub-word lines among a plurality of sub-word lines arranged in the memory device; masking one or more bits of a repair address corresponding to the masked bits of the fault address, among a plurality of repair addresses pre-stored in a second storage circuit, according to the mode information signal; searching for an input address from the first storage circuit; and outputting a selected repair address from the second storage circuit according to the search result (¶ 0027-0028, 0040, 0046, 0031, see claim 1). Nagata teaches masking one or more bits of the fault address, and masking one or more bits of a repair address corresponding to the masked bits of the fault address, among a plurality of repair addresses pre-stored in a second storage circuit, according to the mode information signal (¶ 0061, 0085, see claim 1). It would have been obvious to one of ordinary skill in the art to use the process of Nagata in the process of Park. One of ordinary skill in the art would have been motivated to use the process of Nagata in the process of Park because using the process of Nagata would yield the predictable of matching redundant, repair rows to requested, faulty row addresses.
As per claim 21, Nagata teaches the fault management method of claim 20, wherein the masking one or more bits of the fault address includes: masking the one or more bits related to the two or more sub-word lines, among bits of the fault address, according to the mode information signal (¶ 0060- 0061).
As per claim 23, Nagata teaches the fault management method of claim 20, further comprising: setting, when the selected repair address is output, masked bits of the selected repair address by using bits of the input address corresponding to the masked bits of the fault address (¶ 0060-0061).
Allowable Subject Matter
Claims 3, 5-10, 13-14, 18, 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2016/0239379A1 to Fee et al.: Matching faulty addresses in word lines according to mask.
US 2025/0061055A1 to Sehgal et al.: Row failure masking.
US 2021/0124659A1 to Ryu et al.: Ignoring bits in redundant bit lines for row repair.
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/CHRISTOPHER S MCCARTHY/Primary Examiner, Art Unit 2113